JP3359987B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus having a buffer used for inputting or outputting data to be transmitted and received.

[0002]

2. Description of the Related Art Conventional DSP (Digital Signal Processe)
r) However, the usable capacity of the data buffer used for data transmission and reception is fixed in hardware such as 1 byte or 4 bytes, and the capacity used by software is not controlled. Was.
For this reason, all the capacity of the buffer prepared in hardware was used.

[0003]

Since the capacity of data that can be processed at one time differs depending on the type of the DSP, if the capacity of the data buffer used for data transmission and reception by the DSP is constant, the type of the DSP and the data It becomes very difficult to use depending on the combination of the buffer capacities. For example, when the DSP intends to process three pieces of data (for example, three bytes) in one process, if the capacity of the data buffer is two or four pieces (two bytes or four bytes), There was a problem that it was difficult to use.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide a data processing apparatus capable of changing the capacity of a data buffer according to the processing capacity of a single DSP. Aim.

[0005]

In order to achieve the above object, according to the first aspect of the present invention, a plurality of blocks of a predetermined bit unit are provided.
Each block has a predetermined order.
And the number of blocks used according to the amount of data
Determine the number of blocks and indicate the first block to be read first
Control means, and the location from the designated first block.
Blocks according to the number of used blocks based on a predetermined order
Selector for selecting and outputting data of the selected block
And the read state of the last block of the buffer.
Flag means for generating a read state flag
The last block of the buffer is the last block
The position of the first block is determined so that
The means determines the completion of reading of the last block from the flag.
When recognized, read the next data from the first block
I do.

[0006]

[0007]

According to the second aspect of the present invention, a plurality of blocks in a predetermined bit unit are provided, and each block determines the number of blocks to be used in accordance with a buffer having a predetermined order and a data capacity to be processed at one time. Control means for instructing a head block to be written first, write instructing means for selecting blocks from the instructed head block by the number of used blocks based on the predetermined order, and writing input data, Flag means for creating a write state flag in accordance with the write state of the last block, determining the position of the first block so that the last block of the buffer is the last block, and the control means When the completion of writing of the last block is recognized from the flag, the next input data is written from the first block.

[0009]

According to the first aspect of the present invention, a plurality of buffers constituting a buffer are provided.
According to the amount of data to be processed in one block
The number of used blocks is determined. When the control means indicates the first block to be used, the selector selects from the indicated block to the last block according to the ordering,
Output data to the block. As a result, it is possible to use a block of the buffer corresponding to one processing of the DSP. For example, the buffer is composed of 4 blocks and 1
If a block stores 1 byte of data, DS
When P processes 3 bytes at one time, the second to fourth blocks are used.

Further , a flag means is added so that a flag is displayed when the selector outputs the data of the last block.
This indicates that the output processing of the last block has been completed, so the control means writes the next data according to the order from the designated first block to the last block. Since the first block to be used is determined so that one processing data of the DSP is always used up to the last block, it is easy to detect the end of one processing, and the configuration of software for this detection Also becomes easier.

According to the second aspect of the present invention, the number of used blocks is determined according to the data capacity to be processed at one time from among a plurality of blocks constituting the buffer. When the control means designates a block to be written first, the write designation means selects a block from the designated block according to the ordering, and causes the input data to be written. As a result, the number of blocks corresponding to the amount of data processed by the DSP can be used. For example, the buffer is composed of four blocks, one block has a capacity of one byte, and the processing capacity of one DSP is three.
If it is a byte, the second block is designated as the first block, and blocks of 3 bytes from the second to the fourth can be used.

Further , a flag means is added to display that the write instruction means has written the input data in the last block. As a result, the end of the writing of the last block can be known, so that the control means can write the input data from the first written block to the last block. Since the first block to be used is determined so that one processing data of the DSP is always used until the last block, it is easy to detect the end of this one processing, and the software for this detection is used. The configuration is also easy.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing a transmission / reception data processing circuit of a DSP according to an embodiment of the present invention. FIG. 2 shows an internal structure of a parallel / serial converter (hereinafter, referred to as a P / S converter) in FIG. FIG. 3 is a block diagram showing an internal structure of a serial / parallel converter (hereinafter, referred to as an S / P converter) in FIG. In FIG. 1, 1 is a DSP, 2 is a P / S converter for converting a parallel signal to a serial signal, 3 is an S / P converter for converting a serial signal to a parallel signal, and 4 is a digital signal for converting a digital signal to an analog signal. / Analog conversion unit (hereinafter referred to as D / A conversion unit), 5 is an analog / digital conversion unit (hereinafter referred to as A / D conversion unit) that converts an analog signal to a digital signal, 6 is a transmission side analog line, Reference numeral 7 denotes a receiving-side analog line.

The P / S converter shown in FIG. 2 handles transmission data. 21 is a ring buffer for transmission data, DS
The data sent by P1 is written. The ring buffer 21 is composed of a plurality of blocks, each block being composed of 8 bits. In the present embodiment, 21a to 2
It is composed of four stages of 1d. Each of the blocks 21a to 21d is used in the order of a to d, and can be used in the order of d to a, so that it is called a ring buffer. In the present embodiment, use is started from one of the blocks a to d in accordance with the processing capacity of the DSP 1 at one time. Reference numeral 22 denotes a buffer for storing a value indicating which stage of the ring buffer 21 to use, and a DSP
Written by one. 23 is a buffer 2
When the value of 2 is input, the operation is performed by the sampling clock CLKA and the bit transmission clock CLKB.

A selector 24 selects one of the outputs of the blocks 21a, 21b, 21c, 21d based on the output of the counter 23. A P / S 25 converts the output of the selector 24 from a parallel signal to a serial signal. converter,
26 is the output of the counter 23, the sampling clock CL
This is a flag decoder that creates a status flag indicating the state of the ring buffer 21 based on KA, the bit transmission clock CLKB, and the like. As the status flag, a flag indicating "FULL" when data is written from the block at the stage specified in the ring buffer 21 to the block at the last stage, and a flag indicating "EMP" when data is read are used. . Reference numeral 27 denotes a tri-state buffer for the DSP 1 to read the flag generated by the flag decoder 26.
NCS is chip select, RD is read signal, W
T indicates a write signal, SOUT indicates transmission data, and RIN indicates reception data.

The S / P converter shown in FIG. 3 handles received data. 31 is a ring buffer for received data,
Data read by SP1 is written. The ring buffer 31 is composed of a plurality of blocks, each block being composed of 8 bits. In this embodiment, 31
a, 31b, 31c, and 31d. The blocks 31a to 31d are used in the order of a to d, and can be used in the order of d to a. In the present embodiment, use is started from one of the blocks a to d in accordance with the processing capacity of the DSP 1 at one time. Reference numeral 32 denotes a buffer for storing data indicating which block of the ring buffer 31 to use, and is written by the DSP 1. Reference numeral 33 denotes a counter and a decoder. The counter operates based on the data of the buffer 32 by the sampling clock CLKA and the bit reception clock CLKB, etc., decodes the output result and outputs the result to the ring buffer 31 and the flag decoder 35. The output of the counter indicates from which block the received data is to be written. Reference numeral 34 denotes an S / P converter that converts received data from a serial signal to a parallel signal and outputs the converted signal to the ring buffer 31. 35 is a counter, decoder output and sampling clock CLK
A, a flag decoder that creates a status flag such as “FULL” or “EMP” of the ring buffer 31 in response to the bit reception clock CLKB, etc., and a tri-state buffer 36 for the DSP 1 to read the flag data created by the flag decoder 35 It is.

FIG. 4 is a diagram for explaining the sampling clock CLKA and the bit transmission clock CLKB. The sampling clock CLKA is a clock having a period for sampling the audio signal, and the bit transmission clock CLKB
Is a clock for transmitting this bit when the sampled audio is displayed in, for example, 8 bits.

The P / S converter 2 configured as described above,
The operation of the S / P converter 3 will be described. First, data transmission by the P / S converter 2 shown in FIG. 2 will be described.
The DSP 1 determines the number of blocks to be used based on the amount of data processed at one time. If three bytes of data are processed at one time, three blocks of the ring buffer 21 are used. The value of DSP1 is stored in the buffer 22 (0 to 3HEX).
Is written, but if 3 blocks are used, 1HEX
(Hexadecimal number) is written. When the reset is released and the operation is started, the counter 23 reads the value stored in the buffer 22 by the sampling clock CLKA, and outputs this value and every time 1 is added thereto. Counter 2
The output value of 3 indicates the position of the block of the ring buffer 21. For example, when 0 is output, it is used from the block 21a, and when 1 is output, it is used from the block 21b. The output of the counter 23 is input to the selector 24, which selects a block based on the input value and outputs the selected block to the P / S converter 25. When the value of the counter 23 is counted up to 3HEX by the sampling clock CLKA, the value stored in the buffer 22 is read out again at the next sampling clock CLKA, and this value is output.
Hereinafter, a value obtained by adding 1 is output for each sampling clock CLKA. That is, assuming that the counter 23 reads 1 from the buffer 22, the selector 24 outputs the outputs 21b, 21c, 21d, 21b, 21c of the ring buffer 21.
21d and output to the P / S converter 25 in order.

In the flag decoder 26, the counter 2
3, a status flag for causing the DSP 1 to read the data read state of the ring buffer 21 is output from the sampling clock CLKA and the bit transmission clock CLKB, etc.
7 to the bus of DSP1. This status flag is stored in the last block 21 of the ring buffer 21.
It is created based on the state of d. That is, if the data of the block 21d is read by the selector 24, it means that all the data of the blocks 21b to 21d have been read. To decide how many blocks of the ring buffer 21 are to be used, the block of the stage to be used is decided and used until the last stage. Thus, the status flag can be created only by checking the last stage. It becomes possible.

Next, the operation of the S / P converter 3 shown in FIG. 3 when receiving data will be described. As in the case of the transmission, the DSP 1 first determines the data capacity to be processed at one time. Assuming that this value is 4 bytes, the ring buffer 31 uses 4 blocks. 0HEX (hexadecimal) in buffer 32
Write. The counter decoder 33 outputs the value 0 read by the sampling clock CLKA,
When 2, 3 are output, 0 is read from the buffer 32 again and output as 0, 1, 2, 3. Thereby, 31a, 31b, 31c, 31d, 31 are stored in the ring buffer 31.
The received data is taken in order as a, 31b, 31c, 31d. On the other hand, the received data converted by the S / P converter 34 is directed to all the blocks of the ring buffer 31, so whether or not to take in the data is determined by the output of the counter 33. In the flag decoder 35, the output of the counter decoder 33, the sampling clock CL
A status flag indicating the use status of the ring buffer 31 is created by KA, the bit reception clock CLKB, etc.
Driven to the bus of DSP1 by tristate buffer 36. The flag decoder 35 is the ring buffer 3
When the received data from the S / P converter 34 is read into the first final block 31d, a status flag is created that indicates that the received data has been read into all the blocks of the ring buffer 31.

In the above embodiment, the ring buffers 21 and 31 are used.
Has been described as being composed of four blocks, but the same operation is possible even if this number changes.

[0022]

As is clear from the above description, the present invention has a ring buffer composed of a plurality of blocks,
The buffer can be set so as to be used in accordance with the capacity processed by the DSP at one time. This makes it possible for the DSP to separately set the capacity of the buffer on the transmission side and the capacity of the buffer on the reception side, and it is possible to arbitrarily set the capacity according to the capacity to be used. Also, when determining the capacity of the buffer to be used, set the first stage block to be used and use it from the block to the last block to check the usage status of the last stage block. Therefore, a circuit for creating a status flag indicating this can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a transmission / reception data processing circuit of a DSP according to an embodiment;

FIG. 2 is a block diagram illustrating details of a parallel / serial conversion unit that performs data transmission;

FIG. 3 is a block diagram illustrating details of a serial / parallel conversion unit that performs data reception;

FIG. 4 is a diagram illustrating a sampling clock CLKA and a bit transmission clock CLKB.

[Explanation of symbols]

 1 DSP 2 parallel / serial converter 3 serial / parallel converter 21 ring buffer 22 buffer 23 counter 24 selector 25 P / S converter 26 flag decoder 27 tri-state buffer 31 ring buffer 32 buffer 33 counter decoder 34 S / P converter 35 Flag Decoder

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-155059 (JP, A) JP-A-54-124644 (JP, A) JP-A-7-21121 (JP, A) JP-A 8- 79310 (JP, A) JP-A-4-222985 (JP, A) JP-A-1-233514 (JP, A) JP-A-6-131256 (JP, A) JP-A-3-2194992 (JP, A) 57-123536 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 5/06 G06F 13/38 G11C 7/00 H04L 13/08

Claims (2)

(57) [Claims] A plurality of blocks each having a predetermined bit unit;
Each block is a buffer having a predetermined order, a number of blocks to be used is determined in accordance with a data capacity to be processed at one time, and control means for designating a head block to be read first, and A selector for selecting blocks by the number of used blocks based on a predetermined order and outputting data of the selected block; and a flag means for creating a read state flag in accordance with a read state of the last block of the buffer. Have,
The position of the first block is determined so that the last block of the buffer is the last block, and the control means reads the next data from the first block when recognizing completion of reading of the last block from the flag. A data processing device characterized by the above-mentioned. 2. It has a plurality of blocks of a predetermined bit unit,
Each block has a predetermined ordering buffer, the number of blocks to be used is determined according to the data capacity to be processed at one time, and control means for designating a first block to be written first, and Write instruction means for selecting blocks by the number of used blocks based on a predetermined order and writing input data, and flag means for creating a write state flag according to the write state of the last block of the buffer. When the position of the first block is determined so that the last block of the buffer is the last block, and the control means recognizes the completion of writing of the last block from the flag, the next input data of the next block is read from the first block. A data processing device for performing writing.