JPS60116150A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60116150A
JPS60116150A JP58224746A JP22474683A JPS60116150A JP S60116150 A JPS60116150 A JP S60116150A JP 58224746 A JP58224746 A JP 58224746A JP 22474683 A JP22474683 A JP 22474683A JP S60116150 A JPS60116150 A JP S60116150A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
polyimide resin
aluminum
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58224746A
Other languages
Japanese (ja)
Other versions
JPH0334651B2 (en
Inventor
Kazuyuki Shimada
和之 嶋田
Junichi Okamoto
準市 岡元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58224746A priority Critical patent/JPS60116150A/en
Publication of JPS60116150A publication Critical patent/JPS60116150A/en
Publication of JPH0334651B2 publication Critical patent/JPH0334651B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE:To directly mount on a transparent conductive film used for a liquid crystal panel by forming a conductive material made of photosensitive polyimide resin and conductive metal oxide powder on the aluminum electrode pad of an element chip higher than the passivation film. CONSTITUTION:Tin oxide power of antimony-dope is added at the prescribed ratio to varnish made of polyimide resin and solvent, dispersed in a ball mill, and painted. This is coated on a semiconductor chip, an aluminum pad 2 is exposed with photomask, the unexposed part is developed and removed to obtain a semiconductor device. With the device as a circuit substrate it is aligned on a transparent electrode formed on a glass of a liquid crystal panel as a circuit substrate, and the device is bonded from the back surface. At this time the transparent electrode is not necessarily metallized, but heated to completely cure the resin, thereby obtaining rigid bonding and electric coupling.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は各種電子機器に使用される半導体装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device used in various electronic devices.

従来例の構成とその問題点 従来、半導体装置を最も小さく回路基板に実装する手段
として半導体素子をチップで取扱う方法が各種考案され
ている。その一つとしてフリップチップがあシ、これは
半導体素子テップのtk部、すなわちアルミハツト上に
金属薄膜とハンダメッキにより突起電極(バンプ)を設
け、この半導体素子チップを回路基板上へフェイスダウ
ンで実装するものである。このフリップチップの製造は
まずアルミパッドを含む素子全面にブタンまたはクロム
などアルミと密着性の良好な金属を蒸着によって形成す
る。次に銅などの良導体を同一面に蒸着した後、フォト
レジストを全面にかけ先のアルミバンド部のみを除去し
下の金属を電極としてスズと鉛の電気メッキを適当な厚
みにメッキする。
2. Description of the Related Art Conventional Structures and Problems Conventionally, various methods have been devised for handling semiconductor elements in chips as a means of packaging semiconductor devices on circuit boards in the smallest size possible. One of these is the flip chip, in which protruding electrodes (bumps) are provided on the TK part of the semiconductor chip, that is, the aluminum hat, using a thin metal film and solder plating, and the semiconductor chip is mounted face down on the circuit board. It is something to do. To manufacture this flip chip, first, a metal that has good adhesion to aluminum, such as butane or chromium, is formed by vapor deposition over the entire surface of the device including the aluminum pads. Next, after depositing a good conductor such as copper on the same surface, photoresist is applied to the entire surface, only the aluminum band is removed, and tin and lead are electroplated to an appropriate thickness using the underlying metal as an electrode.

メッキ唆レジストヲ剥離して次にスズと鉛の部分にフォ
トレジストをかけ下地の金属膜をエツチングで除去する
。このフォトレジストを剥離後、スズと鉛のメッキ層全
溶融させハンダとする。このようにして作られた半導体
素子チップは回路基板に載置、加熱することによって回
路基板上の電極へハンダ付けされ、電気的結合が成され
る。この方法によれば蒸着法による薄膜形成、電気メッ
キによるハンダ形成、フォトリンによるレジスト膜形成
とエツチング等、複雑な工程を必要とすることと回路基
板上の電極と十分なハンダ付は強度を得るためハンダ量
を多く必要とし、アルミパッド間隔も200〜300ミ
クロンが必要となる。以上のようにフリップチップはチ
ップそのマ捷の実装面積となり高密度実装には有効な手
段である反面、先はどのように製造プロセスが非常に複
雑であるため製品歩ど捷りの低下やチップコストのアッ
プをまねく。一方、このフリップチップは半導体メーカ
ー側での処理が必要であり、ユーザー側では不可能であ
る。捷だ、フリップチップは回路基板上へハンダ付けに
よって実装するもので回路基板、例えば液晶パネルの如
きITO上へ直接実装する場合などは先にI T (J
 ’、Hハンダ付けできるようにメタライズしておかな
ければならず液晶パネル製造においてもパネルコストの
アップとなる。
After removing the plating resist, a photoresist is applied to the tin and lead parts, and the underlying metal film is removed by etching. After peeling off this photoresist, the entire tin and lead plating layer is melted to form solder. The semiconductor element chip thus produced is placed on a circuit board and heated to be soldered to the electrodes on the circuit board, thereby establishing an electrical connection. This method requires complicated processes such as thin film formation by vapor deposition, solder formation by electroplating, resist film formation and etching by photorin, and sufficient soldering to the electrodes on the circuit board provides strength. Therefore, a large amount of solder is required, and an interval between aluminum pads of 200 to 300 microns is required. As mentioned above, flip-chip is an effective means for high-density mounting because the mounting area of the chips can be varied, but on the other hand, the manufacturing process is extremely complicated, resulting in a decrease in product yield and chip This leads to an increase in costs. On the other hand, this flip chip requires processing by the semiconductor manufacturer and is not possible by the user. Well, flip chips are mounted on a circuit board by soldering, and when mounting directly on a circuit board, such as an ITO such as a liquid crystal panel, first
', H must be metalized to enable soldering, which increases panel costs in LCD panel manufacturing.

発明の目的 本発明は半導体素子チップのコスト低減と回路基板、特
に液晶パネルに使用される透明導電膜上ヘメタライズす
ることなく直接実装できる半導体装置を提供することを
目的とする。
OBJECTS OF THE INVENTION An object of the present invention is to reduce the cost of semiconductor element chips and to provide a semiconductor device that can be directly mounted on a transparent conductive film used in a circuit board, particularly a liquid crystal panel, without being metallized.

発明の構成 本発明は半導体不予チップのアルミ電極バンド部上に感
光性ポリイミド樹脂と導電性金属酸化物粉からなる導電
性塗料をパッシベーション膜よりも高く形成したことを
特徴とするものである。
Structure of the Invention The present invention is characterized in that a conductive paint made of a photosensitive polyimide resin and a conductive metal oxide powder is formed on the aluminum electrode band portion of a semiconductor chip to be higher than the passivation film.

実施例の説明 以下、本発明の実施例について説明する。まず、本発明
の特徴とする点について述べると、最も大きな特徴は導
電性樹脂によってバンプを形成し、樹脂の接着効果を利
用して回路基板の回路導体をメタライズすることなく電
気的1機械的に結合することである。感光性樹脂はアク
リレート化したポリイミド樹脂が良く、導体粉は酸化ス
ズ、酸化インジュウムの微粉末で粒子径が0.1ミクロ
ン以下のものが本発明で特に有効である。これは酸化ス
ズ、敵化インジュウムの微粉末は粒径が小さく元の波長
よりも小さいことから透光性を有し、感光性樹脂の光硬
化の障害とならないためである。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described. First, to describe the features of the present invention, the most significant feature is that bumps are formed using conductive resin, and by utilizing the adhesive effect of the resin, the circuit conductors of the circuit board can be electrically and mechanically processed without metallization. It is about joining. The photosensitive resin is preferably an acrylated polyimide resin, and the conductive powder is particularly effective in the present invention if it is a fine powder of tin oxide or indium oxide with a particle size of 0.1 micron or less. This is because the fine powder of tin oxide and indium oxide has a small particle size and is smaller than the original wavelength, so it has translucency and does not interfere with the photocuring of the photosensitive resin.

一般に良く用いられる金属粉はo、1ミクロン以下の微
粒子にすることは因難であるため本発明には使用できな
い。
Generally used metal powders cannot be used in the present invention because it is difficult to make them into fine particles of 1 micron or less.

次に不発明の一実施例について図面を用いて説明する。Next, an embodiment of the invention will be described with reference to the drawings.

図において、1はシリコン基板であり、このシリコン基
板1上には蒸着などの方法によりアルミパッド部2が形
成され、さらにプラズマナイトライドなどのパッシベー
ション膜3が形成されて半導体素子チップが構成されて
いる。また、上記アルミパッド部2上には感光性ポリイ
ミド樹脂と導電性金属酸化物粉からなる導電性塗料を塗
布して形成されるバンプ4が上記パッシベーション膜3
よく高く形成されている。
In the figure, 1 is a silicon substrate, and on this silicon substrate 1, an aluminum pad portion 2 is formed by a method such as vapor deposition, and a passivation film 3 such as plasma nitride is further formed to constitute a semiconductor element chip. There is. Further, bumps 4 are formed on the aluminum pad portion 2 by applying a conductive paint made of photosensitive polyimide resin and conductive metal oxide powder to the passivation film 3.
Well formed and high.

このような構成の半導体装置についての製造方法を以下
に述べる。まず、ポリイミド樹脂とm剤からなるワニス
の樹脂分100重量重量子ンチモンドープの酸化スズ粉
金40重量部ヲD口えボールミルで分散させ塗料化する
。これを半導体素子チップ上に厚みを5〜50ミクロン
になるよう塗布し、フォトマスクでアルミパッド部2を
露光し。
A method of manufacturing a semiconductor device having such a configuration will be described below. First, 100 parts by weight of a resin component of a varnish consisting of a polyimide resin and an m agent and 40 parts by weight of antimony-doped tin oxide powder were dispersed in a D-mouth ball mill to form a paint. This was applied onto a semiconductor element chip to a thickness of 5 to 50 microns, and the aluminum pad portion 2 was exposed using a photomask.

未露元部を現像除去して半導体装置を得る。この半導体
装置を回路基板として液晶パネルのガラス上に形成され
た透明電極上にアライメントした後、半導体装置の裏面
から360℃30 sec s ei kyg/c1r
iの条件にて接着させる。このとき透明電極のITOは
何らメタライズする必要もなく、加熱するこ、とによっ
て樹脂の硬化が完全となり、強固な接着と電気的結合が
得られる。バンプ4の高さは上記圧着時にこのバンプ4
に圧力が十分加わる高さがあれば良く、通常半導体素子
チップはプラズマナイトライドなどのパッシベーション
膜3で保護されているのが普通である。その厚みは0.
8〜1.0ミクロンであり、本発明によるバンプ4はこ
れ以上の厚み、理想的には回路基板の凹凸を吸収できる
厚みが必要であるっ具体的には各種基板について笑験の
結果、バンプ4の厚みは5ミクロン以上あj%は良好な
接続が得られることが明らかとなった。
The unexposed original portion is developed and removed to obtain a semiconductor device. After aligning this semiconductor device as a circuit board on a transparent electrode formed on the glass of a liquid crystal panel, the semiconductor device was heated at 360°C for 30 sec kyg/c1r from the back side of the semiconductor device.
Adhesion is made under the conditions of i. At this time, there is no need to metalize the ITO of the transparent electrode, and the resin is completely cured by heating, thereby providing strong adhesion and electrical connection. The height of the bump 4 is determined by the height of the bump 4 during the above crimping.
It is sufficient if the height is sufficient to apply sufficient pressure to the semiconductor element chip, and the semiconductor element chip is normally protected with a passivation film 3 made of plasma nitride or the like. Its thickness is 0.
8 to 1.0 microns, and the bump 4 according to the present invention needs to have a thickness greater than this, ideally a thickness that can absorb the unevenness of the circuit board.Specifically, as a result of experiments with various boards, the bump It has become clear that a good connection can be obtained when the thickness of No. 4 is 5 microns or more.

また、5ミクロン以上で50ミクロンの範囲が良くこれ
以上厚くなると、パッド間隔が例えば100ミクロン程
度になったときショートする危険性もある。これは露光
時の力・ぶり現象によりパターン精度が悪くなるためで
ある。
Further, if the thickness is greater than 5 microns, preferably in the range of 50 microns, there is a risk of short-circuiting when the pad spacing becomes, for example, about 100 microns. This is because the pattern accuracy deteriorates due to force and blur phenomena during exposure.

〔実施例〕〔Example〕

導電顔料の材料と配合を以下の通りとしボールミルで混
合9分散させ塗料化した。
The materials and composition of the conductive pigment were as follows, and they were mixed and dispersed in a ball mill to form a paint.

ポリイミド樹脂(東しく株)フォトニース)・・・・・
・100重量部 酸化スズ粉(三菱金属(株)T−1) ・・・・・361量部 この塗料をスピンナーでCMO8が形成された4インチ
ウェハー上に厚み10ミクロンになるようにコーティン
グし86℃60分の予備乾燥した。
Polyimide resin (Toshiku Co., Ltd. Photonice)...
・100 parts by weight of tin oxide powder (Mitsubishi Metals Co., Ltd. T-1) ...361 parts This paint was coated with a spinner on a 4-inch wafer on which CMO8 was formed to a thickness of 10 microns. Preliminary drying was performed at ℃ for 60 minutes.

このウェハーにフAトマスクを密着露′X、(120W
/cr;tUVランプで20秒)し、末路光部全現像除
去した。さらにウェハーを100℃60分の乾燥した後
、ダイシングソーでで所定のチップ寸法に切断し完成半
導体装置とした。この半導体装置を回路基板としてカラ
ス上の透明電極で形成した回路パターンにアライメント
した後、半導体装置の裏面から400℃+ 30 Kg
/cnt 、 30秒の条件でガラス板に圧着すると同
時に篭気的接続を行った。この時のチップサイズは5n
++++角でパッド数64で横方向の押し強度はs、9
1y、垂直方向の引張り強度は2.’IKgであった。
A photomask was closely exposed to this wafer, (120W
/cr; tUV lamp for 20 seconds), and the end-light area was completely developed and removed. Further, the wafer was dried at 100° C. for 60 minutes, and then cut into a predetermined chip size using a dicing saw to obtain a completed semiconductor device. After using this semiconductor device as a circuit board and aligning it with a circuit pattern formed with transparent electrodes on a glass, the semiconductor device was heated at 400°C + 30 kg from the back side.
/cnt for 30 seconds, and at the same time, air-cage connection was performed. The chip size at this time is 5n
+++++ corner, number of pads is 64, horizontal push strength is s, 9
1y, the tensile strength in the vertical direction is 2. 'It was IKg.

回路’f:1tL気的動作さぜたところ所定の動作であ
ることを確認した。
Circuit 'f: 1tL operation was performed and it was confirmed that the circuit operated as specified.

発明の効果 本発明は導電性でしかも感光性を有する塗料をウェハー
上に一定厚み塗布しアルミノ(ノド部に)くンプを形成
した構成であり、この半導体装置を回路是板に熱圧着す
ることによって良好な接着と接続か得られる。この方法
によれば液晶ノくネルのようなガラス上に透明導電薄へ
メタライズすることなく直接実装することカニ可能とな
る。さらに簡単なプロセスによってノくンブ力二ノ形成
できコストの大巾な低減が可能となることと、特殊な技
術を必要としないため今1で半導体メーカー倶11で処
理しなければならなかったノくンブ技術−ユーザー倶1
1で処形成できるようになったことは合成の半導体産業
に貢献するものである。
Effects of the Invention The present invention has a structure in which a conductive and photosensitive paint is applied to a certain thickness on a wafer to form an alumino bump (at the throat), and this semiconductor device is thermocompression bonded to a circuit board. A good adhesion and connection can be obtained. According to this method, it is possible to directly mount the device on glass such as a liquid crystal panel without metalizing it into a transparent conductive thin film. In addition, it is possible to form a semiconductor chip using a simple process, which enables a significant reduction in costs, and because it does not require special technology, it is possible to form a semiconductor chip using a simple process. Mbu Technology - User 1
The fact that it has become possible to form a composite semiconductor in the first step will contribute to the synthetic semiconductor industry.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は不発明の半導体装置の一実施911を示す断面図
である。 1・・・・・・シリコン基板、2・・・・・・アルミ/
<ラド音b13・・・・・ハノシベーシジン膜、4・・
・・・/(ンフ1゜/″j ニン、っ−ア 42
The drawing is a cross-sectional view showing one embodiment 911 of the semiconductor device according to the invention. 1...Silicon substrate, 2...Aluminum/
<Rad sound b13... Hanoshibasidin membrane, 4...
.../(nfu1゜/″j nin, a-a42

Claims (1)

【特許請求の範囲】[Claims] 半導体素子チップの電極パッド部上に感光性ポリイミド
樹脂と導電性金属酸化物粉からなる導電性塗料によるバ
ンプをパッシベーション膜よリモ高く形成したことを特
徴とする半導体装置。
A semiconductor device characterized in that bumps made of a conductive paint made of photosensitive polyimide resin and conductive metal oxide powder are formed on the electrode pads of a semiconductor element chip at a height higher than a passivation film.
JP58224746A 1983-11-29 1983-11-29 Semiconductor device Granted JPS60116150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224746A JPS60116150A (en) 1983-11-29 1983-11-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224746A JPS60116150A (en) 1983-11-29 1983-11-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS60116150A true JPS60116150A (en) 1985-06-22
JPH0334651B2 JPH0334651B2 (en) 1991-05-23

Family

ID=16818584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224746A Granted JPS60116150A (en) 1983-11-29 1983-11-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60116150A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61287625A (en) * 1985-05-29 1986-12-18 Kaneko Agricult Mach Co Ltd Grain filling device in grain drying machine
JPS63181450A (en) * 1987-01-23 1988-07-26 Matsushita Electric Ind Co Ltd Bump for semiconductor device and its manufacture

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50139692A (en) * 1974-04-24 1975-11-08
JPS5650539A (en) * 1979-09-29 1981-05-07 Sharp Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50139692A (en) * 1974-04-24 1975-11-08
JPS5650539A (en) * 1979-09-29 1981-05-07 Sharp Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61287625A (en) * 1985-05-29 1986-12-18 Kaneko Agricult Mach Co Ltd Grain filling device in grain drying machine
JPH0258173B2 (en) * 1985-05-29 1990-12-07 Kaneko Agricult Machinery
JPS63181450A (en) * 1987-01-23 1988-07-26 Matsushita Electric Ind Co Ltd Bump for semiconductor device and its manufacture

Also Published As

Publication number Publication date
JPH0334651B2 (en) 1991-05-23

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