JPS60116147A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60116147A
JPS60116147A JP22311783A JP22311783A JPS60116147A JP S60116147 A JPS60116147 A JP S60116147A JP 22311783 A JP22311783 A JP 22311783A JP 22311783 A JP22311783 A JP 22311783A JP S60116147 A JPS60116147 A JP S60116147A
Authority
JP
Japan
Prior art keywords
film
electrode
groove
insulating film
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22311783A
Other languages
Japanese (ja)
Inventor
Nobuyuki Kajiwara
梶原 信之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22311783A priority Critical patent/JPS60116147A/en
Publication of JPS60116147A publication Critical patent/JPS60116147A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form a 2-layer electrode structure without problem of step coverage by selectively etching a conductor film with a resist film on the conductor film as a mask as the first electrode to form a groove, and forming the second electrode in the groove. CONSTITUTION:After forming an insulating film 2 in the prescribed thickness on a semiconductor substrate 1, a conductor film 3 made of aluminum or gold is formed on the film 2. A resist is coated on the film 3, exposed to be developed to form a resist film 4 of the prescribed pattern. With the film 4 as a mask the film 3 is selectively etched as the first electrode, and the film 2 is selectively etched to form a groove 5. Then, the second electrode 6A is formed in the groove 5 by depositing method, and a conductor film 6B is simultaneously formed on the film 4. Further, an interlayer insulating layer 7A is formed on the electrode 6A to bury the groove 5 with an insulating material by sputtering method, and an insulating film 7B is also formed on the film 6A. Then, the films 4, 6B, 7B are removed to obtain a 2-layer electrode structure.

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は、半導体装置の調造方法、よシ詳しく述べるな
らば、半導体装置の多層配線(電極)構造に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for preparing a semiconductor device, and more specifically, to a multilayer wiring (electrode) structure of a semiconductor device.

rh)従*姑缶J−聞鞘占 半導体装置、特に、電荷結合デノくイス(CCD)の多
層(2層)電極構造では、まず下層電極を絶縁膜上に形
成し、次に層間絶縁膜を形成してから上層電極を形成し
ていた。このように層間絶縁膜および上層m極を形成す
る際には、段差でのステップカバーレジが問題となシ、
層間絶縁膜が局部的に薄くなったシ、上層電極も局部的
に薄くな)場合によっては断線することがある。さらに
、第3層目の電極を形成する場合にはステップカバーレ
ジがもつとうまくいかない恐れがある。
rh) In a multilayer (two-layer) electrode structure of a semiconductor device, especially a charge-coupled device (CCD), a lower electrode is first formed on an insulating film, and then an interlayer insulator is formed on the insulating film. After forming the film, the upper layer electrode was formed. When forming the interlayer insulating film and the upper layer m-pole in this way, step cover registration at the step is a problem.
If the interlayer insulating film becomes locally thin, or the upper layer electrode also becomes locally thin, the wire may break. Furthermore, when forming a third layer of electrodes, there is a risk that the step cover registration will not work properly.

(C) 発明の目的 本発明の目的は、半導体装置の2層電極構造をステップ
カバーレジのトラブルなく形成することである。
(C) Object of the Invention An object of the present invention is to form a two-layer electrode structure of a semiconductor device without the trouble of step cover registration.

本発明の別の目的は、2層電極構造を容易にかつセルフ
ァラン的に形成し、そして上1層電極の表面でもってl
tl¥平坦な平面とすることのできる半導体装置の製造
方法を提案することである。
Another object of the present invention is to easily form a two-layer electrode structure in a self-contained manner, and to form a two-layer electrode structure in a self-contained manner.
The object of the present invention is to propose a method for manufacturing a semiconductor device that can produce a flat surface.

(d) 発明の構成 上述の目的が、半導体基板上の絶縁膜の上に導体膜を形
成し、この導体膜の上に所定ノくターンのマスク膜を形
成し、この導体膜の上に所定ノくターンのマスク膜を形
成し、マスク膜に覆われていない導体膜をエツチングし
て第1電極を形成し、さらに絶縁膜をエツチングして溝
を形成し、この溝内に第2電極を次に層間絶縁膜を形成
し、そして。
(d) Structure of the Invention The above-mentioned object is to form a conductor film on an insulating film on a semiconductor substrate, to form a mask film with a predetermined number of turns on the conductor film, and to form a mask film with a predetermined number of turns on the conductor film. A mask film with a cross-section is formed, the conductive film not covered by the mask film is etched to form a first electrode, the insulating film is further etched to form a groove, and a second electrode is formed in this groove. Next, an interlayer insulating film is formed.

マスク膜を除去することを含んでなる半導体装置の製造
方法によって達成される。
This is achieved by a method for manufacturing a semiconductor device that includes removing a mask film.

本発明に係る製造方法では、第1電極(上j惜′−極)
のパターニングのだめのマスク膜を利用してセルファラ
イン的に第2−tit、極(°上層電極)および眉間絶
縁膜を絶縁膜の溝内に形成し、マスク膜の除去と同時に
その一ヒの不用の第2・1上極形成時の導体膜および不
用の絶縁膜をリフトオフ的に除去する。
In the manufacturing method according to the present invention, the first electrode (upper electrode)
The second-tit, pole (° upper layer electrode) and glabella insulating film are formed in the groove of the insulating film in a self-aligned manner using the mask film of the patterning stage, and at the same time the mask film is removed, the need for that part is eliminated. The conductive film and unnecessary insulating film during the formation of the second and first upper electrodes are removed in a lift-off manner.

(e) 発明の実7バξ例 以下、添付図面を参照して、本発明の実施・2一様例に
よって本発明の詳細な説明する。
(e) EXAMPLES OF THE INVENTION Hereinafter, the present invention will be described in detail by way of example embodiments of the present invention, with reference to the accompanying drawings.

半導体装置の21i4 ′r’ri極を形成するために
、第1図に示すように、半導体基体(例えば、Si基板
、G a A s基板)1の上に絶縁膜(例えば、5i
02膜、Si3N4 膜)2を所定の厚さに形成した後
で、導体膜3を絶縁膜2上に形成する。この導体膜3の
材料はアルミニウム、金、ドープされたポリシリコン、
高融点金属シリサイドなどである。この導体膜3の上に
レジストを塗布し、露光現像して所定パターンのレジス
ト膜4を形成する。
In order to form a 21i4'r'ri pole of a semiconductor device, as shown in FIG.
After forming the 02 film and the Si3N4 film 2 to a predetermined thickness, the conductor film 3 is formed on the insulating film 2. The material of this conductor film 3 is aluminum, gold, doped polysilicon,
These include high melting point metal silicides. A resist is applied onto this conductive film 3, and exposed and developed to form a resist film 4 in a predetermined pattern.

レジスト膜4をマスクとして導体膜6を、第2図に示す
ように、適切なエッチャントで選択的にエツチングして
gl ′4極(上1m電極)とし、さらに別なエッチャ
ントで絶縁膜2を選択エツチングして湾5を形成する。
Using the resist film 4 as a mask, the conductive film 6 is selectively etched with an appropriate etchant to form the gl' quadrupole (upper 1 m electrode), as shown in FIG. 2, and the insulating film 2 is further selected with another etchant. Etch to form bay 5.

この溝5の深さは後述の第2電極を形成しても@1は極
と接触することのない深さである。この絶縁膜のエツチ
ングにはりアクティブイオンエツチングを採用すること
が好ましい。
The depth of this groove 5 is such that even if a second electrode (described later) is formed, it will not come into contact with the electrode. It is preferable to use active ion etching for etching this insulating film.

次に、第6図に示すように、蒸着法、スパッタリング法
などによって導゛成材料(例えば、アルミニウム、金、
高融点金属シリサイドなど)で溝5内に第2−極(下)
Ca 電極)6ノ℃を形成し、同時にレジスト膜4上に
導体膜6Bを形成する。
Next, as shown in FIG. 6, a conductive material (for example, aluminum, gold,
The second electrode (bottom) is made of high melting point metal silicide, etc.) in the groove 5.
A conductor film 6B is formed on the resist film 4 at the same time.

さらに、第4図に示すように、スパッタリング法、化学
的気相成長法などによって絶縁材料(例えば、5L02
,5i5N4など)で溝5内を埋めるように第2fi極
6A上にj督間絶縁膜7Aを形成し、同時に、導体膜6
A上も絶縁膜713を形成する。
Furthermore, as shown in FIG. 4, an insulating material (for example, 5L02
, 5i5N4, etc.) is formed on the second fi electrode 6A so as to fill the inside of the groove 5.
An insulating film 713 is also formed over A.

特に、眉間絶縁膜7Aの表1″Aiが第1電極3の表面
とほぼ同じレベルとなるようにその厚さを制御すること
が望ましい。
In particular, it is desirable to control the thickness so that the surface 1''Ai of the glabella insulating film 7A is approximately at the same level as the surface of the first electrode 3.

次に、レジスト膜4を適切な溶剤でもって除去すると、
その上の導体膜6Bおよび絶縁膜7Bをもリフトオフ的
に除去することができ、氾5図(C示すような、・2層
電極;[造が得られる。3第11.・葎3と層間絶縁膜
7Aとがほぼ平坦な表面を形成することができる。
Next, when the resist film 4 is removed with an appropriate solvent,
The conductive film 6B and the insulating film 7B on top of it can also be removed in a lift-off manner, resulting in a two-layer electrode structure as shown in Figure 5 (C). The insulating film 7A can form a substantially flat surface.

(f) 発明の効果 本発明によれば、上層電極を先に形成してからセルファ
ライン的に下、+音奄極を形成しており、ステップカバ
ーレジの問題はない。得られる21M1ff極橢浩の表
面は丹t〒平也であh、ビ、賽らにイ叶加電極(配線)
を形成しようとする場合に有益である。
(f) Effects of the Invention According to the present invention, the upper layer electrode is formed first and then the lower + sound electrode is formed in a self-aligned manner, so there is no problem with step cover registration. The surface of the resulting 21M1ff extra-thickness is 21M1ff, and the electrodes (wiring) are
This is useful when trying to form a .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第5図は、本発明に係る半導体装置の製造
方法による工種を説明する半導体装置の概略断面である
。 1・・・半導体基板 2・・・絶縁膜 6・・・導体膜(第1電極) 4・・・レジスト膜 5・・・溝 6A・・・Hジ2電極 7A・・・層間絶縁1嘆 特許出願人 富士通株式会社 特許出願代理人 弁理士 青 木 朗 弁理士 西 舘 オロ 之 弁理士内田幸男 弁理士 山 口 昭 之 第1図 乙 ] 第2図 シ「73 図 B Δ54図 第5図
1 to 5 are schematic cross-sections of a semiconductor device for explaining the types of work performed by the method of manufacturing a semiconductor device according to the present invention. 1...Semiconductor substrate 2...Insulating film 6...Conductor film (first electrode) 4...Resist film 5...Groove 6A...H diode 2 electrode 7A...Interlayer insulation 1 layer Patent Applicant: Fujitsu Limited, Patent Application Agent, Patent Attorney: Akira Aoki, Patent Attorney, Oro Nishidate, Patent Attorney, Yukio Uchida, Patent Attorney, Akira Yamaguchi (Fig.

Claims (1)

【特許請求の範囲】 1、半導体基板上の絶縁膜の上に導体膜を形成し、この
導体膜の上に所定パターンのマスク膜を形成し、前記マ
スク膜に覆われていない前記導体膜をエツチングして第
1電極を形成し、さらに前記絶縁膜をエツチングして溝
を形成し、この溝内に第2電極を次に層間絶縁膜を形成
し、そして前記マスク膜を除去することを含んでなるこ
とを特徴とする半導体装置の製造方法。 2、前記マスク膜がレジストであることを特徴とする特
許請求の範囲第1項記載の方法。
[Claims] 1. A conductor film is formed on an insulating film on a semiconductor substrate, a mask film of a predetermined pattern is formed on the conductor film, and the conductor film not covered with the mask film is etching to form a first electrode, further etching the insulating film to form a groove, forming a second electrode in the groove, then forming an interlayer insulating film, and removing the mask film. A method for manufacturing a semiconductor device, characterized in that: 2. The method according to claim 1, wherein the mask film is a resist.
JP22311783A 1983-11-29 1983-11-29 Manufacture of semiconductor device Pending JPS60116147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22311783A JPS60116147A (en) 1983-11-29 1983-11-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22311783A JPS60116147A (en) 1983-11-29 1983-11-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60116147A true JPS60116147A (en) 1985-06-22

Family

ID=16793083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22311783A Pending JPS60116147A (en) 1983-11-29 1983-11-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60116147A (en)

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