JPS60113464A - Manufacture of semiconductor ic device - Google Patents

Abstract

PURPOSE:To reduce the processes of information writing by a method wherein the first threshold voltage is changed to the second one by irradiating a MISFET having the first threshold voltage with X-ray excellent in permeability. CONSTITUTION:After a mask 19 is formed, the entire surface is irradiated with X rays, and thus the threshold voltage of the MISFET other than at the part covered with the mask, i.e., MISFETQ12 is so controlled as to become a desired value e.g. approx. 0.5V. The threshold voltage of the n-channel MISFET is reduced by X ray irradiation. Thereby, in the channel-forming part 20 of the MISFETQ12, threshold voltages over 5V whereby this device does not turn on even when for example an operating voltage of approx. 5V is impressed on the gate electrode can be obtained. In the channel-forming part of the other MISFET, a threshold voltage e.g. of approx. 0.5V whereby this device turns ON when an operating voltage of approx. 0.5V is impressed on the gate electrode can be obtained.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as
This technology relates to a semiconductor integrated circuit device equipped with an MI 5FET (MI 5FET), and is particularly effective when applied to a semiconductor integrated circuit device equipped with a read-only memory function (hereinafter referred to as ROM (Read Only Memory)). It is related to.

[Background technology]

A semiconductor integrated circuit device equipped with a mask ROM can store information in the mask ROM portion. Therefore, it is possible to provide a semiconductor integrated circuit device having various information and meeting various demands to customers.

On the supply side of semiconductor A-product circuit devices, it is preferable that the time required to complete the product (hereinafter referred to as "turn around time") be as short as possible in order to quickly meet the demands of consumers.

As a way to shorten this one completion time,
130963. Japanese Unexamined Patent Publication No. 56-130975 has been proposed. This is because after the process of forming the gate electrode, source region, and drain region that constitutes the MI 5FET,
In this method, using ion implantation technology, a predetermined impurity is introduced into the channel forming part through the gate electrode, the threshold voltage of the MISFET is varied, and information is written.

However, in the method, M I S FE
There is a problem in that information cannot be imprinted after the wiring formation step after the gel electrode, source region, and drain region forming the T. This is due to the causes explained below. In order to introduce impurities for writing information into the channel region, extremely large energy is required to pass through the gate electrode. When impurities with this energy are introduced into the channel region, crystal defects occur in that region. In order to remove these crystal defects, a high-temperature, long-time annealing process is required. That is, since semiconductor integrated circuit devices generally use aluminum (An) as a wiring material, an annealing process at a temperature higher than the melting temperature of the wiring material must be performed before the wiring formation process.

Based on this technology, as a result of the inventor's experiments and repeated studies, the inventor has discovered that by X-ray irradiation,
We discovered that the threshold voltage of MISFET varies.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a technique that can shorten the time required to write information in a semiconductor integrated circuit device equipped with a mask ROM.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by irradiating the MISFET having the first threshold voltage with highly transparent X-rays, the MISFET
Since the first threshold voltage of ET can be changed to the second threshold voltage, information can be written in the final stage of the manufacturing process of a semiconductor integrated circuit device equipped with a mask ROM, and one completion can be achieved. It's about shortening it.

Hereinafter, the configuration of the present invention will be described in detail together with examples.

[Example I]

In this example, a MISFET having a first threshold voltage
A description will be given using a semiconductor integrated circuit device including a mask ROM in which information is configured by a MISF"ET having a second threshold voltage and a MISF"ET having a second threshold voltage.

In all the figures, parts having the same functions are designated by the same reference numerals, and repeated explanations will be omitted.

The present invention utilizes a completely new principle to realize MISFET
First, the principle will be explained.

The threshold voltage [Vth] of MI 5FET can be expressed by the following equation.

Here, φM8' Work function between gate electrode and silicon 08g' Interface charge between silicon and oxide film Oo: Gate capacitance per unit area φf: Fermi potential QB: Induced in the surface depletion layer by ionized donor atoms This is the electric charge.

The present inventor has developed a p-channel MISFET and an n-channel MISFET, each having a predetermined threshold voltage, by X-ray irradiation.
The fact that the predetermined threshold voltage of the FET will be a higher threshold voltage and the predetermined threshold voltage of an n-channel MI 5FET will be a lower threshold voltage has been demonstrated experimentally. confirmed. The inventor presumes that this fact is due to the reasons explained below.

That is, when the MISFET is irradiated with X-rays'1-, the MISFET
Electrons in the gate P edge film (S NO!) constituting the SFET are ejected from inside, forming a deep trap level in the forbidden band of the gate insulating film. As a result, the second term of Ishibe in equation (1) above (QSIJ
Ilon) varies.

Therefore, the principle of the present invention is to control a p-channel MISFET with a predetermined threshold voltage to a higher threshold voltage by X-ray irradiation, and control an n-channel MISFET with a predetermined threshold voltage with X-rays. The method is to control the threshold voltage to be lower than that by irradiation.

In this embodiment, a semiconductor integrated circuit device including a horizontal ROM using an n-channel MI 5FET as a ROM storage element will be described.

FIG. 1 is a schematic circuit diagram of a ROM for explaining one embodiment of the present invention.

In Figure 1, Q u~Q, 1ne Qt+~Q2o
...is an enhancement type n-channel MISFE
T, and is for configuring a memory function as a memory element. MA is M I S F E T Qu~Q
1 (1*Q, +~Q2n...) is a memory array arranged in a matrix. 1 is an X decoder, 2 is an X decoder, and complementary insulated gate field effect transistors [ Below, OMI S (Oomple
-mentary MI 5FET)].

WL is a plurality of word lines extending in rows from one side of the X decoder 1 (the extending direction of the word lines is referred to as the row direction), and MI SFE T Q II arranged in the row direction
+ Qvt + Q+ 21 Qvt +... is electrically connected to a predetermined gate electrode. Word line WL
An operating voltage is applied to QN of a predetermined Ml 8FETQ. Reference numeral 3 denotes a sense amplifier, which amplifies and outputs a voltage serving as information applied to a common data line, which will be described later. OD is a common data line and is used to apply a voltage serving as information. DL has a plurality of data lines extending in a column (the direction in which the data lines extend is referred to as the column direction), and one end of each is connected to the
MISFETs Q, 1 to Q 1 electrically connected to the common data line OD and having their other ends arranged in the column direction
It is electrically connected to the drain region of HI Q, ~Q2o. The gate electrode of the column switch MISFET Q8 is electrically connected to the X decoder 2. MISFET Q++ ~Q1n, Q2, ~Q arranged in column direction
The source regions 2o are commonly grounded in the column direction.

Such a ROM has a first threshold voltage that turns on when an operating voltage is applied to each gate electrode.
Q2o and O when the operating voltage is applied to the gate electrode.
Nt, and M I S F E TQ+2 having a second threshold voltage higher than the first threshold. For example, when MISFETQ++ is selected, the ground potential is read by the sense amplifier 3, and the
When SF"ETQ+2 is selected, the potential applied to the data line DL is read out by the sense amplifier 3. In other words, the ROM is connected to MIs with different threshold voltages.
Various information can be obtained by combining 5FETs.

Next, a specific manufacturing method of this example will be explained.

Figures 2-2 (D are cross-sectional views of main parts of a semiconductor integrated circuit device equipped with a ROM in each manufacturing process for explaining a specific manufacturing method of Example I of the present invention; Figures 3 to 3 are plan views of main parts of a semiconductor integrated circuit device equipped with a ROM in each manufacturing process for explaining the specific manufacturing method of Example 2 of the present invention. (5)～
The sectional view of the main part shown in Figure 2) is shown on the left side of the MISFE.
TQ+□ is shown, and the diagram on the right shows peripheral circuits, for example, OMIS that constitutes X decoder 1 and Y decoder 2.

The main part plan view shown in Figure 3 (A) ~ 3rd issue is MISF
ETQo~Q1n, Q! I-Q2n is the main part of the memory array arranged in a matrix, and the part showing MISFETQ+□ in FIG. 2 (3) to FIG. 3 CB+ is 1]-■
FIG. In addition, in FIG. 3(5) to FIG. 30, in order to make the drawings easier to see, the interlayer insulating film that should be provided between each wiring layer is not shown.

First, in order to construct a semiconductor integrated circuit device, an n-fj4 semiconductor substrate 4 made of silicon (8i) single crystal is prepared. A p-type well region 5 is provided on a predetermined main surface portion of this semiconductor substrate 4 in order to configure an n-channel MISFET.
selectively formed. This is, for example, 8X10′2[
boron (B) ion impurity of about [atomic atoms/Cml],
75 [The impurities may be selectively introduced using an ion implantation technique with an energy of approximately KeV3, and the introduced impurities may be stretched and diffused.

After this, a field insulating film 6 is formed to electrically isolate the MISFETs and the like. σ) The field insulating film 6 is formed by selective thermal oxidation technology of the substrate,
The film thickness may be approximately 1 [μm].

After this, between the field insulating films 6, that is, MISFE
When the insulating film 7 for forming the gate P edge film (Sin, film) is formed on the 40 parts of the semiconductor substrate in the T forming part, as shown in FIG. 2 (4) and FIG. 3 (3). become.

The insulating film 7 may be, for example, a silicon dioxide (S i02 ) film formed by thermal oxidation of the surface of the semiconductor substrate 4, and the film thickness in this case may be about 1000 [A]. After this,
All the MISFETs in the main part of the memory array, that is, the MISFETs Q++~Q, Qt+~, which serve as storage elements.
On the surface of the semiconductor substrate 4 in the Q2n formation area, an n-channel MI
SFETI, an impurity for threshold voltage adjustment is introduced. This means that when the operating voltage is applied to the gate electrode, MISFET Qu-Qtn-Qz+-Qzn
P-type impurities at a predetermined impurity concentration may be introduced by ion implantation technique so as to obtain a threshold voltage such that ONt does not occur. For example, if the operating voltage is 5 [V], M
IS FET Q+ +~Q1r+4Q! 1~Q2
The threshold voltage of n may be set higher than 5 [V].

After the steps shown in FIG. 2(3) and FIG. 3(8), the polycrystalline silicon film is subjected to OVD (Chemical Vacuum
It is formed on the upper part of the semiconductor substrate 4 by the pourDeposition technique. Phosphorus is introduced to lower the resistance of this polycrystalline silicon film. After this, MISFE
To form the gate electrodes of T, selective patterning is performed to form gate electrodes 8, 9, and 10. The gate electrode 8 is electrically connected to gate electrodes adjacent in the row direction to form a word line WL. The film thickness of gate electrodes 8, 9, and 10 is 3500 CAI.
A certain degree is fine. After forming the gate electrode 8.9.10,
At least an insulating film 1 covering them is formed.

After this, to configure the n-channel MISFET.

Using the gate electrodes 8 and 9 and the field insulating film 6 as a mask for impurity-resistant introduction, self-alignment (self-alignment) is performed.
In terms of alignment, n-type impurities are selectively introduced into the vicinity of the surface of the well region 5. Furthermore, in order to configure a p-channel MISFET, p-type impurities are introduced into the semiconductor substrate 1 in a self-aligned manner using the gate electrode 0 and the field insulating film 6 as a mask for impurity introduction.
Selectively introduced near the surface. Then, each impurity is stretched and diffused, and as shown in FIG. 2 (D) and FIG.
A p+ type semiconductor region 14 which will become a source region and a drain region of a p-channel MISFET is formed. As the n-type impurity, for example, phosphorus (P
) ions, and boron ions, for example, may be used as the p-type impurity.

2nd appearance) and after the steps shown in Figure 3 CB+, OV
A P3 film 15 is formed on the entire surface using the D technique.

As this insulating film 15, it is preferable to use, for example, a phosphorous silicate glass (PSG) gland. The phosphosilicate glass film can alleviate the undulations that grow due to multilayering and can capture sodium (Na 2 ) ions that affect the electrical characteristics of semiconductor integrated circuit devices.

After this, the insulating films 7 and 15 on the predetermined semiconductor regions 12 and 13.14 are selectively removed, and the semiconductor regions 12 and 13 are selectively removed.
．． A connection hole 6 is formed in order to electrically connect 14 to the wiring formed in a later step. After this,
Semiconductor regions 12.13°14 and 1[
Wiring 17 is formed for electrical connection. this is,
For example, an aluminum (Al) film having a thickness of about 1 [μm] may be formed by vacuum evaporation technology, and may be patterned in a predetermined manner. Aluminum, which has a low resistance value, is often used as a wiring material for semiconductor integrated circuit devices, and bonding pads (external terminals) and the like are also formed from the same material and in the same manufacturing process. The formed wiring 1
7, in the wiring 17 formed in the memory array part MA, M I S F E T Q++ ~ Ql (1e
Semiconductor region 1 serving as the drain region of Qtl~Q2o
The wiring 17 connected to the semiconductor region 12 serving as the ground potential G is applied to the wiring 17 connected to the semiconductor region 12 serving as the ground potential.

After this, as shown in Figure 2 (01) and Figure 3 (Q).

A protective film 18 is formed on the entire surface by OVD technology. As this protective film 18, for example, a silicon dioxide film may be used. A portion of the protective film 18 above the bonding pad portion is removed to complete the device.

After the steps shown in FIG. 2 (0) and FIG. 3 (C1), R
In order to write information on the OM, a mask material according to Example 2 of the present invention is formed over the entire surface. Gold (Au), silver (Ag), and copper (Ou) are used as materials for this mask.

Heavy metals such as lead (Pb), palladium (Pd), platinum (P
Noble metals such as aluminum (i), nonferrous metals such as aluminum (AA), etc. can be used, but in this embodiment, aluminum, which has a good track record as a semiconductor integrated circuit device, may be used. After forming the mask material, In the memory array section A, when mask material other than at least the channel region forming part of MISFETQ is selectively removed to form a mask 19 for resisting X-ray irradiation, the results shown in FIGS. 2 and 3 are obtained. ). This mask 19
The pattern changes in various ways depending on the content of information written in the ROM. Further, a region of the memory array where peripheral circuits are provided is covered with a mask 19.

The film thickness of the mask 19 may be approximately 1 [, am], for example. However, the film thickness of the mask 19 does not necessarily need to be about 1 [μm] depending on the amount of X-ray irradiation performed in later steps, the degree of control of the threshold voltage value, etc. After forming the mask 19, the entire surface is irradiated with X-rays, and the area other than the part covered by the mask 19, that is, the I8 FE other than the MISFETQ□ of the memory array MA
T Q++-QCs~Q Q, I~Q2n threshold 1
m Control the voltage to a desired value, for example about 0.5 [V]. The threshold voltage of the n-channel MISFET is lowered by X-ray irradiation. This allows the MISFET
In the channel region forming portion 20 of Qn, for example, 5[
Even if an operating voltage of about [V] is applied to the gate voltage, ONL
It is possible to obtain a threshold voltage of 5 [■] or more, which is not possible, and MI 5FETQu * QCs ~ Q1n9 Ql
Channel region forming portions of l to Q2n (not shown)
, when the operating voltage is applied to the gate electrode, ONj
For example, a threshold voltage of about 05 [V] can be obtained. That is, according to Example I of the present invention, R
In semiconductor integrated circuit devices equipped with OM, MISF is
The threshold voltage of ET can be easily controlled. Note that the threshold voltage of a MISFET whose threshold voltage has been controlled by X-ray irradiation can be easily restored by heat treatment. That is, if a heat treatment step is incorporated after X-ray irradiation, it is necessary to consider the recovery of the threshold voltage in advance. Said R.O.
After the information writing step M, the mask 19 is removed and the temperature is reduced to 0.degree.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that various treatments may be performed after this.

Next, the dependence of the threshold voltage of the MISFET on X-ray irradiation will be explained.

Figure 4 shows MIS1 for X-ray irradiation! FIG. 2 is a diagram for explaining the threshold voltage dependence of ET.

In FIG. 4, the vertical axis shows the threshold voltage level of the n-channel MI 5FET, and the horizontal axis shows the threshold voltage level of the n-channel MISFET on the same scale as the vertical axis. As shown in the figure, the f-even curve representing the fluctuation of the threshold voltage due to the Xi irradiation has an inclination of approximately 45'', indicating a downward-sloping N property.

n-channel MISFET and n-channel MISFET
The threshold voltage S, changes to the threshold voltage S, by X-ray irradiation. That is, in the n-channel MISFET, X-ray irradiation increases the p
In the channel MI 5FET, it works in the direction of increasing the threshold voltage (.Also, the n channel M of the threshold voltage S,
The threshold voltage S1 is varied by subjecting the ISFET and the n-channel MISFET to a predetermined heat treatment.

These variations are made by almost the same path.

According to the present inventor, the following facts have been confirmed.

In other words, a gate insulating film (Si
For example, in a p-channel MI 5FET having a characteristic X-ray of aluminum or palladium (wavelength λ
= 10 [A), characteristic X-ray of tungsten (W) (wavelength λ
-0,2[A'l) etc., 1 to 1000[J/cI
This is the fact that by irradiating a p-channel MIsFET with X-rays having an energy amount of about 15 [V], the threshold voltage changes (shifts) about 15 [V]. However, when the MI 5FET 7 is irradiated with X-rays having an energy amount higher than about 1000 [J/cd], the threshold voltage value reaches a saturated state and the threshold voltage value reaches the saturation state, causing the fl! It is not possible to obtain the amount of voltage fluctuation.

Therefore, the threshold voltage of the MISFET can be easily controlled by the amount of X-ray irradiation that can be obtained depending on the wavelength of the X-rays and the irradiation time of the X-rays, and the required amount of variation in the threshold voltage.

In this example, information was written into the ROM after the formation of the protective film, which is the final stage of the manufacturing process of the semiconductor integrated circuit device.
M information may also be written.

In addition, when aluminum is used as the wiring material and gold, platinum, etc., which are not subject to chemical changes, are used as the mask material for X-ray irradiation resistance, the mask material is formed after the wiring is formed, and the mask material is used as the external terminal. By applying buttering to cover parts that are susceptible to unnecessary external influences, such as external terminals, the moisture resistance and corrosion resistance of external terminals and the like can be improved.

[Example ■]

This example is a semiconductor integrated circuit device @vC equipped with a horizontal mROM that uses an n-channel MISFET as a storage element of a ROM instead of the n-channel MISFET of Example I.
explain about. This example has almost the same manufacturing process as Example 2 above.

Drawings for explanation are omitted.

First, as in Example 2, an n-type semiconductor substrate (4) is prepared. In order to configure an n-channel MISFET, a p-type well region (5) is formed on a predetermined main surface portion of this semiconductor substrate, excluding the memory array MA forming portion. After this, similarly to Example I, a field insulating film (6) and a gate insulating film (7) are formed. Thereafter, according to the embodiment (2) of the present invention, impurities for adjusting the threshold voltage of the n-channel MISFET are introduced into the memory array MA section and other predetermined peripheral circuit sections near the surface of the semiconductor substrate. This means that when a predetermined operating voltage is applied to the gate electrode, the MISFET serving as the storage element is turned on.
What is necessary is to obtain a threshold voltage such that For example, if the operating voltage is 5 [■], the threshold voltage of the MISFET may be set to about 0.5 [V].

After this, the gate electrode (8°9.1
0) and an insulating film aυ covering them is formed. After this, a p+ type semiconductor region In” is formed in a self-aligned manner.
m semiconductor regions are formed to configure an n-channel MISFET and an n-channel MISFET. After this,
The process shown in FIG. 2 (q) is carried out in the same manner as in Example (2).

After this, a mask material is formed over the entire surface in order to write information into the ROM. In the memory array MA section, even if the operating voltage is applied to the gate electrode, ONt,
In order to form a MISFET (Qmt) with no oxidation, the mask material is selectively removed so that at least the channel region forming part of the MISFET (Q, +t) is opened, and A mask 19A is formed. X-rays are irradiated using this mask 19A, and the threshold voltage of the MISFET (Qmt) is set to a desired value of 1.
For example, the operating voltage is controlled to be higher than the operating voltage 5c'v].

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that the modification of this example is also Example ■
You can do various things in the same way.

[Example ■]

In this embodiment, a semiconductor integrated circuit device including a vertical ROM using an n-channel MISFET as a ROM storage element will be described.

FIG. 5 is a schematic ROM circuit diagram for explaining another embodiment of the present invention.

In FIG. 5, Q s r ~% + Q 4 □ ~
Q4r11* Q51 to Q5rn are n-channel MIS
It is a FET and serves as a memory element to configure a memory function.

M I 8 F E T Qs+ -Qsa~Q3rn
*Q41~Q4mm (1++~Q, rn is an enhancement type, and MISFET Q st is a depletion type configured by writing information to ROM. These MISFET Qu~Q3m+ Q
41 to Q 4m' Qat to Qsm are connected in series in columns, and are arranged in rows to form a matrix.

Such a ROM has a first threshold voltage that is OF Ii'' when no voltage is applied to the respective gate electrode.
~Qmrn' Q41~Q4m*Qllll~Q5m, and MI 5FETQat which has a second threshold voltage that is turned on when no voltage is applied to the gate electrode.

Next, a specific manufacturing method of this example will be explained.

Figures 6 (3) to 6 (q is 5) RO in each manufacturing process to explain the specific manufacturing method of Example 2 of the present invention
FIG. 2 is a plan view of a main part of a semiconductor integrated circuit device equipped with M. The main part plan views shown in FIGS. Since they are almost the same, they are omitted here.Furthermore, in order to make the drawings easier to see, the interlayer insulating film that should be provided between each wiring 1 is not shown.

First, as in Example 1, an n-type semiconductor substrate 4 is prepared, and a p well region 5 is selectively formed on a predetermined main surface thereof. Furthermore, as shown in the sixth stage, a field insulating film 6A and an insulating film 1117A are formed using the LOOO8 technique.

After the process shown in the sixth stage, the memory array MA section, that is, the MISFETQ□ to Q3mt Q
mt -Q4ms Q! Impurities for adjusting the threshold voltage of the n-channel MI 8FET are introduced into the vicinity of the surface of the semiconductor substrate 4, which will be the portions 1 to Q5m formed.

This is 0FF when no voltage is applied to the gate electrode.
P-type impurities with a constant impurity concentration may be introduced by ion implantation technique in order to obtain an enhancement-type threshold voltage. For example, if the operating W pressure is 5 [V
] The threshold voltage of the tL&i M I S F E T may be set to about 0.5 [V]. After this, similarly to Example 3, a gate electrode 8A is formed, an insulating film (not shown) is formed to cover it, and an n" type semiconductor region 12A that will become a source region and a drain region is formed. The gate electrodes 8A extend in rows and form word lines WL.As shown in FIG.
t-Q4m is constructed.

After the process shown in FIG. 6 [F]), a wiring forming process and a protective film forming process (not shown) similar to those shown in FIG. In order to perform this, in the memory array MA section, MISFE
MISFETQa+ *Qss+ other than TQa*
Qmt e Qmt * When a mask 19B for resisting X-ray irradiation according to the embodiment (2) of the present invention is formed on at least the channel region forming portion of Qmt, it becomes as shown in FIG. 6 (01K). Using this mask 19B, The entire surface is irradiated with X-rays 7, and the threshold voltage of MISFETQsz is controlled to a desired value, for example, about -2.0 [V], to form a depletion type MISFETQst. As a result, MISFETQs+ has a first threshold voltage that turns off when no voltage is applied to the gate electrode.

Qsa e Q41 * Qit + Q4g and a MISFET Qag having a second threshold voltage that is turned on even when no voltage is applied to the gate electrode are formed. After this, mask 19B may be removed.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that this embodiment can also be modified in various ways similar to embodiment I.

[Example ■]

This example is based on the n-channel M I S FE of Example ①.
A semiconductor integrated circuit device including a vertical ROM that uses a p-channel M'l5FET instead of a T as a storage element of the ROM will be described. The manufacturing process of this example is almost the same as that of Example ↑, and the drawings for explanation are omitted.

First, as in Example 2, an n-type semiconductor substrate (4) is prepared, and a p-type well region (5) is selectively formed in a predetermined main surface portion where a peripheral circuit is to be formed. Furthermore, Figure 6 (
Similar to the step shown in 3), a field insulating film (6A) and a gate PH film (7A) are formed.

After this, the memory array MA section, that is, the M I S F E T Qs1 to Q3m, Q4I which become storage elements
~Q4ms An impurity for adjusting the threshold voltage of the p-channel MISFET is introduced into the surface of the semiconductor substrate that will become the Qlll~Q5m formation portion. This can be done by introducing p-type impurities with a predetermined impurity concentration by ion implantation technology so that the gate electrode turns on when no voltage is applied to the gate electrode, that is, obtains a threshold voltage of the degree of debryshiron.

For example, if the operating voltage is 5 [V], MI SF'E
The threshold voltage of T may be set to about -2°0 [V].

After this, in the same manner as in Example ①, a gate electrode (8A) is formed, an insulating film (not shown) is formed to cover it, and a p+ type semiconductor region that will become a source region and a drain region is formed. do.

After this, a wiring forming step is carried out in the same manner as in Example (2).

A retention film formation process is performed. After this, in order to write information into the ROM, a mask 190 for resisting XM irradiation according to the embodiment (2) of the present invention is formed on at least the channel region forming portion of MISFET Qst in the memory array MA section.

Using this mask 190, the entire surface is irradiated with X-rays, and MIS
MI 5FETQs+-Qss~Q other than FETQst
Bme Q41-Q4me The threshold voltages of Qs+ to Q6m are controlled to a desired value, for example, about 0.5 [V], and the enhancement type MISFETQ, 1 is formed.

Qsa~Q3m, Q41~Q4mt Qs+~Q5m are formed.

This allows the M I to have a first threshold voltage that turns off when no voltage is applied to the gate electrode.
8 F ET Qa+ -Qss~QBm, Q41-
04m.

MIS having Qa+ to Q5m and a second threshold voltage that turns on when no voltage is applied to the gate electrode.
FBTQo is formed. After this, mask 190 may be removed.

Through these series of manufacturing steps, the semiconductor integrated circuit of this example is completed. Incidentally, the modification in this embodiment is based on the embodiment (2).

[Example V]

In this embodiment, a case will be described in which a semiconductor chip completed as a semiconductor integrated circuit device equipped with a mask ROM is sealed, and then information is written into the ROM.

FIG. 7 is a schematic diagram for explaining the outline of writing information into a sealed semiconductor integrated circuit device by X-ray irradiation.

In FIG. 7, numeral 21 is a completed semiconductor integrated circuit device on which information is written. 22 is a printed circuit board for housing the semiconductor integrated circuit device 21. Reference numeral 23 denotes wiring arranged in a predetermined pattern on the upper part of the printed circuit board 22. A wire 24 is used to electrically connect the wiring 23 to an external terminal (not shown) provided on the semiconductor integrated circuit device 21Vc. A sealing material 25 is used to seal the semiconductor integrated circuit device 21.

Reference numeral 26 denotes an X-ray irradiation-resistant mask, which is used to write information into the ROM. Top surface 26All of mask 26
"! A pattern 27 for writing information into the ROM is provided. This pattern 27 may be made of the mask material such as gold or platinum described in the above embodiment I. The mask 26 and the semiconductor integrated circuit device 21 The mask 26 is provided with a pattern (not shown) for mask alignment.The mask 26 is etched from the lower surface 26B to prevent its characteristics from becoming unstable due to the transmission of X-rays. It is made into a thin plate.

Next, the operation of this embodiment will be briefly explained using FIG.

First, a printed circuit board 22 is prepared which is a package of a semiconductor integrated circuit device [21] to which no information has been written in the ROM. And that) Upper 1c mask 26
are prepared and alignment is performed using each mask alignment pattern. This alignment is performed by the semiconductor integrated circuit device 2.
The treatment may be performed using X-rays that do not affect the threshold voltage of the MISFET provided in 1. After this, X from the top of mask 26! 28. The X-rays 28 pass through the gate insulating film of a predetermined MISFET provided in the semiconductor integrated circuit device 21 via the pattern 27. As a result, the threshold voltage of a predetermined MISFET is varied, and information writing into the ROM is completed.

As the X-ray source, it is preferable to use synchrotron radiation, which has good directivity.

〔effect〕

(By irradiating MISFET with a predetermined X-ray, it is possible to change the amount of interfacial charge between the channel region forming part of the semiconductor substrate and the gate insulating film,
The threshold voltage of SFET can be easily controlled.

+21 In a mask ROM in which MISFET is used as a storage element and a plurality of them are arranged in a matrix, by using X, 1M to write information in the ROM, the transparency of X-rays is extremely high, which makes it possible to improve semiconductor integrated circuits. Information can be written during any manufacturing process of the device. Therefore, information writing into the ROM can be performed at the final stage in the manufacturing process of a semiconductor integrated circuit device.

1 completion can be significantly shortened.

(3) By using a material that does not undergo chemical changes as a mask material for X-ray irradiation resistance, and using the mask material as a protective film for wiring that is susceptible to chemical changes in aluminum, semiconductor integrated circuit devices It is possible to substantially improve the moisture resistance and corrosion resistance of wiring used for wiring.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is possible to make various changes without departing from the gist of the invention. Not even.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram of a ROM for explaining one embodiment of the present invention, and FIGS. ROM in each manufacturing process to explain
FIGS. 3(4) to 3(D) are cross-sectional views of main parts of a semiconductor integrated circuit device equipped with
FIG. 4 is a diagram for explaining the threshold voltage dependence of MISFET on X-ray irradiation; FIG. 5 is another embodiment of the present invention. 6(3) to 6(0) are schematic ROM circuit diagrams for explaining the R in each manufacturing process for explaining the specific manufacturing method of Example 2 of the present invention.
FIG. 7 is a plan view of essential parts of a semiconductor integrated circuit device equipped with an OM, and is a schematic diagram for explaining the outline of writing information into a packaged semiconductor integrated circuit device by X-ray irradiation. In the figure, Qtt~Q lnt Qt +~Q2nI Q!
II~Q3 m'Q41 ""04m, Qffil~Q
5m"・MI 5FET, MA-...Memory array, W
L...word line, OD...common data line, DL...
...Data line, Qs...MI 5F for column switch
ET, 1...X decoder, 2...Y decoder, 3.
...Sense amplifier, 4...Semiconductor substrate, 5゛°well region, 6. 6A...feel) "P edge [,7°7A, 11. 15...P edge membrane, 8. 8A, 9.1
0...gate electrode, 12. 12A, 12B, 13
．． 14... Semiconductor region, 16... Connection hole, 17...
・Wiring, 18...Protective film, 19.19A, 19B, 1
90...Mask, 20... Channel region forming part,
21... Semiconductor integrated circuit, 22... Print circuit, 23... Wiring, 24... Wire, 25...
Package, 26... X-ray irradiation mask, 27...
Pattern 28...X-ray. Fig. 1 (ψ Fig. 3 (A) Fig. 3 (f3) Fig. 3 (C) Fig. 3 (-D) Fig. 4 - Vd Rep.,. ♂＼, 417th pressure
5 Figure no ζ (q Figure 6 (A) σA JP-A-113464 (13) Figure 6 (C> DaP)/?El rA/q13 Me/ ^// 4rχsu1 + --1 Lee 1 11 W Muta 4z 4, f2 /2A (714) y /bu8 Fig. 6 (f3) 5 (p) 6;

Claims (1)

[Claims] 1. A word in which a plurality of P-edge gate field effect transistors of a predetermined conductivity type having a first threshold voltage or a second threshold voltage are extended in a row. Manufacture of a semiconductor integrated circuit device having a horizontal read-only memory function, in which a plurality of lines intersect with a cough word line and extend in a row, and one double layer is provided at the intersection with a bit line provided. In the method, during or after the step of forming the insulated gate field effect transistor having the first threshold voltage, an X-ray is irradiated so as to pass through a predetermined insulated gate field effect transistor, and the irradiated A method of manufacturing a semiconductor integrated circuit device, comprising changing a first threshold voltage of an insulated gate field effect transistor to a second threshold voltage. 2. The insulated gate field effect transistor is a p-channel type having a first threshold voltage, and the first threshold voltage of a predetermined insulated gate field effect transistor is lowered by X-ray irradiation. Claim 1 characterized in that the second threshold voltage is also varied to a higher second threshold voltage.
A method for manufacturing a semiconductor integrated circuit device as described in 1. 3. The P3 edge gate type field effect transistor is an n-channel type having a first threshold voltage, and the first threshold voltage of a predetermined insulated gate type field effect transistor is increased by X-ray irradiation. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second threshold voltage is varied to a lower second threshold voltage.