JPS60113463A - Manufacture of semiconductor ic device - Google Patents

Abstract

PURPOSE:To contrive to reduce the processes by enabling the information writing of an ROM at the final step in the manufacturing process by a method wherein the threshold voltage of a MISFET is controlled by X-ray irradiation at the final step in the manufacturing process for the IC equipped with the ROM. CONSTITUTION:By excluding the memory array MA forming region of an n<-> type semiconductor substrate 4, a p type well region 5 is formed in its required main surface part to construct the n-channel MISFET. After insulation films 6 and 7 are formed, impurities for adjusting the threshold voltage of the p-channel MISFET are introduced to the MA part and to the neighborhood of the substrate surface in a required peripheral circuit part other than said part. At this time, the threshold voltage is set at about 0.5V so as to obtain a threshold voltage whereby the MISFET serving as the memory element turns on. Next, gate electrodes 8-10 are formed, and an insulation film 11 that covers them is formed. Then, a mask 19 to resist X ray irradiation is formed. This device is irradiated with X rays by using this mask, and thus the threshold voltage of the MISFETQ12 is controlled so as to be more than a desired voltage, e.g., an operating voltage of 5V.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as
The present invention relates to a semiconductor integrated circuit device equipped with a MISFET (hereinafter referred to as ROM), and in particular relates to a technology that is effective when applied to a semiconductor integrated circuit device equipped with a read-only memory function (hereinafter referred to as ROM (Read Only Memory)). .

[Background technology]

A semiconductor integrated circuit device equipped with a mask ROM can write information into the mask ROM portion. Therefore, it is possible to provide semiconductor integrated circuit devices that have various information and meet various demands to customers.

As a supplier of semiconductor integrated circuit devices, it is preferable that the time required to complete the product (hereinafter referred to as "Turn A Round Time") be as short as possible in order to quickly meet the demands of consumers.

As a way to shorten this one completion time,
No. 130963 and Japanese Unexamined Patent Publication No. 56-130975 have been proposed. This is because after the process of forming the gate electrode, source region, and drain region that constitutes the MISFET,
In this method, a predetermined impurity is introduced into the channel forming part through the gate electrode using ion implantation technology, the threshold voltage of the MISFET is varied, and information is written.

However, this method has a problem in that information cannot be written after the wiring formation process after the formation process of the gate electrode, source region, and drain region constituting the MISFET. This is due to the causes explained below. In order to introduce impurities into the channel region for writing information, extremely large energy is required to pass through the gate electrode. By introducing impurities with this energy into the channel region,
Crystal defects occur in that part. In order to remove these crystal defects, a high-temperature, long-time annealing process is required.

That is, since semiconductor integrated circuit devices generally use aluminum (At) as a wiring material, an annealing process at a temperature higher than the melting temperature of the wiring material must be performed before the wiring formation process.

Based on this technology, as a result of the inventor's experiments and repeated studies, the inventor has discovered that by X-ray irradiation,
We discovered that the threshold voltage of MISFET varies.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a technique that can shorten the time it takes to write information in a semiconductor integrated circuit device equipped with a mask ROM.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by irradiating the MISFET having the first threshold voltage with highly transparent X@, the MISFET
Since the first threshold voltage of the ET can be changed to the second threshold voltage, information can be written in the final stage of the manufacturing process of a semiconductor integrated circuit device that includes a mask ROM, thereby shortening the completion time. It's about doing.

Hereinafter, the configuration of the present invention will be described in detail together with examples.

[Example ■]

In this example, MI8 F' having the first threshold voltage
A description will be given using a semiconductor integrated circuit device including a mask ROM in which information is configured by an ET and a MISFET having a second threshold voltage.

In all the figures, those having the same function are marked with the same number, and repeated explanations will be omitted.

The present invention utilizes a completely new principle to realize MISFET
First, the principle will be explained.

The threshold voltage [Vth] of the MISFET can be expressed by the following equation.

Here, export. : Work relationship between gate electrode and silicon Q88: Interface charge between silicon and oxide film Co : Gate capacitance per unit area φf : Fermi potential QB : Charge induced in the surface depletion layer by ionized donor atoms .

The present inventor has discovered that the p-channel MISFET and the n-channel MISFET each have a predetermined threshold voltage, by X-ray irradiation, the p-channel MISFET
The fact that the predetermined threshold voltage of the n-channel M I 8 F E T will be a higher threshold voltage than that, and the predetermined threshold voltage of the n-channel MI 8 FET will be a lower threshold voltage than that, Confirmed by experiment. According to the present inventor, this fact is believed to be due to the causes explained below.

In other words, when MISFET is irradiated with X-rays, MISFET
Electrons in the gate insulating film (810) constituting ET' are knocked out from inside, forming a deep trap level in the forbidden band of the gate insulating film.
This is because (-Qs8/C,), which is the second term on the right side of equation (1), changes.

Therefore, the principle of the present invention is to control a p-channel MISFET with a predetermined threshold voltage to a higher threshold voltage by X-ray irradiation, and control an n-channel MISFET with a predetermined threshold voltage with X-rays. The method is to control the threshold voltage to be lower than that by irradiation.

In this embodiment, a semiconductor integrated circuit device including a horizontal ROM using an n-channel MISFET as a ROM storage element will be described.

FIG. 1 is a schematic circuit diagram of a ROM for explaining one embodiment of the present invention.

In FIG. 1, Qu~Q1rzQt+~Q2n...
...is an enhancement type n-channel MISFE
T, and is for configuring a memory function as a memory element. NAViMISFETQII~Ql n +
Qz+~Qgn... is a memory array arranged in a plurality of IJ sock shapes. 1 is an X decoder, 2 is an X decoder, and is a complementary insulated gate field effect transistor [hereinafter referred to as CMIS
Mentary MISFET)]
It consists of WL is a plurality of word lines extending in a row from one side of the
TQI□r Q21+ Ql! r QtN...
・It is electrically connected to a predetermined gate electrode. An operating voltage that turns on a predetermined MISFBTQ is applied to the word line WL. Reference numeral 3 denotes a sense amplifier, which amplifies and outputs a voltage serving as information applied to a common data line, which will be described later. CD
is a common data line, and is used to apply a voltage serving as information. DL is a plurality of data lines extending in a column (the direction in which the data lines extend is referred to as the column direction), and one end of each is electrically connected to the common data line CD via the column switch MI8FBTQ8. MISFETQII- with each other end arranged in the column direction
Q+n and Q21- are electrically connected to the drain regions of Qtn. MISFET Q8 for column switch
The gate electrode of is electrically connected to the X decoder 2. MISFETQI arranged in column direction! ~Q1n,
The source regions of Q,1 to Qtrl are commonly grounded in the column direction.

Such a ROM has a first threshold voltage that turns on when an operating voltage is applied to each gate electrode.
n.

There is a MISFET Q+x having a second threshold voltage higher than the first threshold voltage when an operating voltage is applied to the gate electrode. For example, when MISFETQ++ is selected, the ground potential is read out by the sense amplifier 3, and the MISFET
When selecting E T Q+t, the data line “D”
The potential applied to L is read out by the sense amplifier 3. That is, the ROM has MIs with different threshold voltages.
Various information can be obtained by combining SFETs.

Next, a specific manufacturing method of this example will be explained.

Figures 2-5 show the ROM in each manufacturing process for explaining the specific manufacturing method of Example 2 of the present invention.
3 is a cross-sectional view of a main part of a semiconductor integrated circuit device equipped with
FIGS. 5 to 3 are plan views of essential parts of a semiconductor integrated circuit device equipped with a ROM in each manufacturing process for explaining the specific manufacturing method of Example 2 of the present invention. Figure 2 (
5) ~ The cross-sectional view of the main part shown in Figure 2 0 shows the MIS on the left side.
FETQ+t is shown, and the diagram on the right shows peripheral circuits, for example, CMIn that constitutes X decoder 1° and X decoder 2.

The main part plan views shown in Fig. 3 (5) to Fig. 3 (g) are MI
SFETQ11~Q, n, Q2. ~Q2n is the main part of the memory array arranged in a matrix, as shown in Figure 2~
The portion showing MISFET QH in FIG. 20 is a cross-sectional view taken along the line ■-■. Note that in FIGS. 3-3, an interlayer insulating film to be provided between each wiring layer is not shown in order to make the drawings easier to see.

In order to construct a semiconductor integrated circuit device, an n-type semiconductor substrate 4 made of single crystal silicon (Si) is prepared. A p-type well region 5 is selectively formed on a predetermined main surface portion of this semiconductor substrate 4 in order to configure an n-channel MISFET. This means, for example, that boron (B) ion impurities of approximately 8X10" (atomic side/cIA) are
The impurities may be selectively introduced using an ion implantation technique with an energy of approximately (KeV), and the introduced impurities may be stretched and diffused.

After this, a field insulating film 6 is formed to electrically isolate the MISFETs and the like. This field insulating film 6 is formed by selective thermal oxidation technology of the substrate, and its film thickness may be about 1 [μm]. After that, an insulating film 7 mainly forming a gate insulating film (8+Ot film) is formed between the field insulators 86, that is, on the top of the semiconductor substrate 4 in the MISFET forming part.
As shown in the picture. The insulating film 7 may be, for example, a silicon dioxide (8i0y) film formed by thermally oxidizing the surface of the semiconductor substrate 4, and the film thickness in this case may be about 1000 (A). After this, all MISFEs in the main part of the memory array
T, that is, MI SF ET Q which becomes a memory element
Impurities for n-channel MI8FETt and threshold voltage adjustment are introduced into the surface of the semiconductor substrate 4 in the forming portions of ++ to Q+n and Qt1 to Qtn. This means that when the operating voltage is applied to the gate electrode, M I S P B T
In order to obtain a threshold voltage such that Q++ ~Q+n and Qt+ ~Q2n are not ONt, p-type impurities with a predetermined impurity concentration may be introduced by ion implantation technology8 For example, if the operating voltage is 5 [■] B, M I S
The threshold voltages of FETQ++ to Q+n and Qt+ to Qtn may be set higher than 5 [■].

After the steps shown in FIG. 2 (6) and FIG.
rDeposition) technology, the semiconductor substrate 4
Form at the top. Phosphorus is introduced to lower the resistance of this polycrystalline silicon film. After this, the MISFET gate! To construct the camellia, selective patterning is performed to form gates at poles 8,9.10't-. The gate electrode 8 is electrically connected to adjacent gate electrodes and electrodes in the row direction to form a word line WL. The film thickness of the gate electrodes 8, 9 and 10 is 3500 (A)
A certain degree is fine.

After forming the gate electrodes 8, 9, and 10, an insulating film 11 is formed to cover at least a little of the solar cells. After this, in order to configure an n-channel MISFET, the gate electrode 8
, 9 and the field insulating film 6 as a mask for impurity introduction, self-alignment (5elf alignment) is performed.
n-type impurities are selectively introduced into the vicinity of the surface of the well region 5.

Furthermore, in order to configure an n-channel MISFET,
Using gate electrode 10 and field insulating film 6 as a mask for impurity introduction, p-type impurities are selectively introduced into the vicinity of the surface of semiconductor substrate 1 in a self-aligned manner. Then, each impurity is stretched and diffused, and as shown in FIG. 2(c) and FIG.
N-type semiconductor regions 12 and 13 serving as the source and drain regions of SFET are formed, and p-channel MI8 is formed.
P+ type semiconductor regions 14 are formed to become the source and drain regions of the FET. As the n-type impurity, for example, phosphorus (P) ions may be used, and as the p-type impurity, for example, boron ions may be used.

After the steps shown in Figure 2 (c) and Figure 3, CVD
Insulation #15 is formed on the entire surface using a technique.

As this insulating film 15, for example, a phosphosilicate glass (PSG) film may be used. The phosphosilicate glass film can alleviate the undulations that grow due to multilayering, and can capture Na+ ions that affect the electrical characteristics of semiconductor integrated circuit devices. After this, the insulating films 7, 15 on the predetermined semiconductor regions 12, 13, 14 are selectively removed, and the semiconductor regions 12, 13, 14 are selectively removed.
3. A connection hole 16 is formed in order to make an electrical connection between 14 and the wiring formed in a later step. After this, a wiring 17 is formed so as to be electrically connected to the semiconductor regions 12, 13 and 14 through the connection hole 16. this is,
For example, aluminum (At) with a film thickness of about 1 [μm]
The film may be formed by vacuum evaporation technology and subjected to predetermined patterning. Aluminum, which has a low resistance value, is often used as a wiring material for semiconductor integrated circuit devices, and bonding pads (external terminals) and the like are also formed of the same material and through the same manufacturing process. Among the wiring lines 17 formed above, the wiring line 17 formed in the memory array part MA
In, MISFBTQ, , ~QlfllQ2I-Q
The wiring 17 connected to the semiconductor region 12 serving as the drain region of tn becomes the data line DL, and the wiring 17 connected to the semiconductor region 12 serving as the source region is applied to the ground potential G. After this, as shown in FIG. 2 (Q) and FIG. 3 (Q), a protective film 18 is formed on the entire surface by CVD technology. As this protective film 18, for example, a silicon dioxide film may be used. membrane 18
The part above the bonding pad portion is removed to complete the device.

After the steps shown in Figure 2 (Q) and Figure 3 (Q), the ROM
In order to omit information, a mask material according to Example 2 of the present invention is formed over the entire surface. As this mask material,
Heavy metals such as gold (Au), silver (Ag), copper (Cu), and lead (PB), noble metals such as palladium (Pd) and platinum (Pt), and non-ferrous metals such as aluminum (At) may be used. However, in this embodiment, aluminum, which has a good track record as a semiconductor integrated circuit device, may be used. After forming the mask material, in the memory array section A, the mask material other than at least on the channel region forming part of M I 8 FET Q10 is selectively removed to form a mask 19 for resisting X-ray irradiation. When the second
The result is as shown in FIG. 0 and FIG. 30.

The pattern of this mask 19 changes in various ways depending on the content of information written in the ROM. Further, the area where the peripheral circuit is provided is covered with a mask 19.

The film thickness of the mask 19 may be, for example, about 1 μm. However, the film thickness of the mask 19 does not necessarily need to be about 1 μm depending on the amount of X-ray irradiation performed in later steps, the degree of control of the threshold voltage value, etc. After forming the mask 19, the entire surface is irradiated with X-rays, and the area other than the portion covered by the mask 19, that is, the MI8FETQ! of the memory array MA! ! MIS other than E
The threshold voltages of TQn, Q+s to Q+n, and Qt+ to Qtn are controlled to desired values, for example, about 0.5 [V]. n-channel M1 by X-ray irradiation
The threshold voltage of 8FE'I' decreases. As a result, in the channel region forming portion 20 of MISFET (J+t), it is possible to obtain a threshold voltage of 5 [V] or more such that no ONL occurs even if an operating voltage of, for example, about 5 [■] is applied to the gate electrode. , MISFF3TQ++ + Q
+s −Q+n + Q21~(In the Ln channel region forming part (not shown), for example, 0, 5 [V
) can be obtained.

That is, according to the embodiment (2) of the present invention, in a semiconductor integrated circuit device equipped with a ROM, the threshold voltage of the MISFET can be easily controlled by X-ray irradiation at the final stage of its manufacturing process. Note that the MISFET whose threshold voltage is controlled by X-ray irradiation
The threshold voltage can be easily restored by heat treatment. That is, if a heat treatment step is incorporated after X-ray irradiation, it is necessary to consider the recovery of the threshold voltage in advance. After the ROM information writing step, the mask 19 may be removed.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that this material may be subjected to various treatment steps.

Next, the dependence of the threshold voltage of the MISFET on X-ray irradiation will be explained.

FIG. 4 is a diagram for explaining the threshold voltage dependence of MISFET on X-ray irradiation.

In FIG. 4, the vertical axis shows the threshold voltage level of the n-channel MISFET, and the horizontal axis shows the pf channel Δ
4 I S FET threshold voltage level is shown. As shown in the figure, the data curve representing the variation in threshold voltage due to X-ray irradiation has an inclination of 45° and shows linearity at the lower right corner.

n-channel MISFET and n-channel MISFET
The threshold voltage SL changes to the threshold voltage S2 by X-ray irradiation. In other words, X-ray irradiation is applied to n-channel MISFET in the direction of lowering the threshold voltage.
In the channel MISFET, it works to increase the threshold voltage. Also, the n-channel MI of threshold voltage S,
The threshold voltage SI is varied by subjecting the SFET and the p-channel MI 8 FET to a predetermined heat treatment. These variations are made by almost the same path.

According to the present inventor, the following facts have been confirmed.

That is, the gate insulating film (Si
In an n-channel MISFET with
For example, characteristic X-rays of aluminum and palladium (wavelength λ =
10 [A:]), 1 to 1000 [J/~ using characteristic X-rays of tungsten (W) (wavelength λ = 0.2 CAj, etc.)
] X-rays having an energy amount of about
This is the fact that by irradiating the I S FET, the threshold voltage fluctuates (shift i) by about 15 [V]. However, if the MIS or FET is irradiated with X-rays having an energy it higher than about 1000 [J/d], the threshold voltage value reaches a saturated state, and the amount of variation in the threshold voltage cannot be obtained.

Therefore, the threshold voltage of the MISFET can be easily controlled by the amount of X-ray irradiation that can be obtained depending on the wavelength of the X-rays and the irradiation time of the X-rays, and the required amount of variation in the threshold voltage.

In this embodiment, information was written into the ROM after the protective film was formed, which is the final stage of the manufacturing process of a semiconductor integrated circuit device.
M information may also be written.

In addition, when aluminum is used as the wiring material and gold, platinum, etc., which are not subject to chemical changes, are used as the mask material for X-ray irradiation resistance, the mask material is formed after the wiring is formed, and the mask material is used as the external terminal. The moisture resistance and corrosion resistance of external terminals and the like can be improved by patterning them so as to cover parts that are susceptible to unnecessary influences from the outside.

[Example ■]

This embodiment describes a semiconductor integrated circuit device equipped with a horizontal ROM in which an n-channel MISFET is used as a storage element for R and OM in place of the n-channel MISFET of embodiment (2). Since the manufacturing process of this example is almost the same as that of Example I, drawings for explanation are omitted.

First, as in Example 2, an n-type semiconductor substrate (4) is prepared. An n-channel MI8FB' is provided on a predetermined main surface of this semiconductor substrate, excluding the memory array 'MA forming part'.
A p-type well region (5) is formed to constitute l'. After this, the field insulation film (
6) and gate insulating film (form a force. After this, according to the embodiment
Impurities for adjusting the threshold voltage of the channel MISFET are introduced.

This can be done by obtaining a threshold voltage that turns on the MISFET serving as a storage element when a predetermined operating voltage is applied to the gate insulating film. For example, if the operating voltage is 5 [■], the threshold voltage of the MI8FET may be set to about 0.5 [V].

After this, the gate electrode (8°9.1
0) and an insulating film (11) covering them is formed. After this, a p+ type semiconductor region in a self-aligned manner,
An n-type semiconductor region is formed and an n-channel MISFE is formed.
Configure T and n channel MISFETs. After this, the process shown in FIG. 20 is performed in the same manner as in Example (2).

After this, a mask material is formed over the entire surface in order to write information into the ROM. Then, in the memory array MA section, in order to form a MI S F Fi T (Q+t) that does not turn on even when an operating voltage is applied to the gate electrode, at least the channel region formation of the M I S F E T (Q+ The mask material is selectively removed so that the upper part is open, and a mask 19A for resisting X-ray irradiation is formed.
form. This mask 19At[is used to irradiate X-rays,
The threshold voltage of the M I S F E T (Q10) is controlled to a desired value, for example, a value higher than the operating voltage 5 [■].

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. It should be noted that various modifications of this embodiment can be made in the same manner as in the embodiment (2).

[Example ■]

(23) This embodiment describes a semiconductor integrated circuit device equipped with a vertical ROM that uses an n-channel MISFET as a ROM storage element.

FIG. 5 is a schematic ROM circuit diagram for explaining another embodiment of the present invention.

In Fig. 5, s Qs+ ~ Qsm + Q41 ~ Q+
m rQ! ,~Q! nl is an n-channel MISFET, which is used as a storage element to configure a storage function. MI 5FETQs+, Qss~Qsm, Q4
1~Q4□IQIII~Q, with mij' J-7 hancement type Te, M engineering 5FETQ3. is a depletion type configured by an information writing mini of RoM.

These M I S F B T Qs+ ~ Qsm, (
L+~Q+m, Q++~Q,. The columns are connected in series, and they are arranged in rows to form a matrix.

Such a ROM has a first threshold voltage that turns off when no voltage is applied to each gate electrode.
There are mQ41 to Q4m r Q51 to Qsm, and a MISFET Qu having a second threshold voltage (24) that is turned on when no voltage is applied to the gate electrode.

Next, a specific manufacturing method of this example will be explained.

FIGS. 6(g) to 6(0) show R and O in each manufacturing process for explaining the specific manufacturing method of Example 2 of the present invention.
FIG. 2 is a plan view of a main part of a semiconductor integrated circuit device equipped with M. The principal part plan views shown in FIGS. 6(5) to 6(0) show the principal parts of the memory array MA, and the cross-sectional views of the MISFETs in each plan view are those shown in Example 2 above. Since it is almost the same as , it is omitted here. moreover,
In order to make the drawings easier to see, an interlayer insulating film to be provided between each wiring layer is not shown.

First, as in Example 2, an n-type semiconductor substrate 4 is prepared, and a p-type well region 5 is selectively formed on a predetermined main surface thereof. Furthermore, as shown in FIG. 6, a field insulating film 6A and an insulating film 7A are formed using the LOCO8 technique.

After the process shown in FIG. 6, the memory array MA section, that is, MISFETQs+ to Q
am + Q41~Q4m + Q s+ -Q I1
An impurity for adjusting the threshold voltage of the n-channel MISFET is introduced into the vicinity of the surface of the semiconductor substrate 4, which will be the m-forming portion.

This turns OFF when no voltage is applied to the gate electrode.
P-type impurities at a predetermined impurity concentration may be introduced by ion implantation technology so as to obtain an enhancement-type threshold voltage. For example, the operating voltage force 5 (V
) Terror hif, threshold voltage of MISFET is set to 0.5
[V] may be sufficient. After this, similarly to Example I, a gate electrode 8A is formed, an insulating film (not shown) is formed to cover it, and an n-type semiconductor region 12A that becomes a source region and a drain region is formed. . The gate electrodes 8A constitute heel word lines WL extending in rows. As a result, as shown in FIG. 6(c), the MIS
FETQs+, Qsz, Qss, Q++, Q10.
(Ls is configured.

After the step shown in FIG. 6 (2), a wiring forming step and a protective film forming step (not shown) similar to those shown in FIG. 2 0 are performed. Then, in order to write information into the ROM, MI8FE is used in the memory array MAllffi.
MISFETQ other than TQst! I.

Qss + Q41 + (Lt r When the mask 19B for X-ray irradiation resistance according to the embodiment (2) of the present invention is formed on at least the channel region forming portion of Q4g,
It becomes as shown in the figure (Q). Using this mask 19B, irradiate the entire surface with X@, control the threshold voltage of MI8FETQ32 to a desired value, for example, about -2, OEVE, and All MISFBT QIIt of the type are formed.Thereby, MISFBTQs+, Qss have a first threshold voltage such that they are turned off when no voltage is applied to the gate electrode.

Q41 + Q42 r Qas and a MISFET Qst having a second threshold voltage that is turned on even when a voltage is almost applied to the gate is formed.

The mask 19B may then be removed.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Note that, similar to Example I, various modifications of this example can be made.

[Example ■]

(271 This example describes a semiconductor integrated circuit device equipped with a vertical ROM in which a p-channel MISFET is used as a ROM storage element in place of the n-channel MISFET in Example (2). Since the manufacturing process is almost the same as that shown in FIG.

First, in the same way as in Example 2, an n-type semiconductor substrate (4) is prepared, and p-type melt regions (5) are selectively formed on a predetermined main surface portion where a peripheral circuit is to be formed. Furthermore, a field insulating film (6A) and a gate insulating film (7A) are formed in the same manner as the step shown in the sixth doctor.

After this, the memory array MA section, that is, M I 8 F B T Qs+ ~Qsrn, Q which becomes a storage element
Impurities for adjusting the threshold voltage of the p-channel MISFET are introduced into the surface of the semiconductor substrate where 41 to Q4m + QB+ to Qsm will be formed. This can be done by introducing p-type impurities at a predetermined impurity concentration by ion implantation technology so that a depletion type threshold voltage, which turns on when no voltage is applied to the gate electrode, is obtained. For example, if the operating voltage is 5 (Vl(28)), the threshold voltage of the MI S FET is -2,
It should be about 0 [■]. After this, in the same manner as in Example ①, a gate electrode (8A) is formed, an insulating film (not shown) is formed to cover it, and a p-th grade semiconductor region that will become a source region and a drain region is formed. do.

After this, a wiring forming step is carried out in the same manner as in Example (2).

Perform a protective film forming process. After this, in order to write R and OM information, in the memory array MA section, at least the channel region forming section of the MI 8 FET Qu is exposed to X-ray irradiation according to the embodiment (2) of the present invention. A mask 19C is formed. Using this mask 19C, irradiate the entire structure with X-rays, MI SF B T Qs
MI8FETQs+ other than t, Qss~Qsm+
The threshold voltages of Q41 to Q4m + Q a+ to Q sm are controlled to a desired value, for example, about o, s [V], and enhancement type M I S F E T
Qs+ IQss-Qsm + Q41~Q+m,
Q+u to Qam are formed. This allows the first gate electrode to turn off when no voltage is applied to the gate electrode.
M I S F E TQs+ with a threshold voltage of
, Qss~Qsm, Q41~Q4ITl.

MI having Qs+ to Qam and a second threshold voltage that turns on when no voltage is applied to the gate electrode.
SFETQ, , and are formed. After this, mask 19
C may be removed.

Through these series of manufacturing steps, the semiconductor integrated circuit device of this embodiment is completed. Incidentally, the modification in this embodiment is based on the embodiment (2).

[Example V]

In this embodiment, a case will be described in which a semiconductor chip completed as a semiconductor integrated circuit device equipped with a mask ROM is sealed, and then information is written into the ROM.

FIG. 7 is a schematic diagram for explaining the outline of writing information into a sealed semiconductor integrated circuit device by X-ray irradiation.

In FIG. 7, 21 is a semiconductor integrated circuit device completed without writing information. 22 is a printed circuit board for housing the semiconductor integrated circuit device 21. Reference numeral 23 denotes wiring arranged in a predetermined pattern on the upper part of the printed circuit board 22. 24 is a wire for electrically connecting the wiring 23 with an external terminal (not shown) provided on the semiconductor integrated circuit device 21. 25 is a sealing material, It is for sealing the circuit device 21. Reference numeral 26 is an X-ray resistant mask for writing information in the ROM.The upper surface 26A of the mask 26 is for writing information in the ROM. A pattern 27 is provided.

For this pattern 27, the mask material such as gold or platinum described in Example I may be used. The mask 26 and the semiconductor integrated circuit device 21 are provided with a pattern (not shown) for mask alignment. The mask 26 is etched from the lower surface 26B to prevent its characteristics from becoming unstable due to the transmission of X-rays, and has a thin plate shape.

Next, the operation of this embodiment will be briefly explained using FIG.

First, R and OM information has not been written (31
) A printed circuit board 22 on which a semiconductor integrated circuit device 21 is packaged is prepared. Then, a mask 26 is prepared on top of the mask 26, and alignment is performed using each mask alignment pattern. This alignment may be performed using X-rays that do not affect the threshold voltage of the MISFET provided in the semiconductor integrated circuit device 21. After this, X-rays 28 are irradiated from above the mask 26. This X-ray 2
8 passes through the gate insulating film of a predetermined M I S FET provided in the semiconductor integrated circuit device 21 via the pattern 27 . As a result, the threshold voltage of a predetermined MISFET is varied, and information writing into the ROM is completed.

As the X-ray source, it is preferable to use synchrotron radiation, which has good directivity.

〔effect〕

(1) By irradiating the MISFET with predetermined X-rays, the amount of interfacial charge between the channel region forming part of the semiconductor substrate and the gate insulating film can be varied, and the threshold value of the MISFET can be changed. Voltage can be easily controlled.

(32) (2) In a mask ROM in which M I S F E T is used as a memory element and a plurality of them are arranged in a matrix,
By using X-rays to write information into the ROM, information can be written in any manufacturing process of semiconductor integrated circuit devices due to the extremely high transparency of the X-rays. Therefore, since information can be written into the ROM at the final stage in the manufacturing process of a semiconductor integrated circuit device, the time required to complete the process can be significantly shortened.

(3) By using a material that does not undergo chemical changes as a mask material for X-ray irradiation resistance, and using the mask material as a protective film for wiring that is susceptible to chemical changes such as aluminum, semiconductor integrated circuit devices It is possible to substantially improve the moisture resistance and corrosion resistance of wiring used for wiring.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is possible to make various changes without departing from the gist of the invention. Not even.

[Brief explanation of the drawing]

FIG. 1 is a schematic ROM circuit diagram for explaining one embodiment of the present invention, and FIGS. 3-30 are cross-sectional views of main parts of a semiconductor integrated circuit device equipped with a ROM in each manufacturing process for illustrating the specific manufacturing method of the embodiment (2) of the present invention. A plan view of a main part of a semiconductor integrated circuit device equipped with a ROM in the manufacturing process, FIG. 4 is a diagram for explaining the threshold voltage dependence of a MISFET on X-ray irradiation, and FIG. Schematic circuit diagrams of a ROM for explaining the embodiment of the present invention, and FIGS. FIG. 7 is a schematic diagram for explaining the outline of writing information into a packaged semiconductor integrated circuit device by X-ray irradiation. In the figure, Qn ~Q+n + Qt+ ~Qtn r Q
s+ ~Qsm rQ41-Qim, Qs+ ~Qs
m□=MISFET, MA-memory array, WL...word line, CD...common data line, D
L...Data line, Q8...MIS for column switch
FET, 1...X decoder, 2...X decoder, 3
...Sense amplifier, 4...Semiconductor substrate, 5...Well region, 6,6A...Field insulating film, 7,7A
. 11.15... Insulating film, 8.8A, 9.10... Gate electrode, 12.12A, 12B, 13.14... Semiconductor region, 16... Connection hole, 17... Wiring, 18・
... Protective film, 19, 19A, 19B, 19C... Mask, 20... Channel region forming part, 21... Semiconductor integrated circuit device, 22... Printed circuit board, 23... Wiring, 24... Wire, 25... Package, 26... MXa irradiation mask, 27... Pattern, 28... X-ray. Fig. 2 Fig. 1/, 4) Fig. 3 (A) Fig. 3 (B) Fig. 3 C to Fig. 3 (f)) Fig. 4 Innel M/5FETnL? \1st Nao jL No. 5
FIG. 1 l, l/L ρJ2 0<2 Fig. 6 (B) Product 1 1:2■ Q79B

Claims (1)

[Claims] 1. A plurality of insulated gate field effect transistors of a predetermined conductivity type having a first threshold voltage or a second threshold voltage are connected in series to constitute an element array, and the element A semiconductor having a vertical read-only memory function, in which a plurality of columns are arranged in a row, and a plurality of word lines common to a predetermined insulated gate field effect transistor in each element column are arranged in a row. In the method for manufacturing an integrated circuit device, during or after the step of forming the insulated gate field effect transistor having the first threshold voltage, an X
1. A method of manufacturing a semiconductor integrated circuit device, comprising: irradiating an insulated gate field effect transistor with a radiation beam, and changing a first threshold voltage of the irradiated insulated gate field effect transistor to a second threshold voltage. 2. The insulated gate field effect transistor is a p-channel type having a first threshold voltage, and the first threshold voltage of a predetermined insulated gate field effect transistor is lowered by X-ray irradiation. Claim 1 characterized in that the second threshold voltage is also varied to a higher second threshold voltage.
A method for manufacturing a semiconductor integrated circuit device as described in 1. 3. The insulated gate field effect transistor is an n-channel type having a first threshold voltage, and the first threshold voltage of a predetermined insulated gate field effect transistor is lowered by X-ray irradiation. Claim 1 characterized in that the second threshold voltage is also varied to a lower second threshold voltage.
A method for manufacturing a semiconductor integrated circuit device as described in 1.