JPS60112320A - Protecting system of tristate gate - Google Patents
Protecting system of tristate gateInfo
- Publication number
- JPS60112320A JPS60112320A JP58219402A JP21940283A JPS60112320A JP S60112320 A JPS60112320 A JP S60112320A JP 58219402 A JP58219402 A JP 58219402A JP 21940283 A JP21940283 A JP 21940283A JP S60112320 A JPS60112320 A JP S60112320A
- Authority
- JP
- Japan
- Prior art keywords
- tristate
- gate
- outputs
- state
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、トライステートゲート保護方式に係り、特に
電源投入時、トライステートゲート破壊防止に好適な保
護回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a tri-state gate protection system, and particularly to a protection circuit suitable for preventing tri-state gate destruction when power is turned on.
第１図は、トライステートゲートを用いたデータ転送シ
ステムの１例を示すものであり、１はバス線、 ２−１
、２−２はトライステートゲートｊＡ、Ａｔはデータ
入力端子、均、Ｂ２はコントロール端子、５は一般ゲー
トを示している。Figure 1 shows an example of a data transfer system using tristate gates, where 1 is a bus line, 2-1
, 2-2 is a tri-state gate jA, At is a data input terminal, B2 is a control terminal, and 5 is a general gate.
第１図のデータ転送システムの動作は、例えばトライス
テートゲート２−１よりデータをバス線１を介して転送
する場合、ドライステートゲ−４２−２は、高インピー
ダンス状態にされる。In the operation of the data transfer system shown in FIG. 1, for example, when data is transferred from the tristate gate 2-1 via the bus line 1, the dry state gate 42-2 is placed in a high impedance state.
ところで、トライステートゲートに電源が投入された時
、トライステートゲートの出力は、高インピーダンス状
態となるか、高レベル状態となるか、あるいは、低レベ
ル状態になるかは一義的に定まらない。このため、第１
図のようにトライステートゲート中力が、共通のバス憇
１に接続されているシステムでは、電源を投入した時、
あるトライステートゲート出力は、高レベル状態となり
、他のトライステート出力が低レベル状態となる場合が
ある。このような事態が発生すると、高レベル状態のト
ライステートゲート出力から、低レベル状態のトライス
テートゲート出力に向って短絡電流が流れ、トライステ
ートゲートが破壊する。この問題点を解決する手段の１
例として、次のトライステートゲートの保護方式が知ら
れている。この動作は電源を投入した時、トライステー
トゲートのコントロール端子金てに、特定状態の論理レ
ベルを与え、出力を高インピーダンス状態にするもので
ある。この場合、高インピーダンス状態の電位は定義さ
れないため、バス線に接続されているシンクゲートが、
例えば、０ＭＯ８系ゲートの時、出力のＰチャネルＭＯ
３、ＮチャネルＭＯ８が共に導通状態となり、大電源電
流が流れ、破壊する危険性がある。By the way, when the tristate gate is powered on, it is not univocally determined whether the output of the tristate gate will be in a high impedance state, a high level state, or a low level state. For this reason, the first
In a system where tristate gates are connected to common bus 1 as shown in the figure, when the power is turned on,
Some tristate gate outputs may be in a high level state while other tristate outputs may be in a low level state. When such a situation occurs, a short circuit current flows from the tristate gate output at a high level to the tristate gate output at a low level, destroying the tristate gate. One of the ways to solve this problem
As an example, the following tri-state gate protection scheme is known. In this operation, when the power is turned on, a specific logic level is applied to the control terminal of the tristate gate, and the output is placed in a high impedance state. In this case, the potential of the high impedance state is not defined, so the sink gate connected to the bus line
For example, when using a 0MO8 system gate, the output P-channel MO
3. Both N-channel MOs 8 become conductive, causing a large power supply current to flow, leading to the risk of damage.
本発明の目的は、従来の問題点を除去するものであり、
′電源投入の際、トライステートゲートが破壊されない
ように保護すると共に、シンクゲートの破壊も保護する
トライステートゲートの保護回路を提供することにある
。The purpose of the present invention is to eliminate the problems of the prior art,
'An object of the present invention is to provide a tri-state gate protection circuit that protects the tri-state gate from being destroyed when the power is turned on and also protects the sink gate from being destroyed.
この発明の特徴とするところは、１本のバス線に接続さ
れた複数個のトライステートゲートを有するデータ転送
システムにおいて、電源投入時、複数個のトライステー
トゲートのコントロール端子を特定の状態にするため、
デコーダ回路を設げ、このデコーダ回路の複数出力を、
複数個のトライステートゲートのコントロール端子に接
続し、１個のトライステートゲート出力を高レベル状態
、又は低レベル状態にし、他のトライステートゲート出
力は、高インピーダンス状態にすることである。The feature of this invention is that in a data transfer system having a plurality of tristate gates connected to one bus line, when power is turned on, the control terminals of the plurality of tristate gates are set to a specific state. For,
A decoder circuit is provided, and multiple outputs of this decoder circuit are
It is connected to the control terminals of a plurality of tristate gates, one tristate gate output is in a high level state or a low level state, and the other tristate gate outputs are in a high impedance state.
以下、本発明の一実施例を第２図により説明する。バス
線１はトライステートゲート２−１及び２−２の出力と
接続され、シンクゲート５の入力端子に接続される。ト
ライステートゲート２−１及び２−２のコントロール端
子Ｂ、及びＢ、は、デコーダ４の複数出力に１対１で対
応して接続される。トライステートゲート２−１及び２
−２のＡ、及びＢ１は、データ入力端子である。An embodiment of the present invention will be described below with reference to FIG. Bus line 1 is connected to the outputs of tristate gates 2-1 and 2-2, and to the input terminal of sink gate 5. Control terminals B and B of tristate gates 2-1 and 2-2 are connected to a plurality of outputs of decoder 4 in one-to-one correspondence. Tri-state gates 2-1 and 2
-2 A and B1 are data input terminals.
電源は、トライステートゲート２−１及び２−２シツク
ゲート６、デコーダ４は共通である。The tristate gates 2-1 and 2-2 sick gates 6 and decoder 4 have a common power source.
上記構成において、電源が投入されると、デコーダ４の
複数出力は、１出力が低レベルの場合、他出力は高レベ
ルとなり、１出力が高レベルの場合、他出力は低レベル
になる機能であり、これらの状態は、デコーダ４の複数
入力の論理レベル状態によって決まる。デコーダ４の複
数出力状態０）、トライステートゲート２−１及び２−
２のコントロール端子Ｂ１及びＢ、に与えられると、一
方のトライステートゲート２−１あるいは２−２の出力
は、高レベル又は低レベル状態となる。この状態は、ト
ライステートゲート２−１あるいは２−２のデータ人力
Ａ、あるいはＡ２の論理レベル状態によって決まる。又
、他方のトライステートゲート２−１あるいは２−２の
出力は、高インピーダンス状態となる。これより、バス
線１の論理レベル状態は、高レベル又は低レベル状態と
なり、シンクゲート６の入力に伝達される。In the above configuration, when the power is turned on, the multiple outputs of the decoder 4 have the function that when one output is at a low level, the other outputs are at a high level, and when one output is at a high level, the other outputs are at a low level. These states are determined by the logic level states of multiple inputs of the decoder 4. Multiple output states 0) of decoder 4, tristate gates 2-1 and 2-
When applied to two control terminals B1 and B, the output of one tristate gate 2-1 or 2-2 becomes a high level or a low level state. This state is determined by the logic level state of data input A or A2 of tristate gate 2-1 or 2-2. Further, the output of the other tristate gate 2-1 or 2-2 is in a high impedance state. As a result, the logic level state of the bus line 1 becomes a high level or a low level state, and is transmitted to the input of the sync gate 6.
本実施例によれば、電源投入時において、共通のバス線
に接続され７こ複数のトライステートゲート出力間の短
絡電流は流れないため、トライステートゲートの破壊を
防止する効果がある。According to this embodiment, when the power is turned on, no short-circuit current flows between the outputs of the seven tri-state gates connected to a common bus line, which has the effect of preventing the tri-state gates from being destroyed.
本発明によれば、抵抗、コンデンサ、ダイオード、ラッ
チ回路等の複数部品を使用せずに、１個のデコーダ回路
で済まため、組立工数の低減効果がある。又、バス線の
論理レベルを高レベル又ハ低レベル状態にできるので、
シンクゲートの破壊防止の効果がある。According to the present invention, only one decoder circuit is required without using multiple components such as resistors, capacitors, diodes, latch circuits, etc., thereby reducing the number of assembly steps. Also, since the logic level of the bus line can be set to high level or low level,
It has the effect of preventing sink gate destruction.
【図面の簡単な説明】
第１図は従来のトライステートゲートを用いたデータ転
送システムの例を示すブロック図、第２図は本発明の一
実施例を示すブロック図である。
１・・・バス線
２−１及び２−２・・・トライステートゲート
６・・・シンクゲート
４・・・デコーダ回路
第 ７図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of a data transfer system using conventional tri-state gates, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Bus lines 2-1 and 2-2... Tri-state gate 6... Sink gate 4... Decoder circuit Figure 7
Claims (1)
ートを有するデータ転送システムにおいて、デコーダ回
路を設け、複数のトライステートゲートのコントロール
端子を、デコーダ回。 路の複数出力と接続することから成り、電源投入の際、
デコーダ回路の複数出力の特定論理し１ベル状態を用い
て、前記複数のトライステートゲート内、１１固のトラ
イステートゲート出力は高レベル又は低レベル状態、残
りのトライステートゲート出力は、高インピーダンス状
態にすることを特徴とするトライステートゲートの俳護
方式。1. In a data transfer system having multiple tri-state gates connected to one bus line, a decoder circuit is provided and the control terminals of the multiple tri-state gates are connected to the decoder circuit. It consists of connecting multiple outputs of the circuit, and when turning on the power,
Using a specific logic of the plurality of outputs of the decoder circuit and one bell state, among the plurality of tristate gates, 11 tristate gate outputs are in a high level or low level state, and the remaining tristate gate outputs are in a high impedance state. A tri-state gate protection method that is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58219402A JPS60112320A (en) | 1983-11-24 | 1983-11-24 | Protecting system of tristate gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58219402A JPS60112320A (en) | 1983-11-24 | 1983-11-24 | Protecting system of tristate gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60112320A true JPS60112320A (en) | 1985-06-18 |
Family
ID=16734844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58219402A Pending JPS60112320A (en) | 1983-11-24 | 1983-11-24 | Protecting system of tristate gate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60112320A (en) |
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