JPS60112312A - Edge trigger optical flip-flop circuit - Google Patents

Abstract

PURPOSE:To obtain an edge trigger optical flip-flop circuit by delivering a set optical signal and a reset optical signal when the data input optical signal is set levels 1 and 0 respectively at a time point of the edge of the rise or fall of a clock input optical signal. CONSTITUTION:A clock input optical signal 301 is transmitted through an optical branch circuit 213, an optical delay element 216 having delay time tau and an optical inverter circuit 218. Thus the signal 301 is delayed by tau and then an inverted optical signal 302 is obtained. Therefore an output optical signal 303 of an optical AND circuit 220 which performs an AND operation between the signal 301 and an optical signal 302 is turned into waveforms of levels 1 and 0 for a period tau between time points t1 and t2 and other periods respectively. An optical signal 305 of width tau is delivered if an input optical signal 304 is set at level 1 at the rise edge of the signal 301. While a reset optical signal 306 of width tau is delivered if the signal 304 is set at level 0.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an edge triggered optical flip 7μ horn circuit.

Conventionally, current mode logic, which uses a current switch as a basic block, has been known as a device that performs logical operations on electrical signals at high speed.9 Furthermore, in recent years, GaAs
Research into ultra-high-speed logical operation devices using FETs, Josephson coupling elements, etc. is progressing.

However, there are limitations in terms of calculation speed, power consumption, etc. in performing high-speed cyclical information processing of a large amount of two-dimensional data such as 1Ilii image information using the signal. Therefore, it is desired to realize an optical logic arithmetic circuit that can digitally process an optical signal as it is, which is compatible with high-speed, two-dimensional parallel information processing. For such an optical logic operation circuit, it is essential to realize an optical flip-flop circuit that can read and write optical information. Among these optical flip-flop circuits, the enon-trigger optical 7-line flip-flop circuit, which can set or re-set the output optical signal according to the state of each input optical signal at the edge of the input optical signal, has an extremely wide range of applications. .

An object of the present invention is to provide an edge-triggered optical flip-flop circuit composed entirely of optical devices.

According to the present invention, when the data input optical signal and the input optical signal are inputted, if the data input optical signal is level at the time of either the rising edge or the falling edge of the input optical signal, the set optical signal is set. An edge-triggered optical flip-flop comprising: an optical circuit that emits a reset optical signal when the output signal is at 0 level; A circuit is obtained.

Further, according to the present invention, an optical set-reset flip-flop, an optical branching circuit that branches the output optical signal of the set-reset flip 7μ tube, and an optical The first data input optical signal, the second data input optical signal, and the second input optical signal are input. When the output optical signal is set to 1V and the first data is 1V, the output optical signal is output to the optical center reset flip-flop, and the output optical signal is set to 1V and the second data An optical circuit that outputs a reset optical signal to the optical sector reset flip-flop when the input optical signal is at 0 level can be obtained. The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention. 1st
According to the figure, the first embodiment of the present invention has an end face 100 of -10,000
an optical waveguide 1 into which an input optical signal is incident, and an optical circuit 10 whose first input end is in contact with the other end surface of the optical waveguide 101.
4, an optical waveguide 103 whose one end surface 102 receives the p-c input optical signal CK, and whose other end surface contacts the second input end of the optical circuit 104;
an optical waveguide 105 whose end faces are in contact with each other; an optical set-reset flip-flop 107 whose set optical signal input S is in contact with the other end face of the optical waveguide 105; and an optical center whose one end face is connected to the second output end of the optical circuit 104. an optical waveguide 106 whose other end surface is in contact with the reset optical signal input end R of the reset flip-flop 107;
and an optical waveguide 108 that outputs an output optical signal Q from the optical waveguide.

The optical circuit 104 outputs a set optical signal through the optical waveguide 105 if the input optical signal is level at the edge determined as either the rising edge or the falling edge of the reverse input optical signal CK. The signal is sent to the optical sector reset flip-flop 107. As a result, if the output optical signal emitted from the output end 109 was at the 0 level immediately before the predetermined edge, it changes from the O level to the level, and if it was at the level, it is maintained at the level. On the other hand, if the input optical signal is at the 0 level at the predetermined edge point, the optical circuit 04 sends the reset optical signal through the optical waveguide 106 to the optical sector reset flip-flop 10.
Send on 7. As a result, if the output optical signal emitted from the output end 109 was at the level immediately before the predetermined edge, it changes to the θ level, and if it was at the θ level, it is maintained at the 0 level.

The optical set/reset flip knob full knob 107 can be realized by combining a semiconductor laser having hysteresis characteristics and an optical inverter circuit using the semiconductor laser. The Optical Set Resent Flinop Flop Circuit is described in detail in Patent Application No. 1984-042573 entitled "Optical Set Resent Flinop Flop Circuit."

r+) 104 is an optical waveguide 201 whose end face 200 receives an input optical signal, an optical branch circuit 202 whose input end is in contact with the other end face of the optical waveguide 201, and a first output end of the optical branch circuit 202. An optical waveguide 203 whose one end surface is in contact with the optical waveguide 203, and an optical waveguide whose first input end is in contact with the other end surface of the optical waveguide 203.
A DAND circuit, an optical waveguide 205 whose one end surface is in contact with the output end of the optical AND circuit 204 and which emits the sent optical signal S from the other end surface 225, and one end surface is in contact with the second output end of the optical branch circuit 202. the original inverter circuit 208 whose input end is in contact with the other end face of the optical waveguide 206; the optical waveguide 209 whose one end face is in contact with the output end of the optical impark circuit 208; and the other end of the optical waveguide 209. an optical AND circuit 210 whose first input end is in contact with the end surface of the optical AND circuit 210;
an optical waveguide 211 that outputs a reset optical signal R from 26; an optical waveguide 212 that receives a clock input optical signal CK on one end surface 224; and an optical branch circuit 2 in which the other end surface of the optical waveguide 212 contacts the input end] 3 and optical branch circuit 213
an optical waveguide 214 whose one end face is in contact with the first output end of the optical waveguide 214 , an original AND circuit 220 whose first input end is in contact with the other end face of the optical waveguide 214 , and a second output end of the optical branch circuit 213 . Optical waveguide 215 and optical waveguide 2 whose end faces are in contact with each other
An optical inverter circuit 218 whose input end is in contact with the other end face of the delay path 217 whose input end is in contact with the other end face of the optical inverter circuit 217;
An optical waveguide 219 whose other end surface is in contact with the second input end of the ND circuit 220; an optical waveguide 221 whose end surface is in contact with the output end of the optical AND circuit 220; and an optical waveguide 221 whose input end is in contact with the other end surface of the optical waveguide 221. The optical branch circuit 222 is in contact with the optical branch circuit 222, and one end face is attached to the first output end of the optical branch circuit 222 to the optical AND circuit 2.
An optical waveguide 20 whose other end surface is in contact with the second incident end of 04
7 and the second output end of the optical branch circuit 222 are connected to the light 201 and 212 whose other end faces are in contact with the second input end of the optical AND circuit 210, and the optical waveguide 201 is connected to the input light. A signal input optical signal CK is input into the optical waveguide 212, respectively. Optical waveguide 1 in Fig. 1
05.106, the optical waveguide 20 in FIG.
5.211 is connected to the optical waveguide 105, the set optical signal S is sent to the optical waveguide 106, and the reset optical signal is sent to the optical waveguide 106. FIG. In FIG. 3, an optical signal waveform 301 represents the clock input optical signal CK that is input to the end face 224, an optical signal waveform 302 represents the output optical signal of the original inverter circuit 218 that is input to the optical waveguide 219, and an optical signal waveform 303 represents the output optical signal of the original inverter circuit 218 that is input to the optical waveguide 219. The output optical signal of the optical AND circuit 220 that is input to the optical waveguide 221 is 1, and the optical signal waveform is 3.
04 represents the input optical signal incident on the end face 200, and the optical signal waveform 305 represents the set optical signal S emitted from the end face 225.
Assume that the optical signal waveform 306 is a reset light bell emitted from the end face 226, and assumes a positive logic in which the L level is the O level. The clock input optical signal 301 is sent to the optical branch circuit 21
The clock input optical signal 301 is delayed by τ, and an inverted optical signal 302 is obtained. Therefore, the output optical signal 303 of the optical AND circuit 220 which performs the logical product operation of the p-c input optical signal 301 and the optical signal 302 has a waveform of a level between times t and t2 and τ, and a 0 level waveform at other times. Here, the input optical signal 30'4 changes from level to O level at time t3 between time t1 and tx.
The output optical signal of the optical AND circuit 204 to which the optical signal 303 is inputted is a level from time 11 to τ, and is 0 otherwise.
A level set optical signal 305 is obtained. On the other hand, the output of the optical AND circuit 210 to which the optical signal obtained by inverting the input optical signal 304 by the optical inverter circuit 208 and the optical signal 303 is inputted is a reset light which is at level 0 from time t2 to τ and is at 0 level at other times. A signal 306 is obtained.

That is, if the input optical signal 304 is a level at the rising edge of the reverse input optical signal 301, a set optical signal 305 with a width τ is output, and if it is at 0 level, a reset optical signal 306 with a width τ is output. .

In this manner, the optical circuit shown in FIG. 2 performs the functions required of the optical circuit 104 shown in FIG. 1. However, if the input optical signal 304 changes between the rising edge of the pck input register signal -53oi and the time τ, both the set optical signal 305 and the reset optical signal 306 may be output. It is desirable that the delay amount τ is sufficiently small.

By using an optical waveguide for the optical delay ring 218, it is possible to stably obtain a small amount of delay.

FIG. 2(2) shows the second (2) of the optical circuit 104 shown in FIG.
1) is a diagram showing a specific example. FIG. 2 (2) shows the optical circuit in FIG. 2 divided by optical AND circuit 220 and optical waveguide 221.
, the optical branch circuits 22 and 2 are removed, and the optical waveguides 214 and 2 are
07, add 11 output ends of the optical branch circuit 213, connect the optical waveguide 223 to the added output ends, and create an optical AND
One additional input end of the circuit 204 is added, the added input end is connected to the optical waveguide 219, and one input end of the optical AND≠Tang circuit 210 is added, and the added input end and the optical inverter circuit 218 are connected. As described in the specific example of the optical inverter circuit, the output end and the four pins are connected by an optical waveguide 227, and it can perform the same logical operation as the U0 circuit shown in FIG. The number of optical devices can be reduced.

FIG. 4 is a diagram showing a third specific example of the optical circuit 104 shown in FIG. 1. In FIG. 4, the optical circuit 104 has an end face 4
00, an optical waveguide 401 into which an input optical signal is incident, an optical branching circuit 402 whose input end is in contact with the other end face of the optical waveguide 401, and one end face which is in contact with the first output end of the optical branching circuit 402. The optical waveguide 403 and the set optical signal input end S are in contact with the other end surface of the optical guide path 403. An optical waveguide 405 whose one end surface is in contact with Q, and an optical branch circuit 4 whose input end is in contact with the other end surface of the optical waveguide 405.
06, an optical waveguide 407 whose one end surface is in contact with the first output end of the optical branch circuit 406 and outputs the set optical signal S from the other end surface 407, a second inverter circuit 411 of the optical branch circuit 406, - A clock input signal CK is input to the end face 431 of the
an optical waveguide 417 into which the light is incident, an optical branching circuit 418 whose input end is in contact with the first end of the optical waveguide 417, and an optical J4 waveguide 412 whose one end is in contact with the first output end of the optical branching circuit 418; an optical AND circuit 413 whose first input end is in contact with the other end surface of the optical waveguide 412;
Reset one end face to the output end of the other end face Reset the priority party set reset flip-flop 404 Reset the optical waveguide 414 in contact with the optical signal input end R and the end face of 10,000 in contact with the output end of the optical inverter circuit 411 An optical waveguide 416, a reset priority optical center reset flip-flop 425 whose reset optical signal input end S is in contact with the other end face of the optical waveguide 416, and an optical waveguide whose one end face is in contact with the second output end of the optical branch circuit 418. 419, an optical AND circuit 423 whose first input end is in contact with the other end surface of the optical waveguide 419, an optical inverter circuit 421 whose input end is in contact with the other end surface of the optical waveguide 409, and an output end of the optical inverter circuit 421. The optical waveguide 420 has an end face of 10,000 in contact and the other end face is in contact with the second input end of the optical AND circuit 423, and an end face of 10,000 in contact with the output end of the optical AND circuit 423 and a reset priority light set reset flinopfp. an optical waveguide 424 whose other end surface is in contact with the reset optical signal input end R of the knob 425; and an optical waveguide 426 whose one end surface is in contact with the output optical signal output end Q of the reset priority light set reset fly knob knob P knob 425; An optical branch circuit 427 whose input end is in contact with the other end face of the optical waveguide 426; an optical waveguide 428 whose end face is in contact with the first output end of the optical branch circuit 427; and an optical waveguide 428 whose input end is in contact with the other end face of the optical waveguide 428. an optical inverter circuit 422 in contact with
Connect the optical AN to the output end of the optical inverter circuit 422.
An optical waveguide 415 whose other end surface is in contact with the second input end of the D circuit 413, and an optical waveguide whose other end surface is in contact with the second output end of the optical branch circuit 427 and which outputs the reset optical signal R from the other end surface 430. wave path 429. Reset Priority Optical Set Reset 7 Lip Fronno 7' 404, 425 is a flip-flop that is reset when the conversion optical signal S is level and is reset when the reset optical signal R is O level. If the optical signals reach level 0 and level 0 at the same time, priority is given to set.

FIG. 5 is a diagram showing a time chart for explaining the operation of the third specific example of the optical circuit 104 shown in FIG. 4.

In FIG. 5, an original signal waveform 501 represents the input optical signal incident on the end face 400, and an optical signal waveform 502 represents the input optical signal CK'fr, , light (if
The optical signal waveform 503 represents the sent optical signal S emitted from the end surface 408, and the optical signal waveform 504 represents the reset optical signal R emitted from the end surface 430.

During the period when the clock input source signal 502 is at the O level, the output optical signal of the optical M circuit 413 and the output 423 is at the 0 level.

Therefore, the reset priority set reset flip 70 knobs 404 and 425 are reset and the set optical signal 5θ
3 and 504 are both 0 level. Also seven))
The output optical signals of the optical inverter circuits 421 and 422, to which the optical signals 503 and 504 are respectively input, are in level. When the set pk input signal 502 changes from the O level to the level, the output optical signals of the original AND circuits 413 and 423 become the level. At that time, if the input optical signal 501 is a level, the reset priority set reset flip 70 knob 404 is set and the set optical signal 501 is set.
3 becomes a level, and conversely, when the input optical signal 501 is at level 0, the output optical signal of the optical inverter circuit 411 is a level, so the reset priority set reset flip-flop 425 is set and the reset signal 504 becomes a level. Once set priority set recent flip 70 knob 4
If either 04 or 425 is set,
The output optical signal of each optical inverter circuit 421 or 422 is maintained at the θ level. The Rakuko light AND circuit 4
The output optical signal of 23 or 413 becomes 0 level, and the other of the reset priority set reset flip-flops 404 or 425 is kept in a centrifugal state. Therefore, even if the input optical signal changes while the input optical signal 502 is at the level, the output optical signals of the reset priority set reset flip-flops 404 and 425 do not change, and the output optical signals of the input optical signal 502 do not change. The set optical signal 503 or the reset optical signal 504 is maintained at the level.

Input light amount Pl of the optical signal incident on the optical signal input end
It is possible to use an optical bistable element whose characteristic of the amount of emitted light Pa++1 with respect to n is bistable as shown in FIG.

The bistable characteristic in Fig. 6 shows that when the amount of incident light is increased from 0, the output light -i P, , increases rapidly at P, and conversely, when Pl, , is decreased from Pl, the output Light emitted:
p, , exhibits a hysteresis characteristic that rapidly decreases at P6, and when bias light of light amount P is applied to the input end, the output light amount P, .・, = P, two stable points 0 of P,
A and point B).

FIG. 7 is a diagram for explaining the operation of reset priority set reset flip-flops 404 and 425.

In FIG. 7, an optical signal waveform 701 is a set input optical signal S
, the optical signal waveform 702 represents the input optical signal π, the optical signal waveform 703 represents the input optical signal P5m, and the optical signal waveform 704 represents the input optical signal P5m.
represent the output optical signal POul, ie, Q, respectively. The set optical signal 701 is Pl at level and O at level 0.
The reset source signal 702 is Pb in Lebel.
, the output optical signal 704 takes a light amount of O at the level O, and the output optical signal 704 takes the light amount of P8 at the level and Pa at the θ level. At this time, Ph so that pc>Ph>P, -P,
, Pb. At time point -, it is assumed that the reset-priority optical centric flip-flop 404 is in the set state, the output optical signal 704 is at the level, the centripetal input optical signal 701 is at the θ level, and the reset input optical signal 702 is at the level. In this state, a set optical signal 701 and a reset optical signal 702
Incident light ftP1 . of the total input optical signal 703 obtained by adding is P+,=Pb, and the reset priority optical set reset flip 404 is maintained at point A in the cent state shown in FIG. The incident light amount P+- of 703 is P+
fi=0, the optical set reset button 404 is reset, and the output optical signal 704 becomes O level. Even if the reset input optical signal 702 becomes a level at time t2, the incident light of the total input optical signal 703 it P+fi=
Since it is Pb, the reset priority light sesotricenotofuriknob μ knob 404 is maintained at the reset state of 8 points in FIG. When the input optical signal 701 reaches the level at time t3, the incident light of the total input optical signal 703 ★Pla=80Ph
becomes P- and reset priority is applied. The set output optical signal 704 becomes a rubel. Even if the set input light %01 becomes O level at time number t4, the incident light ML P l a - P b of the total input optical signal 703 remains, so the recent f destination i seno tricent flyknob flop 404 is as shown in FIG. The sector state is maintained at point A at .

At time t5, when the set optical signal 701 becomes level and the reset source signal 702 becomes O level, the total input optical signal 703 becomes
Since the incident light of it P + n = Pb < Pe, reset priority light center reset flimp p knob 404
is reset, and the output optical signal 704 becomes 0 level.

FIG. 8 is a diagram illustrating an embodiment of an optical bistable device that can be used as reset-prioritized sesotricenotophronopronops 404 and 425.

Figure 8 (a) is an optical bistable element using a directional coupling type switch, and by feeding back a part of the output light of the original switch to the applied voltage of the optical switch, the human emitted light as shown in Figure 6 is generated. In No. 1111(a), 81O is a directional coupling type optical switch, 811 is a semi-transparent mirror, 812 is a photodetector, and 813 is a voltage amplifier.

For details on the operating principle, please refer to the following literature: IEE, Journal Opquantum Electronics, QEE 14
IEEE Journal of Quantum
Electronics, vol, QE-14)
It is stated on pages 577 to 580. FIG. 8(b) shows a bistable semiconductor laser. By providing a saturable absorption part, for example, a part into which no current is injected, in a part of the resonator of a semiconductor laser, the injection current vs. optical output characteristic can be made bistable. By selecting this, the human emission light characteristics shown in FIG. 6 can be obtained. Details of the above bistable semiconductor laser can be found in the literature.
Electronics L
etter) Volume 17, page 741 and Proceedings of the 157th National Conference of the Institute of Electronics and Communication Engineers, Optical and Radio Division (Volume 2)
) stated in number 272.

FIG. 9 is a diagram showing a second embodiment of the present invention.

According to FIG. 9, the second embodiment of the present invention has one end surface 9.
An optical waveguide 902 into which an input optical signal J is input into 01, an optical waveguide 904 into which an input optical signal CK is input into one end face 903, and an optical waveguide into which an input optical signal K is input into one end face 905. Wave path 906 and optical waveguides 902 and 904
The other end face of the workpiece 906 is the first, second and third, respectively.
an optical circuit 908 in contact with the incident end of the optical circuit 908;
The optical waveguide 910 has an end face of 10,000 in contact with the second output end of the optical circuit 908, and the other end face of the optical waveguide 909 and the optical waveguide 910 An optical set/reset flip full tube 911 is in contact with the set source signal input end S and the reset optical signal input end R on the other end surface of the optical waveguide 9, and one end surface is in contact with the output end of the original St.
12, an optical branch circuit 913 whose input end is in contact with the other end face of the optical waveguide 912, and an optical branch circuit 913 whose one end face is in contact with the first output end of the optical branch circuit 913 and whose other end is in contact with the fourth input end of the optical circuit 908. It includes an optical waveguide 907 whose end faces are in contact with each other, and an optical waveguide 914 whose one end face is in contact with the second output end of the optical branching circuit 913 and outputs the output optical signal Q from the other end face 915.

The optical circuit 908 outputs the input optical signal J ifi level and the output light of the optical set reset flip 7p block 911 at the edge determined by either the rising edge or the falling edge of the reverse input optical signal CK. If the signal is 0 level C, a set optical signal S is sent to the optical set reset flip full tube 911. the result,
If the output optical signal Q emitted from the output end 915 was at 0 level immediately before the predetermined edge point, it changes from the θ level to the level, and if it was at the level, it is maintained at the level. - At a predetermined edge point, the input optical signal K is output to the optical center reset flip-flop 9.
If the output optical signal of 11 is a rubel, a reset optical signal R is sent to the optical set reset flip-flop 911.

As a result, if the output optical signal Q emitted from the output end 915 was at the level immediately before the predetermined edge, it changes from the level to the θ level, and if it was at the 0 level, it is maintained at the 0 level.

FIG. 10(1) shows the first part of the optical circuit 908 shown in FIG.
It is a figure showing a specific example. 10(1) and FIG. 2(1) indicate the same components as in FIG. 2. The optical circuit 908 includes an optical waveguide 1001 into which the flip-flop output optical signal Q is incident on one end surface 1000, an optical branch circuit 1002 whose input end is in contact with the other end surface of the optical waveguide 100, and an optical branch circuit 1002. An optical waveguide 1003 whose first output end is in contact with the 10,000 end face, an optical inverter circuit 1004 whose input end is in contact with the other end face of the optical waveguide 1003, and an optical waveguide whose 10,000 end face is in contact with the output end of the optical inverter circuit 1004. A wave path 1005 and an optical AND circuit 10 that connects the optical waveguide 1005 with the first input end.
06, an optical waveguide 1009 whose one end face 1oos receives the input optical signal J, and the other end face is in contact with the second end face of the optical AND circuit 1006, and the second end face of the optical branch circuit 1002.
An optical waveguide 1007 whose output end is in contact with the 10,000 end face, an original AND @ path 1012 whose first input end is in contact with the other end face of the optical waveguide 1007, and an input optical signal K is incident on the end face 1010 of 1y5. The end face of the optical AND circuit 1012
and an optical waveguide 1011 in contact with the second input end of the optical waveguide.

FIG. 11 shows the first part of the optical circuit 908 shown in FIG. 10(1).
This is a time chart for explaining the operation of a specific example. In FIG. 11, an optical signal waveform 1100 indicates the clock input optical signal CK, and an optical signal waveform 1101 indicates the clock input optical signal CK.
0, and the optical signal waveform 1102 is the input optical signal J.
, the optical signal waveform 1103 represents the input optical signal K, the optical signal waveform 1104 represents the flip-flop output optical signal Q incident on the end face 1000, the optical signal waveform 1105 represents the set output optical signal S, and the optical signal waveform 1106 represents the reset output source signal. R is represented respectively. Similarly to FIG. 2, the output optical signal 1101 of the optical AND circuit 220 is a level with a width below the delay time of the optical delay element 216 from the stop edge t of the rise of the input optical signal 1100 and t2. Become. Assume that at time t, the input optical signal 1102 is at the level, the input optical signal 1103 is at the O level, and the flip-flop output optical signal 1104 is at the 0 level. At this time, the output optical signal of the optical inverter circuit 1004 becomes a level. From time t1 to τ
All three input optical signals of the optical AND circuit 1006 become the level, and the set output optical signal 1105, which is the output optical signal of the optical AND circuit 1006, becomes the level for a period of τ from time t. The center output optical signal 1105 is input to the center optical signal input end S of the original set reset flip 911 shown in FIG. The output optical signal 1104 is also at time t.
The bell becomes 1 with a delay of ψ from 1. On the other hand, at time t2, the input optical signal 1102 is O level input optical signal 11
03 is a rubel, and the flip-flop output optical signal 1104 is a rubel. At this time, all three input optical signals of the optical AND circuit 1012 become a level for a period of τ from time t2, and the reset output optical signal 1106, which is an output optical signal of the optical AND circuit 1012, becomes a level for a period of τ from a time t2. The reset output optical signal 106 is input to the reset optical signal input end R of the optical set reset frib knob in FIG. 9, and the operation delay time ψ starts from time t2.
After a delay, the optical set/reset flip-flop 911 is reset, and the flip-flop output optical signal 1104 also reaches ψ from time t2 (it gradually becomes 0-level).

In this case, τ must be small compared to ψ. For example, at times t1 and t2 in FIG.
2 and the input optical signal 1103 are both 1 level, and if τ is thicker than 9, even if the flip-flop output optical signal 1104 becomes 0 level with a ψ delay from time t1, the output optical signal of the optical AND circuit 220 Since the signal 1101 maintains the l level, all three input optical signals to the optical AND circuit 1012 become level. As a result, a reset output optical signal 1106 is emitted from the once set flip 7p.
A phenomenon occurs in which the knob 911 is reset. Similarly, even if the slip prop output optical signal 1104 becomes the level with a ψ delay from time 1°, the output optical signal 1101 of the optical AND circuit 220 still maintains the level, so the optical AND
All three input optical signals to circuit 1006 are in rubel. This causes a phenomenon in which the set output optical signal 1105 is emitted and the once reset flip-flop 911 is set.

FIG. 10(2) shows the second optical circuit of the optical circuit 908 shown in FIG.
It is a figure showing an example of. FIG. 10 (2) shows that the optical AND circuit 220, the optical waveguide 221, and the optical branch circuit 222 are removed from the optical circuit in FIG. An optical waveguide 223 is added and connected to the added output end, and the optical AND circuit 10
06, and connect the added input end to the optical waveguide 219, and connect the input end of the optical AND circuit 1012 to 1.
The newly added input end and the output end obtained after the original inverter circuit 218 as described in the specific example of the optical inverter circuit are connected by a new optical waveguide 10 (3). The same logical operation as the optical circuit shown in FIG. 10 can be performed, and the number of optical devices can be reduced.

FIG. 12 is a diagram showing a third specific example of the optical circuit 908 shown in FIG. 9. In FIG. 12, the same numbers as in FIG. 4 indicate the same components as in FIG. 4. According to FIG. 12, the optical circuit 908 shown in FIG. 9 further has an optical waveguide 1201 into which the slip prop output optical signal is incident on one end face 1200, and an input end on the other end face 1 of the optical waveguide 1201. An optical branching circuit 1202, an optical waveguide 1203 whose end face is in contact with the first output end of the optical branching circuit 1202, an optical inverter circuit 1204 whose input end is in contact with the other end face of the optical waveguide 203, and an optical inverter circuit. Optical waveguide 1 whose one end surface is in contact with the output end of 1204
205, an optical AND circuit 1206 in which the optical waveguide 1205 is in contact with the first input end, and an optical guide in which the J input optical signal is input to one end face 1208 and the other end face is in contact with the second input end of the optical AND circuit 1206. Wave path 1209 and one end face 1
21O, an optical waveguide 1211 into which an input optical signal is input, an optical AND circuit 1212 whose first input end is in contact with the other end surface of the optical waveguide 1211, and a second optical branch circuit 1202.
One end face is in contact with the incident end of the optical M-width circuit 1, and the other end face is in contact with the incident end of
and an optical waveguide 1207 in contact with the second input end of 212 .

FIG. 13 is a time chart for explaining the operation of the third specific example of the optical circuit 908 shown in FIG. 12. 1st
In FIG. 3, an optical signal waveform 1300 represents a flip input optical signal CK, an optical signal waveform 1301 represents an input optical signal J, an optical signal waveform 1302 represents an input optical signal K, and an optical signal waveform 1303 represents a flip input optical signal CK input to an end face 1200. The optical signal waveform 1304 represents the set output optical signal S, and the optical signal waveform 1305 represents the reset output optical signal R. Similarly to FIG. 4, during the period when the input optical signal is at the O level, the output priority reset control knobs 404 and 425 are reset and the output optical signal 1 is set.
304 and the reset output optical signal 13o5 are both at the θ level. Time 1 in FIG. It is assumed that the input optical signal 1301 is at the level, the input optical signal 1302 is at the θ level, and the flip-flop output optical signal 1303 is at the 0 level. At this time, the flip-flop output optical signal 1303
Since the output optical signal of the optical inverter circuit 1204 which is inputted is a rubel, the two input optical signals of the optical AND circuit 1206 are both a rubel, and the output optical signal of the optical AND circuit 1206 is a rubel. In this way, the reset priority set recent flip flop 404 is supplied with the set input optical signal. However, since the clock input optical signal 1300 is at O level, the reset input optical signal of the reset priority center reset slip 70 knob 404 is 0.
level, and the reset input optical signal has priority. When the optical input signal 1300 rises to the level at time t1 while the input optical signal 13o1, the input optical signal 1302, and the slip-prop output optical signal 13o3 maintain the same state as to, the reset priority set reset 7 lip-flop 404 inputs The optical signal becomes a rubel and optical AND
The set input source signal output from the circuit 1206 becomes valid, and the reset priority center reset flip-flop 404 is set. The output optical signal 1304 of the reset priority center reset flip-flop 7' 404, which has been reset once, is transmitted at time 1. clock input optical signal 130 from
It is maintained at the level until time t2 when 0 becomes the θ level. The set output optical signal 1304 is input to the set optical signal input end S of the optical sensor reset button 911 in FIG. The p knob 911 is set and the flip-flop output optical signal 1303 becomes a level. Next, at time t, it is assumed that the roaring °C input optical signal 1301 is at the θ level, the input optical signal 1302 is at the level, and the flip-flop output optical signal 1303 is at the level. At this time, the two input optical signals of the optical AND circuit 1212 are all level, and the output optical signal of the optical AND circuit 1212 is level, and the reset priority center reset flip-flop 425
A set input optical signal is applied to. However, the stiffness p
Since the input optical signal 1300 is at the θ level, it is reset)
The reset input optical signal of the f-first set reset flip-flop 425 is at 0 level, and priority is given to the reset input optical signal.

When the input optical signal 1301, the input optical signal 1302, and the flip-flop output optical signal 1303 remain in the same state as at time t3 and the input optical signal 1300 rises to the level at time t4, the reset priority set reset 7 reset button is activated. The reset input optical signal 404 becomes a level, the set input optical signal output from the optical AND circuit 1212 becomes valid, and the reset priority reset flip-flop μtub 425 is set. Once set, the output optical signal 1305 of the set priority set reset flip-flop 425 is clock input optical signal 1 from time t4.
It is maintained at the level until time t5 when 300 becomes O level.

It is reset after a delay of the extension time ψ, and the flip-flop output optical signal 1303 becomes the θ level.

FIG. 14 shows an example of the optical AND circuit used in the above explanation. In FIG. 14, the optical AND circuit includes a semiconductor laser 14 having a saturable absorption portion in the common camera.
Output light 1 realized by 01 and output from the active layer
402 is an output, and input light 1403, input light 1404, and input light 1405 injected into the active layer from the outside are input. The input light 1403.140 is set by setting the operating point in a semiconductor having a low absorption part in the common camera.
4.The total light amount P l m obtained by adding the light amounts of 1405 and the light amount P of the output light. A differential gain characteristic can be provided in the characteristic 1 between 11 and 11. Details of the semiconductor L laser having such a differential gain characteristic are described in the document IEICE technical research report ED81-10, page 7.

FIG. 15 is a diagram for explaining the operation of a semiconductor laser having differential gain characteristics used in the optical AND circuit,
Input light 1403, 1404, ]405 in Fig. 14
The total light amount Pi, which is the addition of the light amounts Pam5, Pie4, and PIas, =P+-3+P+. 4,000 P1ml+
It shows the relationship between Po□ and the amount of output light Po□. That is, when increasing the total light % of input light (Pie and 0), PIll=Pl.

The light iP of the output light changes suddenly from almost 0 to P,
,.

= Pl, and then the total amount of input light becomes Pl
a ”'Even if it is increased from Ptb, the output light i#P,,
, takes a constant value of approximately P6 m l ” p, and P
It shows differential gain near l. At this time, input light 3.4.
When the light amounts P1, 3, Pie4, and Plafi of 5 are input logic level 0, Ram2 PI na. , Pld ==p,
,,4゜,"lnB"PLaS6 and at input logic level "1", P+++a "'P1.3+, Pl, 4=
Suppose that PL is 4□. Further, at the output logic level 0 of the output light 2, the light quantity of the output light P,...l=0, and at the output logic level "'l", the light quantity of the output light P6uI=P1. In the optical palm circuit, O<P1113°, pH 14o.

P2,5゜not sleepy R-s8, Pl, 4□, Pl.

6, <Pt, and 3 PlmgOI Plmml, Pl, 4°, P
11141, set PIIISOlPlmlll.

By doing so, the input light 1403.140
4. Plmm where all 1405 are input logic level “1”
l, Pl++41. Only when Plmml is the total amount of input light P, ・=Pla$ +PII144'+a+
When + > Rb, the output light quantity Pbu+ -PH, the output logic level becomes 1'', realizing the operation of an AND logic circuit.

FIG. 16 is a diagram showing an example of an optical inverter circuit.

According to FIG. 16, the optical inverter circuit emits two output lights 16o4 from the junction surface in the direction of the reflecting surfaces 1602 and 16o3 of the Febrivé p-resonator, and furthermore, the optical inverter circuit emits two output lights 16o4 from the junction surface in the direction of the reflection surfaces 1602 and 16o3 of the Febrivé p-resonator, and furthermore, the optical inverter circuit emits two output lights 16o4 from the junction surface in the direction of the reflection surfaces 1602 and 16o3 of the Febrivé p-resonator. Input light 1
The half to which the laser beam 605 is incident is constituted by a conductor laser 1601. When the human power light 1.605 is not incident, the population inversion inside the semiconductor laser 16o1 is uniform, and the semiconductor laser 16o1 produces two output lights 16o4 in the direction where the stimulated emission due to the resonance of the Fepribe p-cavity is maximum. is emitting.

If the coherent input light 16o5 is incident on the plane of the junction in a direction that crosses the output light 1604, and the intensity PIn of this human-powered light 16o5 is greater than the intensity P, □ of the output light 1604, it is due to population inversion within the semiconductor laser 16o1. Photons are stimulated and emitted more strongly in the direction of the human power light 16o5 than in the direction of the output light 16o4. As a result, the population inversion that contributes to light emission in the direction of the output light 1604 is reduced, and the light emission of the output light 1604 is stopped.

FIG. 17 is a first diagram for explaining the operation of the optical inverter.
6 is a diagram showing the relationship between Pl++ and Pol in FIG. 6. FIG. In Fig. 17, when pHl is O, Pb is output, and when a light amount P greater than the threshold scene pth is input, P
6° becomes 0. Therefore, the state where P l a is the light amount P is the input logic level i, the state where the pin is the light amount Ph is the input logic level 0, the state where P6Ul is the light amount Pb is the output logic level 1, and the state where P6Ul is the light amount Pb is the output logic level 1. By making a certain state correspond to an output logic level of 0, an inverter in which the input logic level and the output logic level are inverted is realized.

Regarding the phenomenon of oscillation stop due to injection light of the semiconductor laser in Fig. 16, see the document Soviet Physics Semiconductors (5oviet Physics-Sem).
1 conductors) Volume 3 No. 3 September 1969,
It is explained in detail on page 314.

As described above, the present invention provides an edge-triggered optical flip knob that can set or reset the output optical signal according to the state of various input optical signals at the edge of the μ-link input optical signal. .

In the above, detailed explanation has been provided only about the edge-triggered optical flip-flop that operates on the rising edge of the ripple input optical signal, but the edge-triggered optical flip-flop that operates on the falling edge of the ripple input optical signal is explained in detail. can also be configured in exactly the same way.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the first embodiment of the present invention, FIG. 2 (1)
1 is a diagram showing a first specific example of the optical circuit 104 shown in FIG. 1, and FIG. 2 (2) is a diagram showing the optical circuit 1 shown in FIG.
6 is a diagram showing the characteristics of the set-priority set-reset flip-flop shown in FIG. 4, and FIG. 7 is a diagram showing the operation of the reset-priority set-reset flip-flop. Figure 8 (,) is a diagram showing a specific example of the reset priority set reset flip-flop 404, 425, Figure 8 (b) is a diagram showing a bistable semiconductor laser, and Figure 9 is a diagram for explaining the present invention. FIG. 10 (1) is a diagram showing a first specific example of the optical circuit 908 shown in FIG. 9, and FIG. FIG. 11 is a diagram for explaining the operation of the first specific example of the optical circuit 908, and FIG. 12 is a diagram showing a third specific example of the optical circuit 908. FIG. 13 is a diagram for explaining the operation of the third specific example of the optical circuit 908, FIG. 14 is a diagram showing the specific example of the optical AND circuit ψ1, and FIG. Figure shown, 1st
FIG. 6 is a diagram showing a specific example of the optical inverter circuit, and FIG. 17 is a diagram showing the characteristics of the optical inverter circuit. In the figure, 104 and 908 are optical circuits, and 107 and 911 are optical set/reset flip 7p tubes Z1202.
．． 213.222.402.406.418.427.
913.1002.1202 is an optical branch circuit, 204.
210.220.413.423.424.1006.
1012.1206 and 1212 are optical AND circuits,
208.218.411.421.422.1004,
and 1204 are the original inverter circuits, 404 and 4
Reference numeral 25 represents a reset priority setting reset function μ knob, 216 represents an optical delay element, and 1 and 1 represent semiconductor lasers, respectively. t1t2 R-11 Kitaichi, 306 474 42 & Whistle 7 Figure 8 Figure (a) (b) R-111'' -Re~. 5 pouts

Claims (1)

[Claims] 1. When a data input optical signal and a clock input optical signal are input and the clock input source signal rises or falls] At the time of one edge, the data input optical signal and the clock input optical signal are input. An edge-triggered optical flip-flop circuit comprising: a signal; and an optical set-reset flip-knob full-knob circuit into which a signal is input. 2. The input optical signal, the second data input optical signal, and the clock input optical signal are input to the optical set reset flip-flop, the output optical signal of the set reset flip-knob full knob, and the rising and falling edges of the clock input optical signal are input. If the optical set reset flip full knob output optical signal is at the θ level and the first data input optical signal is level at the time of one of the edges, outputs a cent optical signal to the optical set reset flip knob full knob and resets the optical set. an optical circuit that outputs a reset optical signal to the optical set reset flip knob full knob when the flip full knob output optical signal is at the level and the second data input optical signal is at the θ level. Optical flip-flop circuit.