JPS61153900A - Optical information memory circuit - Google Patents

Optical information memory circuit

Info

Publication number
JPS61153900A
JPS61153900A JP59277290A JP27729084A JPS61153900A JP S61153900 A JPS61153900 A JP S61153900A JP 59277290 A JP59277290 A JP 59277290A JP 27729084 A JP27729084 A JP 27729084A JP S61153900 A JPS61153900 A JP S61153900A
Authority
JP
Japan
Prior art keywords
electric current
incident light
light
amount
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59277290A
Other languages
Japanese (ja)
Inventor
Shuji Suzuki
修司 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59277290A priority Critical patent/JPS61153900A/en
Publication of JPS61153900A publication Critical patent/JPS61153900A/en
Pending legal-status Critical Current

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  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To make an optical inverter unnecessary and to execute a room temperature action by changing an injected electric current from an electric current supplying circuit to a bistable semiconductor laser in accordance with the output electric signal of the photoelectric converter. CONSTITUTION:A binary seven setting incident light 11 are photodetected by the photoelectric converter 13, and an electric current supplying circuit 14 is controlled by the binary signal from the converter 13. When the incident light 11 is zero, the light quantity of an emitting light 16 is drastically increased at a bistable semiconductor 15, the electric current (i) of the middle value of the injected electric current values I1 and I2 to show a hysteresis characteristic which drastically decreases following the decrease of injected electric current value is supplied to a laser 15, and the laser 15 outputs the emitting light 16 in accordance with the incident light 12. On the other hand, when the incident light 11 goes to be 1 of a binary, an output electric current (i) from the circuit 14 becomes smaller than the electric current value I2, the laser 15 is reset, and the emitting light 16 is hardly emitted. By these, the light inverter, which processes the resetting incident light and is operated at the low temperature, becomes unnecessary, and the room temperature action can be executed for the set and reset an optical information memory circuit.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は光入力信号によってセット、リセットできる光
情報記憶回路に関わる。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an optical information storage circuit that can be set and reset by an optical input signal.

(従来技術の問題点) 従来、電気信号の論理演算を高速で行なうデバイスとし
てはカレント・スイッチを基本ブロックとしたカレント
モードロジックが知られており更には近年GaAs F
ETやジョセフソン結合素子等を用いた超高速演算回路
の研究が進められている。
(Problems with the prior art) Current mode logic, which uses a current switch as a basic block, has been known as a device that performs logical operations on electrical signals at high speed, and in recent years, GaAs F
Research is progressing on ultrahigh-speed arithmetic circuits using ETs, Josephson coupling elements, and the like.

しかしながら画像情報等の2次元的で大量なデータの高
速ディジタル情報処理を電気信号で行うには演算速度、
消費電力等の面で限界がある。このため高速で2次元並
列の情報処理に親和性のある光信号を光のままディジタ
ル情報処理すやことのできる光論理演算回路の実現が望
まれておりこのような光論理演算回路には、光情報を読
み書きするこ−どのできる光情報記憶回路が不可欠であ
る。
However, in order to perform high-speed digital information processing of large amounts of two-dimensional data such as image information using electrical signals, the calculation speed is
There are limits in terms of power consumption, etc. For this reason, it is desired to realize an optical logic arithmetic circuit that can process optical signals as they are in the form of light, which is compatible with high-speed, two-dimensional parallel information processing. Optical information storage circuits that can read and write optical information are essential.

そのような光情報記憶回路として特願昭58 =’04
2573号明細書に記載されているものがあり、第4図
に示すように光インバータと双安定半導体レーザを使用
している。
A patent application for such an optical information storage circuit was filed in 1984 ='04.
There is one described in the specification of No. 2573, which uses an optical inverter and a bistable semiconductor laser as shown in FIG.

光インバータは発振している半導体レーザへ共振軸を膚
切る方向へ光を入射するとクエンチング効果によって発
振が停止する現象を利用したものである。入射光が入力
されなければ出射光が出力され、入射光が入力されると
出射光が停止するのでインバータの論理機能を果たして
いる。
Optical inverters utilize the phenomenon that when light is incident on an oscillating semiconductor laser in a direction that cuts through the resonance axis, the oscillation stops due to a quenching effect. When no incident light is input, the output light is output, and when the incident light is input, the output light is stopped, thus fulfilling the logical function of an inverter.

双安定半導体レーザは半導体レーザの共振器の一部に可
飽和吸収領域を有し、注入電流を適当に選ぶことによっ
て入射光量対出射光量特性にヒステリシスループを示す
。ヒステリシスループの立上り入射光量と立下り入射光
量の中間の光量のバイアス光を与えると発振しているセ
ット状態と発振していないリセット状態の2の状態のい
ずれか記憶することができる。そしてヒステリシスルー
プの立上り入射光量より大きな光量の入射光を与えるこ
とによってセットすることができ、またバイアス光量を
ヒステリシスループの立下り光量より小きく低減するこ
とによってリセットすることができる。
A bistable semiconductor laser has a saturable absorption region in a part of the resonator of the semiconductor laser, and exhibits a hysteresis loop in the characteristics of the amount of incident light versus the amount of output light by appropriately selecting the injection current. By applying bias light with an intermediate light intensity between the rising incident light intensity and the falling incident light intensity of the hysteresis loop, it is possible to store one of two states: a set state in which oscillation occurs and a reset state in which oscillation does not occur. It can be set by applying a larger amount of incident light than the rising incident light amount of the hysteresis loop, and can be reset by reducing the bias light amount to be smaller than the falling light amount of the hysteresis loop.

第4図では双安定半導体レーザ45は電流供給回路46
から一定の電流iがi主入されセット入射光41および
リセット入射光42が光インバータ43によって論理反
転したバイアス光44とが入射されることによってセッ
トまたはリセットされセット状態では出射光47を出射
する。
In FIG. 4, the bistable semiconductor laser 45 is connected to the current supply circuit 46.
A constant current i is input as main input from i, and set or reset is made by inputting set incident light 41 and reset incident light 42 with bias light 44 whose logic is inverted by an optical inverter 43, and outputs output light 47 in the set state. .

セット入射光41、リセット入射光42のいずれも入射
されなければ光インバータ43は所定の光量のバイアス
光44を与え双安定単導体レーザ45は以前の状態を記
憶している。そして双安定半導体レーザ45がリセット
状態であったならセット入射光41を入力することによ
、ってセットする事ができる。一方双安定半導体レーザ
45がセット状態であったならばリセット入射光42を
入力すると光インバータ43は発振を停止しバイアス光
44の光量が減少し双安定半導体レーザ45をリセット
することができる。このように第4図の光情報記憶回路
は光ところが光インバータ43は現状では70°Ka&
の低温でしか動作しておらず乗温で使用することができ
ない。したがって従来の光情報′記憶′回路は極めて低
温に冷却しなければ使用することができなかった。
If neither the set incident light 41 nor the reset incident light 42 is incident, the optical inverter 43 applies a predetermined amount of bias light 44, and the bistable single conductor laser 45 memorizes the previous state. If the bistable semiconductor laser 45 is in the reset state, it can be set by inputting the set incident light 41. On the other hand, if the bistable semiconductor laser 45 is in the set state, when the reset incident light 42 is input, the optical inverter 43 stops oscillating, the amount of the bias light 44 decreases, and the bistable semiconductor laser 45 can be reset. In this way, the optical information storage circuit shown in FIG.
It only operates at low temperatures and cannot be used at elevated temperatures. Therefore, conventional optical information storage circuits must be cooled to extremely low temperatures before they can be used.

(発明の目的)    ′ 本i明の目的は光イン・・−夕を使用せずにすみ常温で
動作する゛光情報記憶回路を提供することにある。
(Object of the Invention) An object of the present invention is to provide an optical information storage circuit that does not require the use of an optical input and operates at room temperature.

k発明の構成)゛ 本発明によ五ば入射光量フセ零の条件下での注入電流対
出射光量特性において注入電流を零から増加させた場合
11で出射光量が急激の増加し注入型)此を■1から減
少させた場合I2で出射光量の急激に減少するヒステ”
IJシス特性を有しI、と■2の中間値I3の?主入電
流値における入射光量対出射光量特性において入射光量
を零から増加させた場合P1で出射光量が急激に増加す
るヒステリシス特性を有しPlより大きい光量あるいは
零の2値の毛ット光信号が入射される双安定半導体レー
ザと、2値のリセット光信号が入射される光電変換器と
、前記光電変換器の出力型゛気信号に応じて■2より小
さい電流値あるいは■3の2値の注入電流を前記双安定
半導体レーザに供給する電流供給回路から構成されるこ
とを特徴とする光情報記憶回路が得られる。
Structure of the Invention) According to the present invention, when the injection current is increased from zero in the characteristics of the injection current versus the output light amount under the condition that the incident light amount is zero, the output light amount increases sharply at 11 (injection type). ■When decreasing from 1, the amount of output light decreases rapidly at I2.
I has the IJ cis characteristic, and the intermediate value of I3 between ■2? In the incident light intensity vs. output light intensity characteristic at the main input current value, when the incident light intensity is increased from zero, the output light intensity rapidly increases at P1, which has a hysteresis characteristic, and the light signal has a binary value of light intensity greater than Pl or zero. a bistable semiconductor laser into which a binary reset optical signal is input; a photoelectric converter into which a binary reset optical signal is input; There is obtained an optical information storage circuit comprising a current supply circuit that supplies an injection current of 1 to the bistable semiconductor laser.

(講義の詳細な説明) 本発明は上述の構成をとることによって従来技術の問題
点を解決した。常温で十分安定に動作する光電変換器の
出力電気信号に応じて電流供給回路から双安定半導体レ
ーザへの注入電流を変化させることによって光インバー
タを使用することなく光信号でセット、リセットするこ
とができる光情報記憶回路が構成でさる。
(Detailed explanation of the lecture) The present invention solves the problems of the prior art by adopting the above-described configuration. By changing the current injected from the current supply circuit to the bistable semiconductor laser according to the output electrical signal of a photoelectric converter that operates sufficiently stably at room temperature, it is possible to set and reset using optical signals without using an optical inverter. The structure of the optical information storage circuit that can be used is different.

(実施例) 以下、本発明について図面を参照して詳細に説明する。(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

第1図によれば本発明の実施例はセット入射光12が入
射され出射光16を出射する双安定半導体レーザ15と
、リセット入射光11が入射される光電変換器13と、
光電変換器13の出力電気信号によって双安定半導体レ
ーザ15に注入する電流の値iを変化させる電流供給回
路14とを含む。双安定半導体レーザ15についての詳
細はエレクトロニクス(ElectronicsLet
ter)第17巻741ページや昭和57年度電子通信
学会光・電波部門全国大会講演上(分冊2)272#に
記載されている。
According to FIG. 1, the embodiment of the present invention includes a bistable semiconductor laser 15 that receives a set incident light 12 and emits an output light 16, a photoelectric converter 13 that receives a reset incident light 11,
A current supply circuit 14 that changes the value i of the current injected into the bistable semiconductor laser 15 according to the output electric signal of the photoelectric converter 13 is included. For more information about the bistable semiconductor laser 15, please see Electronics.
ter) Volume 17, page 741, and Lectures at the 1985 National Conference of the Optical and Radio Division of the Institute of Electronics and Communication Engineers (Part 2) #272.

第2図は第1図の実施例の双安定半導体レーザ15の特
性を説明するための図である。第2図(a)はセット入
射光12の光量Pinl=0の場合の注入電流iと出射
光16の光量P。utとの関係を示している。iを0か
ら増加させた場合、電流■1で急激にP。utがOから
増加しその後iを減少させると12で急激に0まで減少
するヒステリシス特性を示す。この時11と12の間の
値であるiBにiを設定すればP。utが0である動作
点AとPhである動作点Bの2つの状態をとることがで
きる。第2図(b)は1=ibの場合のセット入射光1
2の光量PinlとP。utとの関係を示しており、動
作点AおよびBは第2図(a)の動作点AおよびBとそ
れぞれ同じ状態である。最初に動作点Aであった場合P
inlをOから増加させるとPinl=PLでP。ut
を0からPhまで急激に増加し、その後Pinlを減少
させてもP。utはほぼphと一定でありPinl=0
まで減少させてもP。ut=Phの動作点Bを保つ。
FIG. 2 is a diagram for explaining the characteristics of the bistable semiconductor laser 15 of the embodiment shown in FIG. FIG. 2(a) shows the injection current i and the light amount P of the output light 16 when the light amount Pinl of the set incident light 12 is 0. It shows the relationship with ut. When i is increased from 0, the current suddenly becomes P at 1. When ut increases from 0 and then i decreases, it exhibits a hysteresis characteristic in which it rapidly decreases to 0 at 12. At this time, if i is set to iB, which is a value between 11 and 12, P is obtained. Two states can be taken: operating point A where ut is 0 and operating point B where Ph is. Figure 2(b) shows the set incident light 1 when 1=ib.
2 light quantity Pinl and P. ut, and operating points A and B are in the same state as operating points A and B in FIG. 2(a), respectively. If the operating point is A at first, then P
When inl is increased from O, Pinl=PL and P. ut
Even if P is rapidly increased from 0 to Ph and then P is decreased. ut is almost constant with ph and Pinl=0
Even if it is reduced to P. Maintain operating point B of ut=Ph.

第3図は第1図の実施例動作を説明するための図である
。記憶状態においてはセット入射光12の光量Pinl
およびリセット入射光11の光量Pin2の光量はいず
れもOであり主入電流i1.tiBである。よって双安
定半導体レーザ15は第2図における動作点Aまたは動
作点Bのいずれかの状態を保持しており出射光16の光
量P。utはそれぞれ0またはPhである。
FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG. 1. In the memorized state, the light intensity of the set incident light 12 is
The light intensity Pin2 of the reset incident light 11 is both O, and the main input current i1. It is tiB. Therefore, the bistable semiconductor laser 15 maintains either the operating point A or the operating point B in FIG. ut is 0 or Ph, respectively.

Pout=0であるリセット状態からP。ut=Phへ
変化させるセット動作はPinlを0から第2図(b)
に示したPsへ増加させることによって行う。Pin2
およびiは各々0、iBの状態のままである。第2図(
b)に示すようにPsはPlより大きく設定してありP
inlの0からPsへの変化により動作点はAからCへ
移動しPout”Phにな葛。その後Pinlが0へ減
少しても動作点はCからBへ移動しP。ut=Phのセ
ット状態が保持される。
P from the reset state where Pout=0. The setting operation to change ut=Ph is to change Pinl from 0 to Fig. 2(b).
This is done by increasing Ps to the value shown in . Pin2
and i remain at 0 and iB, respectively. Figure 2 (
As shown in b), Ps is set larger than Pl.
Due to the change in inl from 0 to Ps, the operating point moves from A to C and becomes Pout"Ph. After that, even if Pinl decreases to 0, the operating point moves from C to B and sets P.ut=Ph. State is preserved.

セット状態からP。ut”0へ変化させるリセット動作
はPin2を0からPrへ増加させることによって行う
。Pin2の変化は光電変換器13の出力電気信号の変
化を生じ、電流供給回路14は注入電流iをiBからi
rへ変化させる。第2図(a)に示すようにirは12
より小さく設定してあり動作点はBからDへ移動しP。
P from the set state. The reset operation to change ut"0 is performed by increasing Pin2 from 0 to Pr. The change in Pin2 causes a change in the output electrical signal of the photoelectric converter 13, and the current supply circuit 14 changes the injection current i from iB to i
change to r. As shown in Figure 2(a), ir is 12
It is set smaller and the operating point moves from B to D and P.

ut”0になる。その後Pin2が0へ減少し、iがi
、からiBへ戻っても動作点はDからAへ移動しP。u
t”Oのリセット状態が保持される。
ut” becomes 0. After that, Pin2 decreases to 0, and i becomes i
, even if it returns to iB, the operating point moves from D to A and P. u
The reset state of t''O is maintained.

(発明の効果) 以上に述べたように本発明に゛よれば光インバータを使
用せずに(すなわち常温で移動しえる)光信号でセット
、リセットすることができる光情報記憶回路が構成でき
る。
(Effects of the Invention) As described above, according to the present invention, it is possible to construct an optical information storage circuit that can be set and reset using an optical signal without using an optical inverter (that is, can be moved at room temperature).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す図、第2図は第1図にお
ける双安定半導体レーザ15の特性を説明するための図
、第3図は第1図の実施例の動作を説明するための図、
第4図は従来の光情報記憶回路の構成を示す図である。 図において13は光電変換器、工4.16は電流供給回
路、15.45は双安定半導体レーザ、43は光インバ
ータをそれぞれ表す。 第2図 Pou を 第3 口 徊    ロ
1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the characteristics of the bistable semiconductor laser 15 in FIG. 1, and FIG. 3 is a diagram for explaining the operation of the embodiment of FIG. 1. diagram for,
FIG. 4 is a diagram showing the configuration of a conventional optical information storage circuit. In the figure, 13 represents a photoelectric converter, 4.16 represents a current supply circuit, 15.45 represents a bistable semiconductor laser, and 43 represents an optical inverter. Figure 2 Pou and 3rd Mouth Lo

Claims (1)

【特許請求の範囲】[Claims] 入射光量が零の条件下での注入電流対出射光量特性にお
いて注入電流を零から増加させた場合I_1で出射光量
が急激に増加し注入電流をI_1から減少させた場合I
_2で出射光量が急激に減少するヒステリシス特性を有
しI_1とI_2の中間値I_3の注入電流値における
入射光量対出射光量特性において入射光量を零から増加
させた場合P_1で出射光量が急激に増加するヒステリ
シス特性を有しP_1より大きい光量あるいは零の2値
のセット光信号が入射される双安定半導体レーザと、2
値のリセット光信号が入射される光電変換器と、前記光
電変換器の出力電気信号に応じてI_2より小さい電流
値あるいはI_3の2値の注入電流を前記双安定半導体
レーザに供給する電流供給回路から構成されることを特
徴とする光情報記憶回路。
In the injection current vs. output light amount characteristics under the condition where the amount of incident light is zero, when the injection current is increased from zero, the output light amount increases rapidly at I_1, and when the injection current is decreased from I_1, I
It has a hysteresis characteristic in which the amount of emitted light rapidly decreases at _2, and when the amount of incident light is increased from zero in the incident light amount vs. output light amount characteristic at the injection current value I_3, which is the intermediate value between I_1 and I_2, the amount of output light increases rapidly at P_1. a bistable semiconductor laser, which has a hysteresis characteristic of
a photoelectric converter into which a value reset optical signal is input; and a current supply circuit that supplies the bistable semiconductor laser with a binary injection current of a current value smaller than I_2 or I_3 according to the output electric signal of the photoelectric converter. An optical information storage circuit comprising:
JP59277290A 1984-12-26 1984-12-26 Optical information memory circuit Pending JPS61153900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59277290A JPS61153900A (en) 1984-12-26 1984-12-26 Optical information memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59277290A JPS61153900A (en) 1984-12-26 1984-12-26 Optical information memory circuit

Publications (1)

Publication Number Publication Date
JPS61153900A true JPS61153900A (en) 1986-07-12

Family

ID=17581473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59277290A Pending JPS61153900A (en) 1984-12-26 1984-12-26 Optical information memory circuit

Country Status (1)

Country Link
JP (1) JPS61153900A (en)

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