JPS60110170A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the performance and the integration of a semiconductor device by forming a low density region only in one of the regions to become source and drain regions, thereby preventing the deterioration of the characteristics of an element. CONSTITUTION:After with a control gate electrode 40 laminated on a substrate 31 as a mask As ions are implanted vertically from above. Then, a CVD oxide film 41 is obliquely accumulated on the overall surface, etched obliquely, and the remaining photoresist 41' is formed on the side wall shaded of the electrode 40. Then, with the electrode 40 and the remaining photoresist 41' as masks As ions are implanted in high dosage, the remaining photoresist 41' is then removed, the impurity is activated by a heat treatment, an n type region 42 made of a low density diffused layer 42a and a high density diffused layer 42b adjacent to the layer 42a is formed on one side of the surface of the substrate 31, and an n<+> type region 43 made of high density diffused layer is formed on the other side. Finally, electrodes 45, 46 are formed, and an EPROM cell is manufactured.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an MO8 conductor device in which a low concentration region is formed in the vicinity of a channel region only in either a source region or a drain region. It pertains to the manufacturing method.

[Technical background of the invention and its problems]

In recent years, there has been remarkable progress in microfabrication technology for MO8 semiconductor devices, and in particular, from the viewpoint of improving switching speed, channel lengths are being shortened and higher integration is being promoted.

However, as the channel length becomes shorter, electric field concentration occurs in the channel region even when the voltage applied between the source and drain is low, causing various problems in terms of device characteristics.

For example, read-only semiconductor memory (EPROM, Erasable Program
Conventionally, a memory cell having a structure as shown in FIG. That is, 1 in the figure is, for example, a P-type silicon substrate, and a field oxide film 2 is formed on the surface of this substrate 1. On the surface of the element region of the substrate 1 surrounded by the field oxide film 2, n+ type source and drain regions 3 and 4 are formed electrically isolated from each other. Furthermore, a floating gate electrode 6 is formed on the channel region between the source and drain regions 3.4 via a first dirt oxide film 5, and a second dirt oxide film 7 is further formed on this floating dirt electrode 6. A control gate electrode 8 is formed therebetween. Furthermore, an interlayer insulating film 9 is deposited on the entire surface, and on this interlayer insulating film 9, a source electrode 10 is connected to the source region 3 through a contact hole, and a drain electrode is formed to connect to the drain region 4, respectively. 11 is formed.

In a memory cell having such a configuration, information is written by applying a high voltage of, for example, +20V or more to the drain electrode 11 and the control gate electrode 8, causing an avalanche phenomenon in the vicinity of the strain region 4 by electrons flowing through the channel region. This is done by injecting and dragging electrons into the floating gate electrode 6 through the first gate oxide film 5. To read information, a voltage of about +5V, for example, is applied to the drain electrode 1 and the control gate electrode 8, and the transistor is turned on or off as the threshold voltage changes depending on whether writing is being performed or not. to decide.

However, when the channel length becomes short, electric field concentration occurs in the channel region even when a relatively low drain voltage (about +5 V) is applied during readout, and electrons are sufficiently accelerated.
It becomes possible to cause an avalanche phenomenon. For this reason,
A similar situation (erroneous writing of information) occurs when electrons are dragged to the floating dart electrode 6 of a memory cell to which information is originally not written and information is written.

Further, a conventional MOS (Rannosk) has a structure as shown in FIG. That is, 21 in the figure is, for example, a P-type silicon substrate, and a field oxide film 22 is formed on the surface of this substrate 21. This field oxide film 2
On the surface of the element region of the substrate 2 surrounded by
4 is formed. In addition, the source and drain regions 23
．． A dirt electrode 26 is formed on the channel region between the holes 24 with a dirt oxide film 25 interposed therebetween. Further, an interlayer insulating film 27 is deposited on the entire surface, and on this interlayer insulating film 27, a source electrode 28 is connected to the source region 23 mentioned in 4iI through a contact hole, and a drain electrode is connected to the drain region 24, respectively. 29 is formed.

Even in a conventional MOS transistor having such a structure, when the channel length becomes short, an avalanche phenomenon tends to occur due to electric field concentration in the channel region near the drain region 24 even when a relatively low drain voltage is applied. As a result, electrons are trapped in the keto oxidation B#, 25, causing a problem in terms of device characteristics such that the threshold voltage fluctuates.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and by providing a low concentration region only in one of the regions that will become the source and drain regions, electric field concentration in the channel region due to shortening of the channel length can be reduced. It is an object of the present invention to provide a method for manufacturing a high-performance, highly integrated semiconductor device that can reduce the stress and prevent deterioration of device characteristics.

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention includes forming at least one layer of dirt electrodes on a first conductivity type semiconductor substrate via a gate insulating film, depositing a film on the entire surface, and anisotropic etching from the printing direction. A film was left on one side wall of the Sigut electrode by etching with a silica film, and a high-dose ion implantation of the second equi% type impurity was performed with the film remaining, and a second conductor was implanted in the state where the film was not present. After performing low-dose ion implantation of type impurities, heat treatment is performed to manufacture a semiconductor device in which a low concentration diffusion layer is provided in the vicinity of the channel region only in one of the regions that will become the thin source region and the drain region.

According to this method, it is not necessary to add a complicated process such as mask alignment to leave a film on one side wall of the gate electrode, so that one of the regions that will become the source and drain regions can be coated with a simple process. Only in this way can a semiconductor device in which a low concentration diffusion layer is provided near the channel region be manufactured.

In such a semiconductor device, electric field concentration in the channel region can be effectively prevented, so for example, EPRO
It is possible to prevent deterioration of device characteristics such as erroneous writing in M cells and fluctuations in threshold voltage in MOS transistors.

[Embodiments of the invention]

Example 1 An example in which the present invention is applied to manufacturing an EPROM cell will be described below with reference to FIGS. 3(-) to (-).

First, a Schifffield oxide film 32 is formed on the surface of a P-type silicon substrate 31 by selective oxidation. Next, a first layer is formed on the surface of the element region of the substrate 3 surrounded by the field oxide film 32.
After forming a thermal oxide film 33, a first polycrystalline silicon film 34, which will become a floating dirt electrode, is deposited on the entire surface.
Part of it is selectively etched. Next, thermal oxidation is performed to form a second thermal oxide film 35 on the surface of the first polycrystalline silicon film 34, and then a second polycrystalline silicon film 36, which will become a control gate electrode, is deposited on the entire surface (the first 3
Figure(,)Illustrated).

Next, the second polycrystalline silicon film 36, the second thermal oxide film 35, the first polycrystalline silicon film 34, and the first thermal oxide film 33 are sequentially etched and turned to form a surface on the substrate 3. Then, a floating gate electrode 38 is formed via a first gate oxide *sy, and a control gate electrode 40 is further formed on the floating dirt electrode 38 via a second dirt oxide film 39. Phosphorus or arsenic is ion-implanted from vertically above at a low dose of about 5×10 cTn using a control dart electrode layered on the substrate 31 as a mask (as shown in FIG. 3(b)).

Next, a 4-layer CVD oxide film with a thickness of 2000× is applied to the entire surface (
After depositing the CVD oxide film 4 (indicated by the broken line in the figure), this CVD oxide film 4 is diagonally color-etched using anisotropic etching, and the remaining CVD oxide film 41' is formed on one side wall that is in the shadow of the control gate electrode 40, etc. (Illustrated in the same figure (c))
. Next, arsenic is ion-implanted at a high dose of about 3 x 10 cm to form sources and drains using the contact electrodes 40 and the remaining CVD oxide film 4 stacked on the substrate 31 as masks.
Figure (d) shown).

Next, after removing the remaining CVD oxide film 41', the cine film is activated by heat treatment to form a low concentration (n-type) diffusion layer near the channel region on the surface of the substrate 31 on one side of the floating gate electrode 38, etc. 42a (impurity concentration approximately 10”c
m-5) and the adjacent high concentration (n+ type) diffusion layer 42
b (impurity level 1019 to 10 crn) is connected to the floating gate ljL#A'3.
A high concentration (n+ type) diffusion layer (
n area 4 consisting of an impurity concentration of 1019 to 10
3 respectively. Next, an interlayer insulating film 4 is applied to the entire surface.
After depositing 4, a contact hole is formed. Subsequently, after coating the entire surface with an A film, electrodes 45 and 46 are formed by cutting, and an EPROM cell is manufactured (as shown in FIG. 4(e)).

In the apuoM cell shown in FIG. 3(a), when writing information, one n-type region 43 is used as a drain region, and the other n-type region 42 is used as a source region. That is, the electrode 45 is a drain electrode, and the electrode 46 is a drain electrode.
is used as a source electrode, and a high voltage is applied to the (drain) electrode 45 and the control dirt electrode 40. In this case, the potential in the channel region is equal to or very close to the potential in the source region, that is, the n-type region 42. Therefore, the electric field between the source and the drain becomes intensively strong in the drain region, that is, the channel region near the layered region 43, and in this region, hot carriers (electron, hole pairs) are generated due to the avalanche phenomenon and the floating dart electrode 38 Electrons are injected into the memory, and information is written.

On the other hand, when reading information, one n+ type region 43 is used as a source region and the other n type region 42 is used as a drain region, contrary to when writing information. That is, the electrode 45 is used as a source electrode and the electrode 46 is used as a drain electrode, and +5V, for example, is applied between the source and drain, and +5V, for example, is applied to the control gate electrode 40 to turn on the transistor as the threshold voltage vTH changes. The off information is read out.

At this time, since a low concentration (n-type) diffusion layer 42a is provided in the n-type region 42 which becomes the drain region near the channel region, this region takes charge of part of the voltage applied between the source and the drain. be able to. Therefore, the electric field concentrated in the channel region near the drain region can be significantly weakened.

Referring to FIGS. 4 and 5(a) and 5(b), the electric field in the channel region near the drain region during reading of the above embodiment and the conventional EFROM cell will be compared in more detail.

FIG. 4 is an explanatory diagram showing a depletion layer generated near the drain region during information reading. The shaded region in the figure is the depletion layer 47 generated in the EFROM cell of the above embodiment.
It extends to both sides of the interface between the low concentration (n-type) diffusion layer 42a and the channel region. On this occasion,! , the distribution state of the rise is as shown in FIG. 5 (,).

On the other hand, when the low concentration (n-type) diffusion layer 42a is not provided (corresponding to the conventional EFROM cell shown in FIG. 1)
, the depletion layer is generated only in the region shown by the dashed line in FIG. 4, that is, on the channel region side. This is because the concentration of the high concentration (n+ type) diffusion layer 42b is high and ol has the same properties as metal. At this time, the distribution state of the electric field becomes as shown in FIG. 5(b).

As shown in Figure 5 (a) and (b), if the potential difference between the source and drain is the same, the peak value of the electric field in Figure 5 (,) has a wider distribution than that in Figure 5 (b). It is obvious that it will be lower. That is, by providing the low concentration (n-type) diffusion layer 42a as a part of the drain region, the electric field concentrated in the channel region near the drain region can be significantly weakened. Therefore, a/, e in this area
The generation of hot carriers due to the Lanchet phenomenon is suppressed,
Erroneous writing of information can be prevented.Furthermore, since there is no risk of erroneous writing occurring when reading information, the channel length can be made sufficiently short, thereby increasing the writing efficiency when writing information. Therefore, the values of write voltages such as the drain voltage and control gate voltage that should be applied when writing information can be reduced compared to conventional methods. For example, the voltages that are applied when writing information and the voltages that are applied when reading information are both about +5V. It can be done.

As explained above, in the method of the present invention, after the CVD oxide film 41 is deposited in the step shown in FIG. 3(e), the control gate electrode 40 and the Taking advantage of the fact that the remaining CVD oxide film 41' can be formed on one side wall of the floating gate electrode 38, etc., low-dose ion implantation using the control gate electrode 40, etc. as a mask in the process of FIG. ) Since the electrode 40, etc. and the remaining CVD oxide film 41' are used as a mask, the control method in the process of ) is performed by dose ion implantation. It is possible to manufacture high-performance, high-density EPROM cells.

Embodiment 2 Hereinafter, an embodiment in which the present invention is applied to the manufacture of an n-channel MO8) transistor will be described with reference to FIGS. 6(a) to 6(d).

First, a field oxide film 52 is formed on the surface of a P-type silicon substrate 51 by selective oxidation, and then a dirt oxide film 53 is formed on the element region of the substrate 5 surrounded by the field oxide film 52 using a conventional method. Electrodes 54 are formed. Next, using the pole 54 as a mask, ions of arsenic, for example, are implanted at a low dose of about 5.times.10@12 cm@-2 (as shown in FIG. 6(a)).

Next, after depositing a CVD oxide film 55 (indicated by a broken line in the figure) with a thickness of 2000X on the entire surface, this CVD oxide film 55 was etched diagonally using anisotropic etching, so that it was in the shadow of the dirt electrode 54. Residual CVD oxide film 55 on one side wall
(Illustrated in Figure (b)). Next, using the dirt electrodes 5, 4 and the remaining CVD oxide film 55 as a mask, arsenic was applied at 3 x 1015 cm to form sources and drains.
Ion implantation is performed at a high dose of about 2 (as shown in FIG. 2(c)).

Next, after removing the remaining CVD oxide film 55', the cine film is activated by heat treatment, and a low concentration (n-type) film is formed on the surface of the substrate 51 on one side of the dart' electrode 54 near the channel region.
An n-type drain region 56 consisting of a diffusion layer 56a (impurity fatigue level of about 10"cm-') and an adjacent high concentration (n"ff1) diffusion layer 56b (impurity concentration 1019 to 1020 crn-2) is connected to a dirt electrode. Substrate 5 on the other side of 54
A layered source region 57 consisting of a high concentration (n+8!) diffusion layer is formed on each surface. Subsequently, an interlayer insulating film 58 is deposited on the entire surface, and then a contact hole is formed.

Subsequently, after depositing an A/film on the entire surface, a/leaning is performed to form a source electrode 59 and a drain electrode 60, thereby manufacturing an n-channel MO3) transistor (as shown in FIG. 4(d)).

In the MOS transistor shown in FIG. 6(d), in the same manner as described with reference to FIGS. Since the low concentration (n-type) diffusion layer 56m is provided, it is possible to prevent electric field concentration in the channel region near the drain region 56, and to prevent deterioration of device characteristics such as fluctuations in threshold voltage of micro MO8) transistors. It can be prevented.

In addition, a so-called LDD (Lightly Doped Diode) is used in which both the source and drain regions are composed of a low concentration diffusion layer near the channel region and an image concentration diffusion layer adjacent to this.
Drain and 5source) structure MOS
) In the transistor, the low concentration diffusion layer on the source region side causes a decrease in mutual conductance (Um), but in the MOS transistor shown in FIG. 6(d), the source region 67 has a low concentration diffusion layer near the channel region. Since no is formed, a decrease in mutual conductance (g) can be avoided.

As explained above, the method of the present invention achieves high performance and high integration without adding complicated steps such as mask alignment in photolithography. +408) It is possible to manufacture a run disk.0 In the above-mentioned Example 1, low-dose ion implantation was performed as shown in Fig. 3 t.
Although it may be annoying after patterning the control gate electrode 40 and the like in the bJ process, low-dose ion implantation may be performed after removing the remaining CVD oxide film 41'. 1
However, it is not necessary to remove the remaining CVD oxide film 41, but in this case, low-dose ion implantation is of course performed temporarily for patterning the control gate electrode 40 and the like.

1.delta.'', the low-dose ion implantation in the second embodiment may be performed after the remaining CVD oxide film 55 is removed. Further, the remaining CVD y-oxide film 55 does not need to be removed.

In addition, in Examples 1 and 2 above, a CVD 5i1 film was used as a coating to remain on one side wall of the beam/meter electrode, etc., but a coating that has selective etching properties with respect to mineral cast@electrodes, etc. That's fine, PSG!-t BS
It may be an insulating film such as G gland or a metal such as AJ. However, if these coatings remain, they may deteriorate the cord characteristics, so it is desirable to remove them eventually.

Furthermore, although the above description has been made regarding n-channel EPROM cells and MOS transistors, similar effects can be obtained with p-channel ones.

〔Effect of the invention〕

As described in detail above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a high performance and highly integrated semiconductor device without deterioration of device characteristics due to shortening of channel length.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional EPROM cell, Fig. 2 is a cross-sectional view of a conventional MOS () run master, and Fig. 3 (, ) to (,
) is a sectional view showing the parent end method of the EPROM cell in Example 1 of the present invention, FIG. 4 is an explanatory diagram of a depletion layer generated during reading of the EPROM cell manufactured in Example 1 of the present invention, and FIG. (a) and (b) are electric field distribution diagrams of Example 1 of the present invention and a conventional EPROM cell, respectively;
FIG. 6(,) to (d) are MO in Example 2 of the present invention.
S) It is a sectional view showing a method of manufacturing a transistor. 31.51...P-type silicon substrate 1. ? 2, 52
...field oxide film, 33...first thermal oxide film,
34... First polycrystalline silicon film, 35... Second thermal oxide film, 36... Second polycrystalline silicon film, 37.
...First dirt oxide film, 38... Floating gate electrode, 39... Second gate oxide film, 40...
Control gate electrode, 4th...CVD oxide film,
4...Residual CVD oxide film, 42a...Low concentration (
n-type) diffusion layer, 42b...high concentration (n-type) diffusion layer, 4
2...n-type region, 43...n-type region, 44...interlayer insulating film, 45.46...electrode, 47...depletion layer,
53... Gate oxide film, 54... Dirt electrode, 55
...CVD oxide film, 55...Residual CVD oxide film, 5
6a...Low concentration (n type) diffusion layer, 56b...High concentration (NL) diffusion layer, 56...Drain region, 57...
Source region, 58... Interlayer insulating film, 59... Source electrode, 60... Drain electrode.

Claims (3)

[Claims] (1) Forming at least one layer of dirt electrodes on a semiconductor substrate of the first conductivity type through a thin insulating film, and after depositing a film on the entire surface, the film is anisotropically etched from an oblique direction. etching to leave a film on one side wall of the gate electrode; a step of ion-implanting a second conductivity type impurity at a high dose using the dirt electrode and the remaining film as a mask; and shaping the gate electrode. hZ L
After that, or after removing the remaining particles, a second conductive impurity silicon ion is implanted at a low dose using the gate electrode as a mask, and the cine material is activated by heat treatment, and one side of the dirt electrode is implanted. A second conductor 1! is formed on the surface of the substrate, consisting of a low concentration diffusion layer near the channel region and a high concentration diffusion layer v4 in contact with the low concentration diffusion layer. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a mold region; and forming a second electrical region made of a high concentration diffusion layer on the surface of the substrate on the other side of the dirt electrode. (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that a dirt electrode is formed on a semiconductor substrate via a dirt insulating film to manufacture a MOS transistor. (3) The first film is placed on the semiconductor substrate via the date insulating film described in 1 above.
A dirt electrode is formed on the first gate electrode, and a second dirt electrode is formed on the first gate electrode via a second dirt insulating film to manufacture a FROM cell. A method for manufacturing a semiconductor device according to scope 1.