JPS60109234A - Method for etching process of two-layer film - Google Patents
Method for etching process of two-layer filmInfo
- Publication number
- JPS60109234A JPS60109234A JP21599083A JP21599083A JPS60109234A JP S60109234 A JPS60109234 A JP S60109234A JP 21599083 A JP21599083 A JP 21599083A JP 21599083 A JP21599083 A JP 21599083A JP S60109234 A JPS60109234 A JP S60109234A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- titanium silicide
- polycrystalline silicon
- oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体集積回路の低抵抗の電極として用いら
れる、チタンシリサイド膜と多結晶シリコン膜とからな
る二層膜のエツチング加工法に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for etching a two-layer film consisting of a titanium silicide film and a polycrystalline silicon film, which is used as a low-resistance electrode in a semiconductor integrated circuit. be.
従来、平板型の平行電極間に高周波電界を印加し、反応
性ガスを導入してグロー放電させエツチングする方法（
以下ＲＩＥ （Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉ
ｎｇ）法という）を用いた１チタンシリサイド膜と多結
晶シリコン膜とからなる二層膜のエツチング加工におい
ては、塩素を中心とした反応性ガス例えばＣｊ１２とＣ
Ｆ、との混合ガスが用いられていた（例えば、 Ｋ、Ｌ
、Ｗａｎｇ 、Ｔ、Ｏ，Ｈｏｌｌｏｗａｙ 、几、Ｆ、
Ｐｉｎｉｚｚｏｔｔｏ。Conventionally, a high-frequency electric field is applied between flat parallel electrodes, and a reactive gas is introduced to cause glow discharge and etching (
Below is RIE (Reactive Ion Etchi)
In the etching process of a two-layer film consisting of a titanium silicide film and a polycrystalline silicon film using the ng) method, a reactive gas mainly containing chlorine, such as Cj12 and Cj12, is used.
F, mixed gases were used (for example, K, L
,Wang, T., O., Holloway, 几,F.
Pinizzotto.
Ｚ、 Ｐ、 ５ｏｂｃｚａｋ、 Ｗ、 Ｒ，Ｈｕｎｔｅ
ｒ ａｎｄ Ａ、 Ｆ、 Ｔａ５ｃｈ 、 Ｊｒ、 。Z, P, 5obczak, W, R, Hunte
r and A, F, Ta5ch, Jr.
ｉｎ １９８１ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｅｊｌ
ｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ Ｍ、ｅｅｔｉ、ｎｇ。in 1981 International Ejl
ectron Devices M, eti, ng.
Ｄｉｇ、 Ｔｅｃｈ−Ｐａｐｅｒｓ （Ｗａｓｈｉｎｇ
ｔｏｎ 、 Ｄ、 ０． ）、 ｐｐ５ｓ −６１）。Dig, Tech-Papers (Washing
ton, D, 0. ), pp5s-61).
すなわち、次の方法により第１図に示すような形状を得
ていた。半導体基板１上に酸化シリコン膜２を形成し、
続けて多結晶シリコン膜３を堆積し、その上にチタンシ
リサイド膜４を堆積し、レジストバタン５を形成した後
、塩素を中心とした反応性ガス例えばＣ７Ｉ２とＯＦ４
との混合ガスを用いたｌ’ＬＩＥ法により、テクノシリ
サイド膜４と多結晶シリコン膜３のエツチングを行った
。しかし、この従来法では、チタンシリサイド膜４のエ
ツチング速度が多結晶シリコン膜３のそれよりも小さく
、かつエツチングの異方性が悪いため、第１図に示され
るように、多結晶シリコン膜３がアンダカットを呈しす
なわちチタンシリサイド膜４に比べて多くエツチングさ
れて図示のような段差が形成されてしまう。したがって
、チタンシリサイド膜４と多結晶シリコン膜３とからな
る二層膜のバタンの端の該段差部で、前記二層膜上に堆
積する層間絶縁膜の被覆が一部で薄くなったりして不良
となり易く、上層配線と該二層膜との帰結あるいは上層
配線の断線を生じ、半導体集積回路の製造歩留りの低下
あるいは信頼性の低下を引き起す欠点があった。That is, the shape shown in FIG. 1 was obtained by the following method. forming a silicon oxide film 2 on a semiconductor substrate 1;
Subsequently, a polycrystalline silicon film 3 is deposited, a titanium silicide film 4 is deposited on top of the polycrystalline silicon film 3, and a resist batten 5 is formed.
The techno-silicide film 4 and the polycrystalline silicon film 3 were etched by the l'LIE method using a mixed gas with However, in this conventional method, the etching rate of the titanium silicide film 4 is lower than that of the polycrystalline silicon film 3, and the etching anisotropy is poor, so as shown in FIG. The film exhibits an undercut, that is, is etched more than the titanium silicide film 4, and a step as shown in the figure is formed. Therefore, the coating of the interlayer insulating film deposited on the two-layer film becomes partially thin at the stepped portion at the edge of the two-layer film consisting of the titanium silicide film 4 and the polycrystalline silicon film 3. This has the disadvantage that it tends to be defective, resulting in a connection between the upper layer wiring and the two-layer film, or a disconnection of the upper layer wiring, resulting in a reduction in manufacturing yield or reliability of semiconductor integrated circuits.
〔発明の目的〕
本発明は、これらの欠点を改善するため鋭意研究を行い
、極めて簡単な方法により、多結晶シリコン膜をアンダ
カットを伴うことなくエツチング加工する方法を提供す
ることを目的とする。[Object of the Invention] The purpose of the present invention is to provide a method for etching a polycrystalline silicon film without undercutting, using an extremely simple method, by conducting intensive research to improve these drawbacks. .
すなわち、本発明は、ＲＩＦｔ法によるチタンシリサイ
ド膜と多結晶シリコン膜とからなる二層膜のエツチング
加工において、０〜刀モル％の酸素を含有する０Ｆ２Ｃ
ｊ１２中にてエツチングを行うことを特徴とするもので
ある。That is, in the present invention, in the etching process of a two-layer film consisting of a titanium silicide film and a polycrystalline silicon film by the RIFt method, 0F2C containing 0 to 2 mol% of oxygen is used.
This is characterized in that etching is performed during step 12.
次に、本発明の実施例について説明する。本発明により
加工したチタンシリサイド膜４と多結晶シリコン膜３と
からなる二層膜の加工形状を第２図に示す。反応性ガ１
として、０−３０モル％の酸素を含有するｃＦ２０１２
を用いた本発明によるＲＩＥ法では、チタンシリサイド
膜のエツチング速度が多結晶シリコン膜のエツチング速
度より大きく、がつ極めて優れた異方性を有するイオン
性エツチングが可能なため、多結晶シリコン膜３がアン
ダヵットを呈することなく加工できている。なお、本試
料の多結晶シリコン膜３ ＋’ｚ ＯＶＤ法により、ま
たチタンシリサイド膜４は、スパッタリング法で堆積し
た。また、試料は、エツチング前に８ｏｏ℃以上でアニ
ールを施しである。レジストには、ポジ型ホトレジスト
を用い、ポストベークは１２０℃〜１８０℃で行った。Next, examples of the present invention will be described. FIG. 2 shows the processed shape of a two-layer film made of titanium silicide film 4 and polycrystalline silicon film 3 processed according to the present invention. reactive moth 1
cF2012 containing 0-30 mol% oxygen as
In the RIE method according to the present invention using a titanium silicide film, the etching rate of the titanium silicide film is higher than that of the polycrystalline silicon film, and since ionic etching with extremely excellent anisotropy is possible, the polycrystalline silicon film 3 can be processed without any undercut. Note that the polycrystalline silicon film 3 of this sample was deposited by +'z OVD method, and the titanium silicide film 4 was deposited by sputtering method. In addition, the sample was annealed at 80° C. or higher before etching. A positive photoresist was used as the resist, and post-baking was performed at 120°C to 180°C.
ＲＩＥ工程における、ガス圧はｌ７−Ｐ ａ ＋ ガス
流量は５０ ｓｅｃｍ テある。In the RIE process, the gas pressure is 17-P a + gas flow rate is 50 sec.
また、本発明において１酸素の混入量を０〜３０モル％
に限定したが、その理由は、第３図に示すように、０〜
３０モル％内では、チタンシリサイド膜のエツチング速
度を、多結晶シリコン膜およびレジストのエツチング速
度に比較して、適度に大きくできるためである。これに
より、多結晶シリコン膜がアンダカッートを呈するのを
十分防ぐことが可能になる。酸素濃度は、望ましくは１
０〜２０モル％にすることＫより、最大のエツチング速
度比を得ることができる。In addition, in the present invention, the amount of 1 oxygen mixed is 0 to 30 mol%.
The reason for this is as shown in Figure 3, from 0 to
This is because within 30 mol %, the etching rate of the titanium silicide film can be appropriately increased compared to the etching rates of the polycrystalline silicon film and resist. This makes it possible to sufficiently prevent the polycrystalline silicon film from exhibiting undercuts. The oxygen concentration is preferably 1
By setting K to 0 to 20 mol %, the maximum etching rate ratio can be obtained.
以上詳述した如く、本発明方法によれば＼チタンシリサ
イド膜と多結晶シリコン膜とからなる二層膜を多結晶シ
リコン膜がアンダカットを呈することなく加工できるた
め、該二層膜上に形成する層間絶縁膜の二層膜バタン端
段差部での被覆を損なうことがなく、上層配線と該二層
膜との短絡や該上層配線の断線を防止することができ１
半導体集積回路の製造歩留りが著しく向上する効果があ
−る０As described in detail above, according to the method of the present invention, a two-layer film consisting of a titanium silicide film and a polycrystalline silicon film can be processed without the polycrystalline silicon film exhibiting undercuts. It is possible to prevent a short circuit between the upper layer wiring and the two layer film and a disconnection of the upper layer wiring without damaging the covering of the interlayer insulating film at the step part at the end of the double layer film.
It has the effect of significantly improving the manufacturing yield of semiconductor integrated circuits0
第１図は、従来方法により加工されたチタンシリサイド
膜と多結晶シリコン膜とからなる二層膜の断面形状を示
す図、第２図は、本発１明方法により加工されたチタン
シリサイド膜と多結晶シリコン膜とからなる二層膜の断
面形状を示す図、第３図は、チタンシリサイド膜、牌結
晶シリコン膜およびレジストのエツチング速度と酸素濃
度との関係を示す図である。
１・・・半導体基板、２・・・酸化シリコン膜、３・・
・多結晶シリコン膜、４・・・チタンシリサイド膜、５
・・・レジスト
特許出願人 日本電信電話公社
代理人弁理士 中 村 純之助FIG. 1 shows the cross-sectional shape of a two-layer film made of a titanium silicide film and a polycrystalline silicon film processed by the conventional method, and FIG. 2 shows the cross-sectional shape of a titanium silicide film processed by the method of the present invention. FIG. 3 is a diagram showing the cross-sectional shape of a two-layer film composed of a polycrystalline silicon film, and a diagram showing the relationship between the etching rate and oxygen concentration of the titanium silicide film, the tile crystal silicon film, and the resist. 1... Semiconductor substrate, 2... Silicon oxide film, 3...
・Polycrystalline silicon film, 4...Titanium silicide film, 5
...Resist patent applicant Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Public Corporation
Claims (1)
ガスを導入してグロー放電させ、多結晶シリコン膜上に
チタンシリサイド膜を形成した二層膜をエツチングする
加工方法におし）て、前記反応性ガスとして、０〜３０
モル％の酸素を含有する０ＦＯＩガス中にてエツチング
を行うことを特徴と２ するチタンシリサイド膜と多結晶シリコン膜と力）らな
る二層膜のエツチング加工法。[Claims] Processing in which a high-frequency electric field is applied between electrodes arranged opposite each other, a reactive gas is introduced to cause a glow discharge, and a two-layer film in which a titanium silicide film is formed on a polycrystalline silicon film is etched. method), the reactive gas is 0 to 30
2. A method for etching a two-layer film consisting of a titanium silicide film and a polycrystalline silicon film, characterized in that the etching is performed in a 0FOI gas containing mol% of oxygen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21599083A JPS60109234A (en) | 1983-11-18 | 1983-11-18 | Method for etching process of two-layer film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21599083A JPS60109234A (en) | 1983-11-18 | 1983-11-18 | Method for etching process of two-layer film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60109234A true JPS60109234A (en) | 1985-06-14 |
Family
ID=16681574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21599083A Pending JPS60109234A (en) | 1983-11-18 | 1983-11-18 | Method for etching process of two-layer film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60109234A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4726879A (en) * | 1986-09-08 | 1988-02-23 | International Business Machines Corporation | RIE process for etching silicon isolation trenches and polycides with vertical surfaces |
-
1983
- 1983-11-18 JP JP21599083A patent/JPS60109234A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4726879A (en) * | 1986-09-08 | 1988-02-23 | International Business Machines Corporation | RIE process for etching silicon isolation trenches and polycides with vertical surfaces |
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