JPS60109105A - Method of producing semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to
The present invention relates to a method of manufacturing a semiconductor device in which electrode wiring made of um-Tin-Owide (hereinafter referred to as 1.T and O) is etched.

[Prior Art] This type of transparent M I+@ consisting of I, T, and O is used as an electrode substrate for liquid crystal display devices, electrochromic display devices, and thin film transistor arrays (hereinafter referred to as TFT arrays) for matrix type display devices. ), are widely used as transparent electrodes or wiring materials for various electronic devices such as image sensors and solar cells.

For example, as shown in FIGS. 1 and 2, 1. T, O electrode wiring (1) is formed. The method for forming the I, T, O electrode wiring (1) includes a method in which indium (In) containing about 5% of tin (Sn) is formed by a vapor deposition method, and then oxidized under pressure in an oxygen atmosphere; The sputtering method and the electron beam evaporation method in a low pressure oxygen atmosphere are used. After forming an I, T, O film with a thickness of about 100 OA by any of the above methods, a resist pattern of a predetermined shape, for example, 50 gm width is formed by photoetching,
With a composition of HCfl:H2O:FeCf1 = 4:4:l,
By etching with a hydrochloric acid solution at a liquid temperature of 40°C,
A T, O electrode arrangement M (1) is formed.

However, according to the method described in -1-, since a hydrochloric acid-based solution is used to etch the I, T, and O electrode wirings (1), side etching portions (l) of about 10 pm are left on both sides.
a) was formed, and the wiring pattern spacing was set to 30 μm.
It was impossible to do less.

As shown in Figures 3 and 4, in various functional devices including multi-layer wiring, quartz glass (plate (2)
After forming an active element (not shown) on the top, a TFT array and an alloy electrode wiring (3) made of A pattern or A pattern = Si-based alloy are formed, and plasma is applied on this alloy electrode wiring (3). An interlayer insulating film (4) made of a SIN film or 5j021 pattern is formed by the CVD method. This interlayer insulating film (4
) is used as a gate insulating film for amorphous 5i-TFT arrays, a living room insulating film for multilayer wiring, and a passivation preservation A'J film. Next, an I layer is formed on this interlayer insulating film (4) by the same method as above, that is, through photoresist and etching step 1.
', T, O electrode wiring (1) is formed.

By the way, generally -1, SiN film or 5i02+1
In A, as shown in FIG. 4, there are pinhole defects (5),
Defects such as foreign matter defects (fi) caused by reaction products and various low-density defects (7) caused by abnormal growth of interlayer insulation 8 (4) are inevitable, and it is impossible to form a film without defects. 4
．． In addition, in the interlayer insulating film (4) having the above-mentioned structure, the hillock 1
Since one defect is further superimposed, the arrangement of film defects will be additional.

Further, the etching rate of I, T, and O is about 50 OA/min in a hydrochloric acid solution at 4° C., whereas the etching rate of A-type alloys reacts violently at about 50 pm/min. Therefore, the etching solution permeates through the film defects in the interlayer insulating film (4) and etches the alloy electrode wiring (3), resulting in frequent disconnections. Furthermore, the first
Defects similar to those described in FIGS. and FIG. 2 also occur.

Therefore, the semiconductor device manufactured by the above method has the drawbacks of poor performance and low yield.

``Summary of the Invention'' This invention was made to eliminate the drawbacks of the prior art described in 1.
- It is an object of the present invention to provide a method for manufacturing a conductive device with good performance and good sludge by etching electrode wiring made of Tin-Oxide with a sulfuric acid solution or a solution containing sulfuric acid.

[Inventor's Example An embodiment of the present invention will be described below with reference to the drawings.

In Figures 5 and 6, the quartz glass substrate (2)
After forming a 1, T, O film of approximately 1000 A on the surface of the substrate by, for example, electron beam evaporation in a low-pressure oxygen atmosphere, a resist pattern of a desired shape is formed by photo-etching, and then (For example, a sulfuric acid aqueous solution of 70% by weight and a solution temperature of 70° C. is used as the sulfuric acid-based etching solution) to form I, T, and O electrode wirings (1).

In the semiconductor device l formed by the above method, since the sulfuric acid aqueous solution is used, the edges of the pattern of the I, T, and O electrode wirings (1) are not rough, and there are few site edges and sharp fan-like turns. It becomes possible to form

Therefore, a wiring pattern of lines and spaces can be stably formed with an interval of about 5 m.

3 and 4, as shown in FIGS. 7 and 8.
Similar to the prior art shown in the figure, I, T.

After forming a resist pattern and etching with a sulfuric acid solution having a concentration of 20% by weight and a temperature of 70° C., a matrix type two-layer wiring is completed.

In this case, 1. T, ON etching rate, 200
The etching rate of A1 alloy is about 10 per minute, whereas the etching rate of A1 alloy is about 10 per minute. T, O/AM
The etching rate ratio of the alloy reached approximately 20, I,T
, O and A9. Stable selective etching properties of the alloy can be obtained. Therefore, there is no disconnection of the alloy electrode wiring (3) formed under the interlayer insulation II (4), and the manufacturing yield is greatly improved. In addition, Figures 5 and 6
Similar to the embodiment shown in the figure, 1. The T and O electrode wiring (1) can also sharply form a high-definition IK pattern with a width of about 5+1 mm.

[Effects of the Invention] As described below-1, according to the present invention, Indium-Tin-Oxid formed on the substrate or the insulating layer-1-
By etching the electrode wiring consisting of E with a sulfuric acid solution or a solution containing sulfuric acid, it is possible to provide a method for manufacturing a semiconductor device 1δ with good performance and an excellent production yield.

[Brief explanation of drawings]

Figure 1 is a plan view showing a conventional semiconductor device, and Figure 2 is a top view of a conventional semiconductor device.
3 is a plan view showing another conventional semiconductor device, and FIG. 4 is a sectional view taken along line II-II in the figure, and FIG.
5 is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line Vl-V in FIG.
7 is a plan view showing a cliff conductor device according to another embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along line I, FIG.
It is a sectional view along the line. (1)...I, T, O electrode wiring, (2)...substrate, (3)...A cross alloy electrode wiring, (4)...interlayer insulating film. Note that the reference numerals in the figures indicate the same or corresponding parts. Agent Masunori Oiwa Procedural amendment (spontaneous) Mr. Commissioner of the Japan Patent Office 1. Indication of the case: Japanese Patent Application No. 58-217963 2. Name of the invention 6. Method for manufacturing a conductor device 3. To Hitoshi Katayama, representative of the person making the amendment. Section 5, Sleeve 1) - 41 ¥1゜6 of [Detailed Description of the Invention] of Subject Specification 1i1J,
Contents of the amendment (1) The description is amended as follows.

Claims (4)

[Claims] (1) Indium formed on a substrate or insulating layer
- A method for manufacturing a semiconductor device, characterized in that electrode wiring made of Tin-Owide is etched using a sulfuric acid solution or a solution containing sulfuric acid. (2) Is the concentration of Jz sulfuric acid 5 to 4Of? ,amount%
2. The method of manufacturing a semiconductor device according to claim 1, wherein the aqueous solution has a temperature of 50 to 100°C. (3) The method for manufacturing a semiconductor device according to claim 1 or 7752, wherein the insulating S plate 1- is made of a transparent electrode. (4) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein a multilayer wiring made of A-pattern or A1 alloy is formed under the insulating layer.