JPS6010908A - Digital delay device - Google Patents

Abstract

PURPOSE:To delay plural channels by dividing a memory in response to the number of input channels and adjusting the timing reading the divided memories. CONSTITUTION:An analog input signal of 4 channels is converted respectively by A/D converters 9-12 into a digital signal, extracted sequentially by a multiplexer 13 and stored in a memory area corresponding to the channel of a memory 15. The memory 15 is used as a delay means by giving a prescribed time of delay to the reading time of the memory 15 from the time written in the address of the memory 15, the delay time is set at each output channel and the memory 15 is read, the output is distributed into channels CH1-CH8 by a demultiplexer 16, converted into the analog signal by D/A converters 17-24 and outputted to output terminals 25-32.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay device for a digital signal corresponding to an acoustic Q signal, and provides flexibility in circuit configuration by dividing and using memory constituting a delay circuit according to the number of channels. It is a stuttering device that can be adapted to various purposes and usage situations.

The digital 1g delay device that corresponds to the Jin 41 signal is:
For example, it is used to create the acknowledgment decoding required when cutting records. In other words, when cutting records, the NC recording groove pitch (adjacent distance between recording grooves) is changed by 5T depending on the level of the recording signal in order to prevent the cutting from reaching the adjacent groove when the level is high. In order to perform control, the recording groove pitch is adjusted using the original signal as an A (admonition signal) for level determination, and then actual cutting is performed using a signal delayed from this original signal. Another use is to adjust the sound field and acoustic effects by adding a delay to the recorded sound of each instrument in studio recording.

Conventionally, this rod delay circuit has multiple output channels CH for one human power as shown in Figure 1 (67).
I-CHN with various delay times selected, or as shown in FIG. A system is being considered in which the configuration in (a) is provided for the number of human-powered channels.

However, since these delay circuits have a fixed configuration, they are not adaptable and have the disadvantage of requiring a different one to be prepared depending on the purpose and situation of use. For example, in creating the above-mentioned Advance G, the number of input channels may be two in total, the left Ishitani channel, but the delay time is long, about 1.1 seconds (standard), so each memory that makes up the delay circuit needs to be A large capacity was required.

In addition, in the above-mentioned distortion of the sound field and acoustic effects in studio recording, the delay time may be relatively short (several layers sec to
In order to control the delay time for each instrument (several tens of msec), a device with a large number of input channels was required.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a digital signal delay device that can be adapted to various usage situations and purposes.

According to this invention, by dividing and using memory according to the number of memory input channels configuring the delay circuit, the circuit configuration can be made flexible and can be used for various purposes and usage situations.
Be able to adapt.

In other words, when the number of input channels is small, a large memory area can be allocated to each input channel, and a long delay time can be obtained. can get. Also, when the delay time is short, the memory area allocation for each input channel is less, so the number of input channels can be increased accordingly. A suitable configuration can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this example, eight output channels CHI-C
By equally allocating these output channels CHI-CH8 according to the number of input channels, various delays 4g can be achieved for each input channel. That is, when the number of input channels is one, the delay number 1g of 8 blocks is obtained for the input signal.

When there are two input channels, four delay signals are added to each input signal (hereinafter referred to as 2-in mode), and when there are four input channels, Two types of delay signals are obtained for each input 4W signal (hereinafter, this usage pattern will be referred to as 4W).
(called in mode).

FIG. 2 shows an example of the overall configuration of a digital signal delay device to which the present invention is applied. The stiffness device M has four input channels lch to 4eh, and all # signals inputted from the respective input terminals 1 to 4 are digitally converted to A-Df amplifiers 9 to 12 via attenuators 5 to 8, respectively. The signal is converted into a signal and input to the multiplexer 13. The multiplexer 13 selects 1! according to the 1 history mode. Each input channel leh~4eh according to a predetermined clock according to 14 commands from the control device (CPU).
The input data is multiplexed and output at °C. for example,
In the case of 1-in mode, l clock (A-D converter 9
-12 samples of the input channel (for example, the first human-powered channel 1ch) are output one by one. In addition, in the case of 2-in mode, two manual channels (for example, the 11th and 2nd
Outputs samples of human channels Ich and 2eh) one by one. In addition, in the case of 4-in mode, all input channels lah to 4a'+ are input every l clock.
Sequentially output the samples one by one.

Data output from the multiplexer 13 is applied to a memory IJ (RAM) 15 forming a delay circuit.

The memory area of the memo+715 is divided according to the number of input channels in the usage mode according to a command from the city control device 14. That is, in case of l-in mode, all addresses are transferred to that one input channel (e.g. 1eh) without splitting.
In the case of 2-in mode, it is divided into two and each area is used for each input channel (for example, lch, 2ch
), and in the case of 4-in mode, it is divided into four areas and used by allocating each area to all input channels leh to 4ch, respectively.

Therefore, if the memory lj 15 is configured, for example, in 64 words, the allocation awards for each input channel will be: 1 in mode = 64 words in 2 in mode 2 32 in words 4 in mode: 16 words.

The data of each input channel added to the memory 15 is
According to the write address command from 11ilJ @1nx4, the l
The i primary data is written. The write address circulates within the valley area, and older data is written to the older data in sequence. Therefore, if the storage clock is 40 kHz, the maximum delay time obtained in each mode is as follows.

The data stored in memo IJ 15 is the control device j! t
It is read out once by the command from 14. At this time, delayed data can be obtained by shifting the successive address with respect to the write address. This reading is performed in cycles with the glutes.

FIG. 3 shows the relationship between write addresses and read addresses in one divided memory area (address address n). Writing is performed cyclically within the memory area of address n, and old data is sequentially rewritten with new data. Delay time R1
When set to , when writing is performed at clock t1, the data at the address written at clock t□' is read out, and when writing is performed at clock t2, the data at the address written at clock t2' is read out. The data at the address to which writing was performed is read out, and when writing is performed at clock t3, the data at the address to which writing was performed is read out at clock t3', and the write address and read address are separated by a constant interval T1. It is shifted one by one while maintaining this. If the delay data of two kinds is superior to the signal of one input channel, as shown by the dashed line in Fig. 3,
Set another delay time R2 and tle t2 e j3
j1' e j2 when writing by the clock of T...
'pt3' The written data is read using the r... clock. If more delay times are set, more types of delay data can be obtained for No. 9 of one input channel.

In FIG. 2, the data read out from the memory 15 is input to the demultiplexer 16, and according to a command from the control device 14, the data is input to the demultiplexer 16 for each delayed data.
Sorted to HI-CH8. Each output channel C
The delay data distributed to HI to CH8 is converted into the original audio signal by the D-Af receivers 17 to 24, and then guided to the respective channel outputs 25 to 321C.

FIG. 4 shows the memory 150 division state in each mode,
Output channel C)1 for each divided memory area
1- This shows the CH30 allocation status.

Figure 4 (aJ is in the l-in mode, at this time 1
The entire area of the memory 15 is allocated. Also 8 output channels CHI~CH
8 are all assigned to the input channel lch, and a maximum of 8 delay keys can be obtained for the input signal of the input channel lch. FIG. 4(b) shows the case of the 2-in mode, where the memo 5 is divided into two areas 15a and 15b, which are assigned to the input channels leh and 2ch, respectively. The output channels ICH to 8CH are divided into 42 sets, and the output channels ICH to 4ch are assigned to the input channel leh, and the output channels ICH to 8CH are assigned to the input channel 2eh. Therefore, in this case, a maximum of four types of delay signals can be obtained for each person's input signal of 2ah and 2ah. Figure 4 (eJ is 4
In the case of in mode, the memory 15 has four areas 15e.
*15d e 15e + 15f, and input channels leh to 4eh are respectively assigned.

Output channels ICH to 8CH are also divided into 4 groups, output channels ICH and 2CH are human-powered channels lch, and output channels 3CH and 4CH are input channels 2a.
b&C11tl channels 5CH and 6CH are assigned to the manual channel 3eh, and output channels 7CH and 8CH are assigned to the input channel 4eh. Therefore, in this case, a maximum of two delay signals can be obtained for each input channel leh to 4ch.

The connection status between the crowds in each mode is the same as the 5th one song.
In the figure, they can be represented as &), fb), and (e), respectively. Figure 5 (&) is 1-in mode, (
b) is the 2-in mode, and (C) is the 4-in mode.

That is, in the case of 1-in mode, it is equivalent to providing 8 delay elements for one human-powered channel leh, and in the case of 2-in mode, it is equivalent to providing 8 delay elements for one human-powered channel leh,
This is equivalent to providing four delay elements for each of 2eh, and in the case of the 4-in mode, it is equivalent to providing two delay elements for each of the four human channels lah to 4cbVc. In this way, the digital delay device shown in FIG. 2 can realize various combinations of the number of input channels and delay times.

In addition, in Figure 2, select the keyboard mode,
Setting of M delay time (can be set for each output channel ICH to 8CH), etc. is performed. Also, memo +7 (RA
M) 34 stores delay time settings and processing programs. The display device 135 also displays the selected mode g and input channels leh to 4c.
The connection state of H and output channels CHI to CH8 and the delay time of each output channel C)II to CH8 are displayed, for example, in a manner as shown in FIG. 5, so that the current usage state can be seen at a glance.

Next, the actual No. 1g delay of the delay device shown in Figure 2 is shown in Figure 6.
This will be explained with reference to the flowchart shown in the figure.

Before use, select the mode and set the delay times R1 to R8 for each output channel C)11 to CH8 in advance.
Configure settings.

When a mode is selected, the control device 14 calculates the start and end addresses of each divided area in the memory 5 according to the selected mode, and divides the memory into 50 areas. The calculated value is as follows, assuming that the entire area of the memo U 15 is, for example, 0000 to FFFFH (hexadecimal notation).

] Also, since the delay times R1 to R8 can be set within the time for one cycle of vows in each memory area, the longest value that can be set varies depending on the size of the memory area, and as described above,
Based on the 1-in mode, the 2-in mode is 7. The 4-in mode is gradually shorter than the above.

The signal delay operation in each mode is as follows. Incidentally, the relationship between write addresses and read addresses in each mode is shown in FIG.

■l-in mode (Figure 7(a)) If the 1-in mode is selected, there is no division of memo IJ15, so memo 1J15 is input from the first address AI.
The data is sequentially written and read by going around the entire access area. The address for bladder removal is the preset delay time 1l-R8.
Accordingly, the address separation from the current address ADI can be calculated and improved. These read data are demultiplexed and output. Each time one set of merging and reading is completed (this one loop corresponds to 1. sampling period of human data), 1 is incremented by 1 (current address AI), and the current address ADZ is
When the end address El is completed, the process returns to the beginning address Al and repeats the operation.

■2-in mode (Fig. 7(b)) When the 2-in mode is selected, the data of input channels lch, 2eh from the first address Al and A2 is stored in the a area of the divided memory 15. Multiplex and forget it. For reading, output channel CH
For I-CH4, the first memory area 15a O
) Each set delay time R from the current address ADZ
This is performed by accessing the address obtained by calculating from 1 to R41C, and for output channels CH5 to CH8K, the address obtained by calculating from the delay time R5 to R8 set respectively from the current address AD2 of the second memory area 15b. This is done by accessing the address. Each area 15
Each time one set of loading and unloading is completed in a and 15b (also in this case, the current address ADI and AC3 are set to 1, corresponding to one sampling period in the l loop).
Go one step at a time and repeat the above movements. Current address ADZ
, AC3 is the end address of the valley area E1. After completing H2, the process returns to the initial address At, A2 and repeats the operation.

■4-in mode (Fig. 7 (C)) When the 4-in mode is selected, each area 15e-15f of the memory 15 divided into four parts is input from the starting address Al, A2, A3, A4. The data of input channels ehl, eh2, ch3, and ch4 are multiplexed and stored. For the output channels CHI and CH2, reading is performed by accessing the address obtained by calculating from the current address ADI of the first memory area 15c using the set delay times R1 and R2, and for the output channels CH3 and CH4.
, the current address AD of the second memory area 15d
This is done by accessing the current address obtained by calculating the delay times R3 and R4 respectively set from 2, and for output channels CH5 and CH6K, refer to the third memo 1.
This is done by accessing the address obtained by calculating 1 from the set delay time tunes R5 and R61C from the current address AD3 in the 71B area 15s, and outputs the output channel CH.
7. For CH8, the fourth memory area 15 f O
) This is performed by accessing the address obtained by calculating from the current address AD4 using the respective set delay times R7 and R8. 1 in each region 15c to 15f. ! Every time writing and reading of 11 are completed (in this case also, it corresponds to 1 sampling period in 1 loop), the current address ADI, AC3, AC3° AC4 is set to 1.
Go one step at a time and repeat the above steps. Current address ADI
, AC3, AC3, and AC4 complete the end addresses El, 'E2, H3, and H4 of each area, and repeat the operation to return to the beginning addresses AI, A2, A3, and A4.

Note that in the above implementation I5i+1vc, memo U15 is divided equally according to the number of input channels, but if the required delay time differs depending on the input channel, the allocation amount may be changed for each input channel accordingly. It can also be done.

As explained above, according to the present invention, since the memory area is divided and used according to the input channels, it is possible to create various combinations of the number of manual channels and the delay time, and it can be used in various ways. It can be adapted to the purpose and usage situation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional digital delay circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the structure of a conventional digital delay circuit. FIG. 4 is a diagram showing the relationship between addresses and read addresses. FIG. 4 is a diagram showing the divided state of the memory in FIG. 2 in each mode. FIG.
6th diagram showing the equivalent circuit of the connection state of the human output of the device in question.
7 is a flowchart showing the operation of the device of FIG. 2 in valley mode, and FIG. The relationship between read addresses is shown. 1 to 4: input terminal, 15: memory, 15a to 1
5s...Memory division area, δ~32...Output terminal,
lah~4ch...Input channel, CHI-CH
8...Output channel.

Claims (1)

[Claims] The memory constituting the delay circuit is divided according to the input channel of the digital signal corresponding to the sound No. 1M, and each divided memory area is used to delay the digital signal of each person. Digital delay circuit.