JPS60102021A - Diagnostic system of logical circuit - Google Patents

Abstract

PURPOSE:To hold values of the latch group of a partial circuit to be diagnosed and take a diagnosis without the intervention of an operator by adding a partial circuit which cuts off a signal to the latch group and substituting this latch group with an equivalent circuit. CONSTITUTION:A partial circuit 29 consisting of an AND gate 25 which inhibits the input of a signal to an input latch 22 of a partial circuit 28 to be diagnosed, and a latch 26 is added to the partial circuit 28 to be diagnosed, and the partial circuits 28 and 29 are regarded as a test pattern generation uint. Then, the input latch 22 is substituted with the equivalent circuit which outputs an indefinite value ''X'' when the level of a timing signal supply line 27 is ''1''. If a single regenerative fault occurs on an input signal line 30 of an OR gate 33, that is detected from the propagation through the OR gate 33, the transmission of a timing signal T0 from an output latch 34, and the scanning-out operation of the output latch 34, so such a test pattern that a timing input signal line 37 of an equivalent circuit 32 is set to ''0'' is generated to attain the detection.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for diagnosing logic circuits, and particularly to logic circuits and logic circuits that include a group of latches whose values may be destroyed by synchronous or asynchronous timing signals. The present invention relates to a diagnostic method suitable for.

[Background of the invention]

In logic circuits such as large-scale integrated circuits, a method is generally used to diagnose the circuits by dividing them into a plurality of partial circuits each consisting of a group of latches that can be scanned in and scanned out, and combinational circuits surrounded by the latches.

In this case, for subcircuits containing launch groups whose values can be destroyed by synchronous or asynchronous timing signals,
Conventionally, the timing signal supply line for the latch group was
Fixed value 1; 7 to the desired latch outside the partial circuit to
Based on the dest pattern created by the design, the following three steps are performed: A, scan-in port of the input latch f, ＼, timing signal sending of the output latch I\, and scan-out of the output latch f. The relevant partial circuit was tested.

FIG. 1 is a diagram explaining this conventional method, in which 11 is a target partial circuit (combinational circuit), 12 is an input latch, 1;
14 is an output latch, 14 is a timing signal supply line, 15 is an AND gate, and 16 is a fixed value designation latch. That is, this is an example of a partial circuit in which the input latch 12 and the output latch I3 are in an in-phase transfer relationship. Conventionally, a timing signal T is used for such a partial circuit 11. input latch 12
Under the condition that the latch I6 outside the partial circuit that affects the contents of the partial circuit is selected and fixed to II OI+, the partial circuit 11 itself is used as the test pattern generation m position to generate a test pattern and perform the test. be.

However, in the past, the latches outside the above-mentioned partial circuits and their values were specified manually, which caused the problem of pointing out the failure location due to poor specification. An object of the present invention is to provide a diagnostic method for a logic circuit that eliminates manual intervention and does not require consideration of the destruction of lunch groups caused by synchronous or asynchronous signals.

[Summary of the Invention] The present invention creates a partial circuit in which a group of latches whose values can be destroyed by synchronous or asynchronous Sending synchronous or asynchronous signals to 4iIII
Add another partial circuit with ll +l.

The present invention is characterized in that the last pattern is automatically generated and tested as a test pattern generation unit for these partial cycles.

[Embodiments of the invention]

FIG. 2 is a diagram illustrating the first embodiment of the present invention. In Figure 2, 28 is the target subcircuit consisting of latches 21, 22, 24 and a combinational circuit with t:, -C+++ and 1:, and its input latch 22 and output Color two 1-24 have the same timing signal 1゛.

It is a common mode transfer latch controlled by This in-phase transfer latch 2: J! , 24, the timing signal T of the output latch 24\. In order to prevent the value of Rokukara J22 from becoming too narrow when sending out the signal, it is necessary to fix the timing signal supply line 27 to 110B1.To this end, the present invention does the following.

(1) The timing signal supply line 27, ant game
A partial circuit 29 including 1-25 and a latch 26 is added to the diagnostic target partial circuit 28 as an in-phase transfer inhibiting circuit, and the partial circuits 28 and 29 are set as the worst pattern generation unit.

(2) When the timing signal supply line 27 of the in-phase transfer input latch 22 is II 1'', the output is an uncertain value 71 X I
Replace it with an equivalent circuit that becomes I.

FIG. 3 shows the test pattern generation unit replaced by the equivalent circuit after implementing (1) and (2) above.

In FIG. 3, 31.34.36 are latches corresponding to 21.24.26 in FIG. 2, respectively. 33.35
is the or gate 23° ant game 1-25 in FIG. 32 is a circuit in which the input latch 22 of FIG. 2 is replaced with an equivalent circuit, and when the timing signal supply line 37 is " ] ", the output signal line 39 has an uncertain value II X 'g.

Now, if we assume a single stuck-at fault in the input signal line 30 of ORGOO 1 to 33, the fault will be: ■ Propagation via OR gate 33 ■ Sending timing signal 1゛. ) Output ramp (observed by the scan alarm 1~ of 4. In FIG. 3, the timing signal line 37 of the 1 equivalent circuit 32 is generated to the worst pattern set to "o", so that the signal line 30 is It becomes possible to propagate the assumed stuck-at fault to the output latch 34. In this case, the latch 36 functions as an in-phase transfer inhibition latch whose value is always "o", and automatic in-phase transfer inhibition can be implemented.

FIG. 4 is a diagram for explaining a second embodiment of the present invention, and shows an example in which the latch 44 corresponding to the launch 2G in FIG. 2 is further in phase with the latches 42 and 43. Even in this case, by performing the same processing on the latch 44 as the input latch 22 in FIG. 2, it is possible to automatically hold the value of the in-phase transfer latch 44 when the timing signal >3'' is sent. , carry out the following:

(1) A partial circuit 47 consisting of a latch 45 and a latch 46 is further added to the ant game 1 as a circuit that affects the sending of timing signals of the latches 4 and 1.

(2) Replace the latch 44 with an equivalent circuit.

This is exactly the same when the circuit 47 added to the latch 44 further includes a dot transfer latch.

So far, we have described logic circuits that involve synchronous signals, but the same processing can also be applied to logic circuits that involve asynchronous signals.

In FIG. 5, the reset signal line 56 of the input latch 52 in the partial circuit 57 is only divided into individual parts by the output of the latch 55.
This is an example where there is no AND condition with the timing signal as shown in FIG. In this case as well, by carrying out the following steps, the partial circuit 5 can be
The diagnosis of 7 is uJ function.

(1) A partial circuit 58 that affects the sending of an asynchronous signal (recession 1-signal) to the input latch 52 is added.

(2) Connect the input latch 52 to the reset signal line 56.
1”, the circuit is replaced with an equivalent circuit whose output is an uncertain value “x”.

FIG. 6(n) shows an example of a latch circuit, and FIG. 6(b) shows an example of its equivalent circuit. That is, for the latch 61 whose value can be destroyed by the synchronous or asynchronous signal shown in FIG.
The equivalent circuit in which the output becomes an uncertain value "x" when the R input (reset) is II L H is shown in Figure 5 ().
)). In FIG. 6(b), 2 is an uncertain value generation circuit, and 63 is an RS fritz. 1 block, and when any of the inputs CK, S, and R is "l", and the output of the uncertain value generation circuit 62 is set to 1", the outputs Q and Q of the flip-flop 63 will eventually become C+ " ] ". Become.

FIG. 7 shows the processing flow of the diagnostic method according to the present invention in the case of a logic circuit including in-phase transfer latches at 1 and 11'.

First, regarding a logic circuit that includes a group of latches that can be controlled by a timing signal and that can be scanned or scanned,
Create a plurality of partial circuits consisting of a desired launch group and combinational circuits surrounded by it (step I fit
Q). Next, it is checked whether there is an in-phase transfer relationship between the input latch P and the output latch Q in the partial circuit A to be diagnosed and whether a control signal is present (step 101). And YE
S is nine.

Another partial circuit B that can suppress the sending of the synchronization signal to the corresponding input latch P is added (step 102).

For example, in the case of FIG. 2, the input latch 22 and output latch 24 in the subcircuit 28 to be diagnosed are in-phase transfer latches,
In addition, since the latch 26 is present as a control signal source for the input latch 22, a partial circuit 29 including the latch 26 is added to the partial circuit 28. Next, the in-phase transfer input latch P is replaced with an equivalent circuit (step 103). For example, in the case of FIG. 2, when the clock signal C to the input latch 26 is "o", the output of the latch 26 becomes the value of the latch 26 itself, and the clock signal CK becomes i.
``, the output of the latch 26 is replaced with an equivalent circuit having an uncertain value ``×'''' (see FIG. 3).

Next, using partial circuits A and B as test pattern generation units,
A terminal (output latch Q) for observing failures in the subcircuit A to be diagnosed
) to generate a test pattern to be propagated to (step 104). FIG. 13 shows an algorithm for generating a test pattern in which a single stuck-at fault S assumed on the signal line 30 in FIG. 3 is propagated to the output latch 34.

In other words, the generation of the dest pattern is based on the uncertainty value II
This is done in a direction that avoids the propagation of gg, and as a result, in the example of FIG. 3, path 1 is selected by one length.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the signal of the latch group l\ is transmitted to the partial circuit including the edge group whose value may be destroyed by a synchronous or asynchronous signal. By generating a test pattern that includes other subcircuits that can be suppressed, human intervention can be completely eliminated. Effects such as no need for verification can be obtained.

-4. Brief explanation of the drawings Figure 1 is a diagram explaining the conventional diagnostic method, Figure 2 is a diagram showing an embodiment of the diagnostic method according to the present invention, and Figure 3 is a diagram based on the equivalent circuit of Figure 2. 4 and 5 are diagrams showing other embodiments of the diagnostic method according to the present invention, and FIG. 6(a)
, (b) is a diagram showing a latch circuit and its equivalent circuit, FIG. 7 is a diagram showing an example of the processing flow of the diagnostic method according to the present invention, and FIG.
The figure shows an example of an algorithm for generating test patterns.

28.29...Partial circuit, 22...Input latch.

24...Output latch.

Representative Patent Attorney Akio Takahashi 2 rays Figure 3 4th Shil 51st Tsu 1 Figure 6 tn) Figure 7 Figure 8 ) call Pamata 2

Claims (1)

[Claims] (1) Testing by dividing a logic circuit into multiple subcircuits) - In a method of generating and diagnosing patterns, the above-described method is used for a subcircuit to be diagnosed that includes a launch group whose value can be destroyed by synchronous or asynchronous signals. Adding another partial circuit capable of suppressing synchronization to the latch group or sending out signals of non-same weeks, and replacing the latch group with an equivalent circuit to generate the dest pattern and hold the value of the latch group. A method for diagnosing a logic circuit characterized by diagnosing a partial circuit to be diagnosed based on the state.