JP2501202B2 - Logic circuit diagnosis method - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a method of diagnosing a logic circuit by dividing it into a plurality of partial circuits, and a logic circuit suitable for a logic circuit having a partial circuit whose expected value cannot be guaranteed when a certain specific clock is applied. Regarding diagnostic methods.

[Prior art]

A logic circuit of a certain size or more is composed of a plurality of combinational circuits connected via flip-flop groups. Although formed as such a logic circuit LSI or mounted on a printed wiring board, the diagnosis of such a logic circuit is performed by combining all circuits as described in, for example, Japanese Patent Laid-Open No. 60-102021. And logically divided into a plurality of partial circuits consisting of the input and output flip-flop groups, and after setting the diagnostic input data to the input flip-flop group for each partial circuit, apply the clock to the output flip-flop group. Thus, the logical operation result from the combinational circuit is set in the output flip-flop group, which is read as an observed value and compared with the expected value. This is called a circuit division diagnosis method. When the input or output of the combinational circuit is the edge pin group, the edge pin group is the division position.

[Problems to be Solved by the Invention]

In the conventional circuit division diagnosis method, for example, a combinational circuit such as a synchronous transfer circuit in which input and output flip-flop groups are controlled by the same clock and an asynchronous control circuit in which flip-flop groups are controlled by signals other than the clock are used. For the partial circuit of the circuit that destroys the contents of the input flip-flops when the logical operation result of is set in the output flip-flops, the output observed value is not determined and the expected value calculated in advance However, accurate failure detection was impossible. Further, regarding the partial circuit in which the output of the partial circuit is the output edge pin and the data is propagated to the output edge pin by the application of the clock, the output observation value is determined only in the presence of the clock, and other than the expected value, There is a possibility that they may be different, and it is practically impossible to detect a failure in the partial circuit. An object of the present invention is to provide a method for diagnosing a logic circuit, which guarantees an output observation value even for a partial circuit under the above conditions and improves the failure detection rate.

[Means for Solving the Problems]

The present invention sets the combinational circuit logical operation result to the output flip-flop group after setting the diagnostic input data to the input flip-flop group (when the output of the combinational circuit is the output edge pin, the logical operation result is output to the output edge pin). When observing), select an input edge pin for which a clock is not input to the input flip-flop group for each partial circuit, and create a diagnostic clock control pattern that activates the output flip-flop group at the input edge pin. That is, the output observation value is obtained in a steady state. When the output of the combinational circuit is an output edge pin, the selected input edge pin is treated as a level signal.

[Action]

In the present invention, when the logical operation result of the combinational circuit is set in the output flip-flop, the clock input pin is selected for each partial circuit and the diagnostic clock control pattern is applied so as not to destroy the contents of the input flip-flop group. , It is possible to prevent the contents of the input flip-flop group from being destroyed and to take the wrong value into the output flip-flop, and to never observe the wrong value. Also, when the output of the combination circuit is the output edge pin group, the level signal is applied instead of the clock, so during observation, the logical operation result of the combination circuit is guaranteed for the output edge pin group, and it is also necessary to observe the wrong value. There is no.

【Example】

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 conceptually shows an example of a logic circuit to be diagnosed. In FIG. 2, the logic circuit 1 represents an entire logic circuit formed as an LSI or mounted on a printed wiring board. The logic circuit 1 is divided into a plurality of partial circuits 2 for the purpose of diagnosis. Logically divided. One partial circuit 2 includes a logic block 3 composed of a combinational circuit, an input flip-flop group 4 located in the front stage of the logic block 3, an output flip-flop group 5 located in the rear stage,
The clock line 6 is input to the input and output flip-flop groups 4 and 5. The input flip-flop group 4 may be an input edge pin group and the output flip-flop group 5 may be an output edge pin group. After setting the diagnostic input data in the input flip-flop group 4, the diagnostic clock is applied to the clock line 6 to set the logical operation result of the logic block 3 in the output flip-flop group 5, and finally the output flip-flop group. The contents of group 5 are read. The logic circuit 1 is diagnosed by repeating this process for each partial circuit. When the diagnostic clock of the clock line 6 is applied to the input flip-flop group 4 at the same time as the output flip-flop group 5, the diagnostic input data of the input flip-flop group 4 is destroyed (the state of the data input terminal is Since it is not guaranteed that it is in the same state as when the diagnostic input data is set), an incorrect value is set in the output flip-flop group 5, so correct diagnosis cannot be expected. FIG. 1 shows a flowchart for selecting a specific clock pin for each partial circuit and creating a clock control pattern for the clock pin according to the present invention. In the figure, FF represents a flip-flop. First, it is determined whether the output point of the partial circuit is a flip-flop (step 101), and for each partial circuit whose output point is a flip-flop, the logic from the clock terminal of the output flip-flop group to the input flip-flop group or the input edge pin is determined. Trace backward (fan-in trace)
Then, all the reached input edge pins are used as diagnostic clock candidate pins (step 102). Next, the following pattern is created for each of these candidate pins (step
103). 1. Creating a pattern that activates the path from the clock candidate pin to the output FF group. 2. Create a pattern that turns the clock terminals of the input FF group to "OFF" (logical value "0"). 3. Create a pattern that sets the clock candidate pin to "NO" (logical value "1"). With respect to the patterns created by the above 1, 2 and 3, it is judged whether or not there is a pattern (that is, the same pattern) that satisfies all the conditions (step 104), and if any one of the patterns exists, its clock candidate The pin is used as a diagnostic clock pin for the partial circuit (step 107). That is, the clock candidate pin and its clock control pattern satisfy the condition of activating the output FF group without activating the input FF group, and using this, the logical operation result of the combinational circuit of the partial circuit is used. When is set to the output FF group, the value of the input FF group is not destroyed. If a pattern satisfying the above conditions is not obtained even after processing all the diagnostic clock candidate pins, an arbitrary clock candidate pin is selected as the diagnostic clock pin of the partial circuit and its synchronous or asynchronous flip-flop group is selected. It is excluded from the diagnosis target (steps 105 and 106). That is, since the observed value of the output FF group at that time may be an incorrect value, it is excluded from the target of diagnosis. On the other hand, when the output point of the partial circuit is the output edge pin, all the input edge pins are used for level signal application (step 108). By repeating the above process for each partial circuit,
The selection of the diagnostic clock pin of each partial circuit and the creation of its control pattern are completed (step 109). When setting the logical operation result of each logic block at the time of diagnosis to the output flip-flop group, apply the clock or control signal (clock control pattern) to the selected input edge pin independently for each partial circuit. Thus, the contents of the input flip-flop group are guaranteed, and a predetermined observation value is obtained at the output flip-flop group or the output edge pin in the steady state. FIGS. 3 to 5 show examples of measures according to the present invention. FIG. 3 shows a case of a synchronous transfer circuit, FIG. 4 shows a case of an asynchronous control circuit, and FIG. 5 shows a case of a clock passing circuit. . Here, 11 and 12 are partial circuits before countermeasures, 13 and 14 are partial circuits after countermeasures, 15 is a clock line during actual operation, and 16 and 17 are clock lines during diagnosis. Each sub-circuit 11, 12 is clocked on line 15 during actual operation. If this clock line 15 is also used during diagnosis, it becomes a synchronous transfer circuit for the partial circuit 11 of FIG. 3, and when a clock is applied to the output flip-flop group, the same clock is also applied to the input flip-flop group. , The contents of the input flip-flop group are destroyed, and the operation result of the logic block based on this is set in the output flip-flop group, so that proper diagnostic data (observation value) is obtained.
Can't get Also, for the partial circuit 11 of FIG.
When the asynchronous control signal of the input flip-flop is suppressed as shown in the figure (low "L"), the clock is not applied to the output flip-flop, the operation result of the logic block is not set in the output flip-flop group, and No proper diagnostic data can be obtained. This Fig. 3 and 4
In the case of the figure, by selecting the lines 16 and 17 and applying a clock according to the flowchart of FIG. 1 and activating the path from the line to the output flip-flop, the input flip-flop is activated when the clock is applied. Since the output flip-flops are not activated but only the output flip-flops are activated, a proper observation value can be obtained for the output flip-flops. Further, for the partial circuit 12 of FIG. 5, when a clock is applied to the clock line 15 at the time of diagnosis, the partial circuit 12 becomes a clock passing circuit, and the operation result of the logic block is not held at the output edge pin. In such a case, by forming the partial circuit 12 in the form of the data partial circuit 14 and applying a level signal to the line 17 corresponding to the line 15, the operation result of the logic block is held at the output edge pin at the time of diagnosis, and an appropriate value is obtained. It can be obtained from diagnostic data (observed values).

【The invention's effect】

As is clear from the above description, according to the present invention, it is possible to detect the stuck-at faults of the synchronous transfer circuit, the asynchronous control circuit, and the clock passing circuit, which cannot be sampled by the conventional method. It can be expected that the fault coverage will be improved by several percent.

[Brief description of drawings]

FIG. 1 is a flow chart of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a logic circuit to be diagnosed according to the present invention, and FIGS. 3 to 5 are diagrams showing a target example according to the present invention. 1 ... Logic circuit, 2 ... Partial circuit, 3 ... Logic block, 4 ...
Input flip-flop group, 5 ... Output flip-flop group, 11, 12 ... Partial circuit before countermeasure, 13, 14 ... Partial circuit after target, 15 ... Clock line in actual operation.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shun Ishiyama 1 Horiyamashita, Hadano City Hitachi Ltd. Kanagawa factory

Claims (2)

(57) [Claims] 1. A logic circuit comprising a combinational circuit, a front stage input edge pin group and a rear stage output flip-flop group, a combination circuit, a front stage input flip-flop and a rear stage output flip-flop, and a combination circuit and a front stage input flip-flop, respectively. Divide into a plurality of partial circuits surrounded by the output edge pin group of the latter stage, and set the diagnostic input data to the input edge pin group or the input flip-flop group for each partial circuit,
In the logic circuit diagnosis method of outputting the logical operation result of the combinational circuit to the output flip-flop group or the output edge pin group and comparing it with the expected value, regarding the partial circuit surrounded by the combinational circuit, the input flip-flop group and the output flip-flop group. , Fine traces in the reverse direction from the clock terminals of the output flip-flop group, and reach the input pin as a diagnostic clock candidate pin. Among the diagnostic clock candidate pins, the input flip-flop group is not activated and the output flip-flop group is not activated. A method for diagnosing a logic circuit, characterized in that a candidate pin whose group is activated is selected and a diagnostic clock control pattern is applied. 2. A logic circuit comprising a combinational circuit, a front stage input edge pin group and a rear stage output flip-flop group, a combination circuit and a front stage input flip-flop and a rear stage output flip-flop, and a combination circuit and a front stage input flip-flop, respectively. Divide into a plurality of partial circuits surrounded by the output edge pin group of the latter stage, and set the diagnostic input data to the input edge pin group or the input flip-flop group for each partial circuit,
In the logic circuit diagnosis method of outputting the logical operation result of the combinational circuit to the output flip-flop group or the output edge pin group and comparing with the expected value, when the output point of the partial circuit is the output edge pin, a signal is output to the output edge pin A method for diagnosing a logic circuit, characterized in that a level signal is applied to an input pin that activates a gate.