JPS60101975A - Hetero-junction fet - Google Patents
Hetero-junction fetInfo
- Publication number
- JPS60101975A JPS60101975A JP21022583A JP21022583A JPS60101975A JP S60101975 A JPS60101975 A JP S60101975A JP 21022583 A JP21022583 A JP 21022583A JP 21022583 A JP21022583 A JP 21022583A JP S60101975 A JPS60101975 A JP S60101975A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- xas
- alxga1
- role
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 235000008733 Citrus aurantifolia Nutrition 0.000 description 1
- 101100080050 Oryza sativa subsp. japonica NIP2-2 gene Proteins 0.000 description 1
- 235000011941 Tilia x europaea Nutrition 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 239000004571 lime Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明はへテロ接合FETに関する。[Detailed description of the invention] Industrial applications The present invention relates to heterojunction FETs.
従来例の構成とその問題点
GaAsLSIに用いられるFETとしてt:11、構
造の簡単なM E S F’ E Tが主流である。し
かし、M E S F B、Tを再現性良く製造するに
は、ノーマリーオノMESFETでは活性層厚1000
人を±6%程度の精度で制御する必要があシ、これは現
在の技術では困難でGaAs LSI実現の大きな壁と
なっている6、この」:うなMKSFETに対し、ゲー
トとしてP Jl、l! A exG a 、、 A
s層を用いるヘテロ接合FET (以下HJFETと略
記する。)は、ビルトイン電圧が約1.4vとMESF
KTの0.8Vに比して大きく、論理振l]が大きくと
れること活性層厚を厚くできること等の長所がある。し
かしP型A lx G a 1 x A s層の比抵抗
が大きいために、第1図に示す、1うにゲート1の形状
をドレイン2全囲む閉ループにする必要があシ、LSI
用素子には適さなか一ノ/+Z (1尚、第1図で3は
ソースである0
発明の目的
本発明は上記欠点に鑑み、LSIに適したヘテロ接合F
ETを1)、1供するものである。Conventional Structures and Problems The mainstream FETs used in GaAs LSIs are M E S F' ET, which has a t:11 and a simple structure. However, in order to manufacture M E S F B, T with good reproducibility, the active layer thickness must be 1000 mm for normally ono MESFETs.
It is necessary to control the human body with an accuracy of about ±6%, which is difficult with current technology and is a major barrier to realizing GaAs LSI6. ! A exG a,, A
A heterojunction FET (hereinafter abbreviated as HJFET) using an s-layer has a built-in voltage of approximately 1.4V and is MESF
It is larger than KT's 0.8V, and has advantages such as a large logic voltage and the ability to increase the thickness of the active layer. However, because the specific resistance of the P-type AlxGa1xAs layer is large, it is necessary to make the shape of the gate 1 into a closed loop that completely surrounds the drain 2, as shown in Figure 1.
In view of the above-mentioned drawbacks, the present invention provides a heterojunction F suitable for LSI.
1).
発明の構成
この目的金達成するために、本発明のへテロの接合FI
Tは、A7?xGa、 −xAsからなるゲート上に金
属層を設けて構成これている。Structure of the Invention In order to achieve this object, the heterojunction FI of the present invention
T is A7? It is constructed by providing a metal layer on the gate made of xGa, -xAs.
実施例の説明
以下に本発明の実施例について図面を参照しながら説明
する。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第2図は本発明の一実施例におけるH、TFETと
の断面か示すものである。第2図において、11はCr
ドープ半絶縁性GaAs基板、12はアンドープGaA
sバッファ層、13は分離領域14はn1ンース、ドレ
イン領域、15はP型Ala、+(”o、6Asゲ一ト
層、16はタングステン層、17はn型GaAs活性層
、1Bは5i02膜、19は層間絶縁膜、20はA u
G e / A u オーミック電極、21はT1/
Au配線層である。FIG. 2 shows a cross section of H and TFET in one embodiment of the present invention. In Figure 2, 11 is Cr
Doped semi-insulating GaAs substrate, 12 is undoped GaA
s buffer layer, 13 is the isolation region 14 is the n1 source and drain region, 15 is the P-type Ala, +("o, 6As gate layer, 16 is the tungsten layer, 17 is the n-type GaAs active layer, and 1B is the 5i02 film. , 19 is an interlayer insulating film, 20 is A u
G e / A u ohmic electrode, 21 is T1/
This is an Au wiring layer.
次に、この実施例のH,TFKTの製造方法について説
明する。まず、第3図に示すように、Orドープ半絶縁
性GaAs基板11をクリーニング後分子線エビクキシ
アル(MBE)装置へ導入し、アンドープGaAsバッ
ファ層12を27tm、キへ・リア濃度1 X 10”
cm ’のn型GaAs活1/1層17を・0.14μ
m、濃度I X 10”’on SのP”+’! A
&o、z ” ’o、6Asゲート層15を0.2μm
成技する。次に、フォー・レジスト12でマスクしてイ
オン注入でボロンを100〜1soKe’Vで10”c
tF−2注入し、トランジスタ領域23の分離をする。Next, a method for manufacturing H, TFKT of this example will be explained. First, as shown in FIG. 3, an Or-doped semi-insulating GaAs substrate 11 is cleaned and then introduced into a molecular beam evixial (MBE) apparatus, and an undoped GaAs buffer layer 12 is formed with a thickness of 27 tm and a Kihe-rea concentration of 1 x 10''.
cm' n-type GaAs active 1/1 layer 17, 0.14μ
m, concentration I X 10"'on S'P"+'! A
&o, z ” 'o, 6As gate layer 15 with a thickness of 0.2 μm
Accomplish a skill. Next, mask with four resist 12 and ion implant the boron at 10"C at 100 to 1soKe'V.
tF-2 is implanted to isolate the transistor region 23.
次に、トランジスタ領域23上のレジスト22を除去後
、スパック−によって夕/ゲステンを0.4μm蒸着す
る。このタングステン層16ば、移動度が低くしだがっ
て抵抗の高いP型Ap(,4G ao、4A s で構
成きれているゲート層15の抵抗を実質的に下ける役割
をする。更に注入によって絶縁化されている分%1領域
13のA l o、a G ao、6 A s層に代っ
て配線層の役割を果たす。Next, after removing the resist 22 on the transistor region 23, a 0.4 .mu.m thick layer of Gesten is deposited by spacing. This tungsten layer 16 serves to substantially lower the resistance of the gate layer 15, which is composed of P-type Ap (, 4G ao, 4A s ), which has low mobility and high resistance. It plays the role of a wiring layer in place of the A lo, a Gao, and 6 As layers in the insulated %1 region 13.
次にゲート領域をマスクした後にプラズマエッチにより
先ず、タングステン層16を選択的に除去し、次にヨー
ドエッチ液によって、P mA IJ 0.4G+L、
)、6ASFiを沢択エッチしゲートを形成する。Next, after masking the gate region, the tungsten layer 16 is first selectively removed by plasma etching, and then by an iodine etchant, P mA IJ 0.4G+L,
), 6ASFi is selectively etched to form a gate.
この方法により、n型に a A s活性層はMBEの
精度を保持する“jlが用来る(第4図)。By this method, an n-type a As active layer can be used that maintains the accuracy of MBE (FIG. 4).
次にソースドレインとなる領域にSiを170=180
kOV−C1013Cnl−2注入し、n生型とする(
第6図)。このII、1、ゲート層15自身がマスクに
なり、いわゆるヒルファライメ/ト注入となる。Next, add 170=180 Si to the region that will become the source and drain.
Inject kOV-C1013Cnl-2 to make n-live form (
Figure 6). This II,1, gate layer 15 itself serves as a mask, resulting in so-called Hilfa lime implantation.
次に、5i07膜4−彼着し、800°Cで16分アニ
ールした後、通常の電極工程により、AuGe/Auの
オーミック電極20.Ti/Auの配線層21を形成し
てHJFETを完成でせる0
発明の効果
本発明は注入で絶縁化された分1η1]領域のAeXG
al−xAs層に代ってゲート層」二に形成した金属層
がゲート配線層の役割を果たす。この結果ゲート形状を
閉ループにする必要がなくなり、LSI川H用FETに
適した構造になる。iだ金属層によってゲート抵抗が下
げられ低いゲート 抵抗のHIFETが得られる。Next, the 5i07 film 4 was deposited and annealed at 800°C for 16 minutes, followed by a normal electrode process to form an AuGe/Au ohmic electrode 20. The HJFET can be completed by forming a Ti/Au wiring layer 210. Effects of the Invention The present invention provides an Ae
A metal layer formed on the gate layer 2 instead of the al-xAs layer plays the role of a gate wiring layer. As a result, there is no need to make the gate shape into a closed loop, resulting in a structure suitable for an LSI river H FET. The metal layer lowers the gate resistance, resulting in a HIFET with low gate resistance.
第1図は、従来ノHJ F E T ノ平1fii図、
第2図は本発明に係るf(JFETの構造断面図、第3
図〜第6図は本発明に係るH、TFETの製j電l:4
’J”を示す図で、第3図、第5図は断面図、第4図t
L平面図である。
12・・・・アンドープG?LA Sバッフ/層、13
・・・・・・分離領域、14・・・・・ソース、ドレイ
ン領域、15・・・・・・P型Aρ。、a G 2L0
.6A Sゲート層、16・・・・・・タングステン層
、17・・・・・・n1GaAs活性層、18・・・・
・Sin、膜、19−・・層間絶縁膜、21・・・・・
・T i/A u配線層、2O−=−Au(、e/Au
オーミック電4+640
代理人の氏名 弁理ト 中 尾 敏 男 ほか1名第
1 図
第 2 図
第3図
第4図
6Figure 1 is a conventional HJ FET Nohira 1fii diagram,
Fig. 2 is a structural sectional view of f (JFET) according to the present invention;
Figures to Figure 6 show the manufacturing method of H and TFET according to the present invention: 4
This is a diagram showing 'J', Figures 3 and 5 are cross-sectional views, and Figure 4 is a sectional view.
FIG. 12...Undoped G? LA S buffer/layer, 13
... Separation region, 14 ... Source, drain region, 15 ... P type Aρ. , a G 2L0
.. 6A S gate layer, 16...Tungsten layer, 17...n1GaAs active layer, 18...
・Sin, film, 19-... interlayer insulating film, 21...
・T i/A u wiring layer, 2O-=-Au(, e/Au
Ohmic Den 4+640 Name of attorney: Toshio Nakao and 1 other person
1 Figure 2 Figure 3 Figure 4 Figure 6
Claims (1)
導電型の’[X eal−X As層からなるゲート層
、をらに前記ゲート層の上に、金属層がそれぞれ形成さ
れるとともに、前記GaAs基板の表面の周辺部に素子
分離領域が形成されていることを!1+J徴とするヘテ
ロ接合FET。On the surface of a GaAs substrate of one conductivity type, a gate layer consisting of a '[xeal- Also, note that an element isolation region is formed at the periphery of the surface of the GaAs substrate! Heterojunction FET with 1+J characteristic.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21022583A JPS60101975A (en) | 1983-11-08 | 1983-11-08 | Hetero-junction fet |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21022583A JPS60101975A (en) | 1983-11-08 | 1983-11-08 | Hetero-junction fet |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60101975A true JPS60101975A (en) | 1985-06-06 |
Family
ID=16585856
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21022583A Pending JPS60101975A (en) | 1983-11-08 | 1983-11-08 | Hetero-junction fet |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60101975A (en) |
-
1983
- 1983-11-08 JP JP21022583A patent/JPS60101975A/en active Pending
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