JPS60101975A - Hetero-junction fet - Google Patents

Abstract

PURPOSE:To obtain low gate resistance by forming a metallic layer on a gate layer consisting of AlxGa1-xAs. CONSTITUTION:An un-doped GaAs buffer layer 12, an n type GaAs active layer 17 and a p type AlxGa1-xAs gate layer 15 are grown on a Cr doped semi-insulating GaAs substrate 11. A transistor region is isolated through ion implantation while being masked with a photo-resist. The resist is removed, and a W layer 16 is formed. The layer 16 fills the role of the substantial lowering of the resistance of the layer 15 having high resistance. It fills the role of a wiring layer in place of an AlxGa1-xAs layer in an isolation resion 13. The layer 16 is removed selectively, and the layer 15 is etched selectively to form a gate. Si is implanted into regions 14 as source-drain, and the regions 14 are changed into an n<+> type. According to the constitution, the metallic layer on the gate layer fills the role of the gate wiring layer in place of the AlxGa1-xAs layer in the isolation region insulated through implantation. Consequently, the shape of the gate needs not be brought to a closed loop, and structure fitted to an LSI is formed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to heterojunction FETs.

Conventional Structures and Problems The mainstream FETs used in GaAs LSIs are M E S F' ET, which has a t:11 and a simple structure. However, in order to manufacture M E S F B, T with good reproducibility, the active layer thickness must be 1000 mm for normally ono MESFETs.
It is necessary to control the human body with an accuracy of about ±6%, which is difficult with current technology and is a major barrier to realizing GaAs LSI6. ! A exG a,, A
A heterojunction FET (hereinafter abbreviated as HJFET) using an s-layer has a built-in voltage of approximately 1.4V and is MESF
It is larger than KT's 0.8V, and has advantages such as a large logic voltage and the ability to increase the thickness of the active layer. However, because the specific resistance of the P-type AlxGa1xAs layer is large, it is necessary to make the shape of the gate 1 into a closed loop that completely surrounds the drain 2, as shown in Figure 1.
In view of the above-mentioned drawbacks, the present invention provides a heterojunction F suitable for LSI.
1).

Structure of the Invention In order to achieve this object, the heterojunction FI of the present invention
T is A7? It is constructed by providing a metal layer on the gate made of xGa, -xAs.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a cross section of H and TFET in one embodiment of the present invention. In Figure 2, 11 is Cr
Doped semi-insulating GaAs substrate, 12 is undoped GaA
s buffer layer, 13 is the isolation region 14 is the n1 source and drain region, 15 is the P-type Ala, +("o, 6As gate layer, 16 is the tungsten layer, 17 is the n-type GaAs active layer, and 1B is the 5i02 film. , 19 is an interlayer insulating film, 20 is A u
G e / A u ohmic electrode, 21 is T1/
This is an Au wiring layer.

Next, a method for manufacturing H, TFKT of this example will be explained. First, as shown in FIG. 3, an Or-doped semi-insulating GaAs substrate 11 is cleaned and then introduced into a molecular beam evixial (MBE) apparatus, and an undoped GaAs buffer layer 12 is formed with a thickness of 27 tm and a Kihe-rea concentration of 1 x 10''.
cm' n-type GaAs active 1/1 layer 17, 0.14μ
m, concentration I X 10"'on S'P"+'! A
&o, z ” 'o, 6As gate layer 15 with a thickness of 0.2 μm
Accomplish a skill. Next, mask with four resist 12 and ion implant the boron at 10"C at 100 to 1soKe'V.
tF-2 is implanted to isolate the transistor region 23.

Next, after removing the resist 22 on the transistor region 23, a 0.4 .mu.m thick layer of Gesten is deposited by spacing. This tungsten layer 16 serves to substantially lower the resistance of the gate layer 15, which is composed of P-type Ap (, 4G ao, 4A s ), which has low mobility and high resistance. It plays the role of a wiring layer in place of the A lo, a Gao, and 6 As layers in the insulated %1 region 13.

Next, after masking the gate region, the tungsten layer 16 is first selectively removed by plasma etching, and then by an iodine etchant, P mA IJ 0.4G+L,
), 6ASFi is selectively etched to form a gate.

By this method, an n-type a As active layer can be used that maintains the accuracy of MBE (FIG. 4).

Next, add 170=180 Si to the region that will become the source and drain.
Inject kOV-C1013Cnl-2 to make n-live form (
Figure 6). This II,1, gate layer 15 itself serves as a mask, resulting in so-called Hilfa lime implantation.

Next, the 5i07 film 4 was deposited and annealed at 800°C for 16 minutes, followed by a normal electrode process to form an AuGe/Au ohmic electrode 20. The HJFET can be completed by forming a Ti/Au wiring layer 210. Effects of the Invention The present invention provides an Ae
A metal layer formed on the gate layer 2 instead of the al-xAs layer plays the role of a gate wiring layer. As a result, there is no need to make the gate shape into a closed loop, resulting in a structure suitable for an LSI river H FET. The metal layer lowers the gate resistance, resulting in a HIFET with low gate resistance.

[Brief explanation of the drawing]

Figure 1 is a conventional HJ FET Nohira 1fii diagram,
Fig. 2 is a structural sectional view of f (JFET) according to the present invention;
Figures to Figure 6 show the manufacturing method of H and TFET according to the present invention: 4
This is a diagram showing 'J', Figures 3 and 5 are cross-sectional views, and Figure 4 is a sectional view.
FIG. 12...Undoped G? LA S buffer/layer, 13
... Separation region, 14 ... Source, drain region, 15 ... P type Aρ. , a G 2L0
．． 6A S gate layer, 16...Tungsten layer, 17...n1GaAs active layer, 18...
・Sin, film, 19-... interlayer insulating film, 21...
・T i/A u wiring layer, 2O-=-Au(, e/Au
Ohmic Den 4+640 Name of attorney: Toshio Nakao and 1 other person
1 Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] On the surface of a GaAs substrate of one conductivity type, a gate layer consisting of a '[xeal- Also, note that an element isolation region is formed at the periphery of the surface of the GaAs substrate! Heterojunction FET with 1+J characteristic.