JPS5999758A - Manufacture of complementary mis semiconductor device - Google Patents

Abstract

PURPOSE:To contrive improvement in the yield rate of production as well as to make uniform the electric characteristics of the titled semiconductor device by a method wherein a photolithographic process for formation of channel stopper is dispensed with. CONSTITUTION:An Si3N4 mask 3' is provided on the thermal oxide film 2 located on an N type Si substrate, and an SiO2 film 4 is deposited. A window is selectively provided on films 3 and 4, a B-ion is implanted, and a P-well 5 is formed by performing a heat treatment at approximately 1,200 deg.C. Then, a B-ion is implanted using the mask 3 located on the well 5, subsequently the SiO2 film 4' and the thermal oxide film 2 are removed by performing an etching, and a P-ion is implanted thereon. Then, a field oxide film 6 is formed by performing a thermal oxidation and, at the same time, P type and N type channel stoppers 7 and 8 are formed by activating the ion-implanted layer. Subsequently, the film 2 and 3' are removed, and a CMOS device is completed as described. According to this constitution, one photolithographic process can be reduced when compared with the conventional method, the manhours and the yield rate of the semiconductor device can be improved, and the positional relations between the well and the channel stopper can also be maintained constant, thereby enabling to make uniform the electric characteristics of the titled device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary MIS semiconductor device. □ [Technical background of □]: In a complementary MIS semiconductor device, a parasitic MO8) runnostar is formed using a field oxide film as a dirt insulating film. Therefore, in order to set the threshold voltage of such a raw MOS transistor to a predetermined value, an impurity region (hereinafter referred to as a channel concentration/mother region) having a predetermined impurity concentration □: is required under the field oxide film.・Needs to be completely formed.

・In the past, complementary MiS semiconductor devices have been manufactured, for example, by the following method.

First, for example, a thermal oxide film is formed on the surface of an N-type silicon substrate, and then a photorenost pattern is formed so as to cover the area other than the portion where the P-type well region is to be formed. Next, after all ions of P-type impurities are implanted into this entire photorenost ZF turn mask, the entire thermal oxide film on the portion where the well region is to be formed is removed by etching. Subsequently, after removing the photoresist pattern, heat treatment is performed in an oxidizing atmosphere to fully activate the ion implantation layer and form a P-type well region. The thermal oxide film is then removed from the entire surface. Subsequently, a buffer oxide film and a silicon nitride film are sequentially formed over the entire surface. Subsequently, the silicon nitride film corresponding to the area where the field oxide film is to be formed is selectively removed by etching to form a silicon nitride film pattern. Subsequently, a photoresist pattern is formed to cover the P-type well region, and the photoresist pattern is formed to cover the P-type well region. Using the silicon nitride film pattern on the substrate other than the pattern and well region as a mask, N-type impurity ions are implanted. Subsequently, after removing the photoresist pattern, a photoresist pattern is formed on the entire substrate other than the well region in a manner similar to that shown in FIG. Implant ions. Subsequently, after removing the photoresist pattern, thermal oxidation is performed using the silicon nitride film pattern as an oxidation-resistant mask to form a field oxide film and activate the ion implantation layer 8. A P-type channel stopper region is formed in the P-type well region, and an N-type channel stopper region is formed in the substrate other than the well region. Subsequently, after removing the silicon nitride film pattern and buffer oxide film by etching,
The entire complementary MIS semiconductor device is manufactured by forming dirt electrodes, a gate insulating film, source and drain regions, and wiring according to the usual process.

[Problems with background technology]

In the above-mentioned conventional manufacturing method, in order to form the P-type channel stopper region and the N-type channel stopper region, the photoresist method is used to form the P-type channel stopper region and the N-type channel stopper region, respectively. ion implantation is performed. Therefore, the overall effect of defects in the photorenost pattern is easy, and the yield is 9.
In addition to this, manufacturing costs will rise. Furthermore, due to mask misalignment, the positional relationship between regions of each element is not constant, resulting in variations in electrical characteristics. Further, in the above-described method, the surface of the P-type well region is oxidized by heat treatment in an oxidizing atmosphere when the entire P-type well region is formed. For this reason, when the thermal oxide film is completely removed, there is a difference in height between the surface of the P-type well region and the rest of the substrate surface, resulting in poor flatness.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and by reducing the photolithography process for forming the channel stopper region, it is possible to improve the yield 9 and reduce the cost, as well as to improve the electrical performance of each element. It is an object of the present invention to provide a method for manufacturing a complementary MIS semiconductor device that has uniform characteristics and can improve surface flatness.

[Summary of the invention]

The method for manufacturing a complementary MIS semiconductor device of the present invention first includes:
A thermal oxide film and a nitride film are all sequentially formed on the surface of a 14th electrode type semiconductor substrate, and the nitride film on the area where the field oxide film is to be formed is selectively etched away to form a nitride film pattern. A film, such as a CVD-5i02 film or a polycrystalline silicon film, is fully deposited by selectively etching the nitride film pattern. After selectively etching and removing the film on the part where the well region of the second conductivity type is to be formed to form a film pattern, 1, impurities of the second conductivity type are ion-implanted, and heat treatment is performed to form the second conductivity type. Form the well region of the mold. Subsequently, impurities of the second conductivity type are ion-implanted as a mask for the entire nitride film pattern on the film pattern and the first six well regions, and after etching and removing at least the nozzles of the film, the nitride film pattern is used as a mask. Impurity drmi of the first conductivity type is ion-implanted, and thermal oxidation is performed using the nitride film pattern as an oxidation-resistant mask to form a field oxide film and channel stocking regions of the first and second conductivity types therebelow. According to the method described above, the photo-etching process for forming the channel region is performed only once when forming the coating pattern9, whereas the conventional method also requires the photo-etching process once. It is possible to reduce the number of times, thereby improving yield and reducing costs. In addition, in the complementary MI8 semiconductor device to be manufactured, the positional relationship between the second conductivity type well region and the first and second conductivity type channel storage regions is always constant, so that the electrical characteristics can be made uniform. I can do it. Furthermore, since the surface is covered with the nitride film Nosetan during the formation of the second conductivity type well region, there are few oxidized stones, and finally the surface height difference is eliminated, resulting in improved flatness.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to all of FIGS. 1 to 6.

First, a thermal oxide film 2 with a thickness of about 1000× and a silicon nitride film 3 with a thickness of about 2000× are sequentially formed on the surface of an N-type silicon substrate 1 (as shown in FIG. 1).

After selectively etching and removing the silicon nitride film 3 on the area where the field oxide film is to be formed to form a silicon nitride film pattern 3', a CVD-5i02 film 4 is deposited on the entire surface. (Illustrated).

Next, using the photorenost nozzle (not shown) as a mask, the CVD-Si is removed on the portion where the P-type well region is to be formed.
After selectively etching and removing the O2 film 4 and the thermal oxide film 2 below it and forming the CVD-5j02 film 4' shape 1a, B was quickly etched using the photorenost pattern described above as a mask. Energy 1. Ion implantation was carried out under the conditions of O0keV, dose amount 4.0', X: 1.1012cm''.Subsequently, after completely removing the photorenost pattern, thermal oxidation treatment was performed at approximately 1200°C to increase the depth of 4.
A P-type well region 5 of ~8 μm was formed.

At this time, the P-type well region 5 is formed by being diffused into a long length due to the lateral force and rotation (as shown in FIG. 3).

Next, the CVD-'5to2 film pattern 4' and P
Using the silicon nitride film pattern 3' on the mold well region 5 as a mask, the ion-implanted layer was then deposited on the CVD-5i02 film under the conditions of an acceleration energy of 40 keV s and a dose of 8.0 x 10 t:m. 4' and the silicon nitride film 2 not covered with the silicon nitride film/gutter 3' are removed by etching.
With Lean 3 as a mask, P+ is the speed energy, -40
Ion implantation was carried out under the conditions of keV and a dose of 2'x1012ffi-2 (as shown in FIG. 5).

Next, the silicon nitride film pattern 3' is thermally oxidized as an oxidation-resistant mask to reduce the thickness to about 0. o1□07(-
#l'wii film 6 □ Uiyu. . At the same time, the boron ion implantation layer and the phosphorus ion implantation layer are activated to form a P-type channel stopper region 7 and an N-type channel stopper region 7 under the field oxide film 6.
-21 channel stopper region 8 was completely formed (as shown in FIG. 6).

Thereafter, the silicon nitride film/mother turn 3' and the thermal oxide film 2 thereunder were sequentially removed by etching, and then a thermal oxide film to become a dirt oxide film was formed on the surface of the element region. Subsequently, a polycrystalline silicon film was deposited on the entire surface and then patterned to form a dirt electrode, and using the dirt electrode as a mask, the thermal oxide film was etched away to form a gate oxide film. Subsequently, N+ type north and drain regions and final type source and drain regions were successively formed. Continuing □,
After depositing a CVD-6'i02 film on the entire surface, a contact hole) b'f was opened. Subsequently, an AA film was deposited on the entire surface and then patterned to completely form the wiring. Next, a passivation film and a hole window for bonding were formed, and CMO8 was manufactured. □ However, according to the above method, the following effects can be obtained.

(1) In the step shown in FIG. 3, the CVD-SiO2 film 4 is patterned by photolithography to form the P-type well region 5, and the CVD-,5i02 film is turned 4'.
After forming the silicon, ion implantation of lron to form the P-type channel stopper region in the step □ shown in Fig. 4 is performed. Using the film pattern 3' as a □ mask, ion implantation of phosphorus for forming an N-type channel stopper region in the step shown in FIG. 5 is carried out using the silicon nitride film notation 3' as a mask. Therefore, compared to the traditional method, the photo-etching process is
Because it is less affected by defects in Photorenost Noreen, it is possible to improve the yield9, and
Cost reduction and manufacturing time can be reduced.

(11) As mentioned in (1), P-type channel stock A
? Since there is no photolithography process between the poron ion implantation process for forming the region and the phosphorus ion implantation process for forming the N-type channel stopper region, there is no problem of mask misalignment, and the manufacturing process is easy. In the CVD 3, a P-type well region 5, a P~-type chall stopper region 7
The positional relationship of the N-type channel stock/mother region 8 is always constant. Therefore, electrical customization such as withstand voltage between each region becomes uniform without variation among ICs.

010 Since the P-type well region 5 formed in the step shown in FIG. 3 is diffused in the horizontal direction, the N-type channel stopper region 8 is always in the P-type well region 5 as shown in FIG.
It was formed with 9 people in it.

Therefore, even if the N-type channel stopper region 8 hederon is diffused from the P-type channel stopper region 7 in the later thermal process, the source, domain region and P-type well of the P-type channel stopper region 7 formed in the later step are an N-type channel strike between region 5;

The space area 8 can be secured. Therefore, compared to CVD3 manufactured by the conventional method, even if the distance tW between the P-type source and drain regions and the P-type well region is the same, CVD8 manufactured by the conventional method has a higher distance between the two regions. The withstand pressure increases.

(When forming the pa mirael region 5 in the step shown in FIG. 3, most of the surface is covered with the silicon nitride film pattern 3', so there is little oxidation in the part, and the surface height and height are Since the difference is reduced, flatness is better compared to conventional methods.

Therefore, it becomes easier to process in subsequent steps, and an improvement in yield can be expected, which is advantageous for coverage of wires, passivation films, and the like.

In addition, the above real 2I! In row Ii, a CVD-5i02 film 4 was deposited as a film having selective etching properties with respect to the silicon nitride film pattern 3' in the step shown in FIG.
This coating may be, for example, a polycrystalline silicon film. In this case, only the polycrystalline silicon film pattern is completely etched away in the step shown in FIG. In the step shown in FIG. 6, thermal oxidation may be performed for the first time with the thermal oxide film 2 remaining.

〔Effect of the invention〕

As detailed above, according to the method of manufacturing a complementary MIS semiconductor device of the present invention, it is possible to improve the yield and reduce the cost, and also to achieve remarkable effects such as making the electrical characteristics of each element uniform. .

[Brief explanation of drawings]

1 to 6 are cross-sectional views showing a method of manufacturing CVD 8 in an embodiment of the present invention. 1...N-type silicon substrate, 2...thermal oxide film, 3...
・Noricon Hokame film, 3'...Silico/Yaba film pattern, 4 ・-CVD -SiO2 film, 4'・=CVD
-5i02 film pattern, 5... P-type well region, 6...
. . . Field oxide film, 7 .

Claims (1)

[Claims] After sequentially forming a thermal oxide film and a nitride film on the surface of a first conductivity type semiconductor substrate, and selectively etching and removing the nitride film on a portion where a field oxide film is to be formed, a nitride film/gutter is formed. , a step of depositing a film having selective etching properties with respect to the nitride film pattern over the entire surface, and selectively etching away the film on the portion where the 2' conductivity type well region is to be formed to form a film pattern. After that, a step of ion-implanting impurities of a second conductivity type and performing heat treatment to form a well region of a second conductivity type; a step of implanting all ions of impurities of a second conductivity type; and a step of ion-implanting impurities of a first conductivity type using the nitrided PIX'l'-n as a mask after etching away at least the BA7'l'turn; □ A complementary type characterized by comprising the step of performing thermal oxidation on the nitride film pattern as well as an oxidation-resistant mask to form a field oxide film and Tejanel storage regions of the first and second conductivity types thereunder. A method for manufacturing an MIS semiconductor device.