JPS5999541A - Arithmetical logical operation circuit - Google Patents

Abstract

PURPOSE:To reduce the number of constituent transistors (TR) of a fast ALU using CMOSTRs and simplify the constitution, and to suppress the occupation area on a chip in case of IC implementation. CONSTITUTION:Both NMOSTRs 4-1 and 4-4 are both in the off state at the beginning of a sampling period T2, so there is no danger of erroneous discharging of charge accumulated on a carry/borrow signal line in the transition from a precharging period T1 to the sampling period T2. Further, the NMOSTRs 4-1 and 4-4 are permitted to change only from an off state to an on state, so they never turn off after the carry/borrow signal line 4-2 is discharged temporarily. Therefore, charge on the carry/borrow signal line 4-2 are held in safety or discharged in a short time, so secure and fast operation is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to an arithmetic logic circuit (hereinafter referred to as ALU), and particularly to a high-speed ALU using (JiO8 (complementary MO8)) transistors.

(Prior Art) CMO8 has the major features of extremely low power consumption operation and wide noise margin. Commercial for application to microcomputers
The usefulness of O8 has been widely recognized, and the demand for low cost and high speed operation has increased, and even CMO8 is an arithmetic logic circuit that can operate at high speed without complicating the circuit. desired.

An example of a high-speed ALU conventionally used in an NMO8 microcomputer is shown in FIG. This circuit consists of NMO
8) Ranister group 1-1 to 1-3, NMO8) Run raster 1-9, 1-10, Impark 1-11, 1-1
2, 1-13, and 1-14EX-ORI-15, respectively, and the calculation control signal OPO
The result Rn and the carry/debit signal Cn to the next digit are generated from the operand signal An, the operand signal Bn, and the carry/debit signal Cn-1 based on the combination of OF2.

The high-speed ALU circuit shown in Fig. 1 decodes the combination of the operand signal An and the operand signal Bn using the NMO8 transistor groups 1-1 to 1-8, and performs the calculation using the NMO8 transistor groups 1-1 to 1-4. Control signals OP4 to 0P71
NMO8) Select any one of the arithmetic control signals OPO to 0P3t in transistor groups 1-5 to 1-8, and set the carry/borrow signal level and It has a structure that controls propagation. therefore,
NMO based on the combination of operation control signals OPO to OF2 and operand signal An and operation number signal Bn8) Detailed 0N10FF status of transistor groups 1-1 to 1-8 is correctly grasped, and only one of each is selected. Any logical operation result can be obtained by arbitrarily setting the level of the operation control signal.

Table 1 shows the operation control signals OPO to OF2 during addition and subtraction, the operand signal An, the operation signal Bn, the carry/borrow signal Cn-1, the operation result Rn, and the carry/digit to the next digit. A truth table of the debt signal Cn is shown as an example. Similarly, logical operations such as AND, OR, and EX-OR are also possible by setting the operation control signals OPO to OF2.

Table 1 (subtraction) By the way, in general, from NMO8 transistor group 1-1 to 1
If the NMO8) transistor in -8 is made into a 0MO8 structure, as shown in Figure 2, NMO8) transistor a and PMO
The circuit configuration uses 8 transistors b as bare and inputs a positive logic signal and a negative logic signal to each gate.

Therefore, if the ALU'f:,0MO8 structure shown in FIG. 1 is used, the circuit configuration will be as shown in FIG. 3. However, this circuit configuration requires a large number of NMO8 and PMO8 transistors, and the mutual wiring and arrangement of each transistor becomes extremely complicated. Therefore, when integrated into an IC, the area occupied on the chip inevitably becomes large, which is a major drawback and is not practical.

(Object of the Invention) The present invention has been made in view of the above circumstances, and uses CMO8) transistors, which have a simple configuration with a small number of transistors, and can minimize the area occupied on a chip when integrated into an IC. The aim is to provide a high-speed ALU.

(Structure of the Invention) A predetermined combination of first logic circuit signals that outputs a signal that prohibits the propagation of the carry/7-digit borrow signal with the operation control signal and the carry/digit respectively with the operation control signal. A first operation control circuit that allows the propagation of the borrow signal, a second operation control circuit that inverts the value of the carry 7-digit borrow signal, and an output of the first logic circuit and the carry/digit borrow signal. and a third logic circuit that obtains a calculation result from the signal.

(Explanation of Examples) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the operand signal An and the operand signal Bn are used in the state of the operation control signals from OPO to OF2.

The operation to be executed between the carry 7-digit borrow signal co-1 is specified, and the operation result Rn and the carry 7-digit borrow signal Cn generated by the operation are generated. In addition, this carry/digit borrow signal C
n becomes a carry 7-digit borrow signal Cn-1 in the calculation of the next digit. Table 2 shows a truth table representing the operation of this embodiment in addition and subtraction.

Table 2 (subtraction) Next, the role of each transistor will be explained.

8MO8 transistor 4-1 is carry/digit borrow signal gland 4
-Control the propagation of the signal on 2. The PMOS transistor 4-3 supplies charge onto the carry 7-digit borrow signal line 4-2, and its source side is connected to the power supply Vcc. 8MO8
) The transistor 4-4 discharges the charge accumulated on the carry/borrow signal line 4-2, and its source side is connected to GND (ground). The 8MO8 transistor 4-5 discharges the charge accumulated in the capacitor 4-6, and the 8MO8 transistor 4-7 discharges the charge accumulated in the capacitor 4-8, and their sources are connected to GND. 2MO8)
The transistor group 4-9 is an operand signal An and an operand signal B.
2MO8) Together with the transistor group 4-10, the connection relationship between OF2 and the capacitor 4-6 is controlled by the operation control signal OPO.

The 2MO8 transistor group 4-11 receives the operand signal An.
2MO8) together with the transistor group 4-12, the arithmetic control signal OP4°OF2 and the capacitor 4.
-Controls the connection relationship with 8. Operation control signals OPO to OF2 specify the type of operation to be executed, and as shown in Table 2, during addition, OPO, OPI, OF2, O
F2, OF2, OF2 are respectively 0, 1, 1, 0,
Set to 0.1, and when subtracting, 1, 0, 0, 1, 1.0
Set to .

The operation control signal Cout is a control signal for controlling one arithmetic circuit, and is a control signal for controlling the 2MO8 transistor groups 4-10, 4-12 and 8.
Connected to the gates of MO8 transistors 4-5 and 4-7,
The signal via the inverter 4-13 is connected to the gate of the 2MO8) transistor 4-3. EX-OR4-14
is to calculate the result Rn from the potential of the capacitor 4-6 and the carry/borrow signal Cn-1.

Next, the operation will be explained with reference to the timing diagram shown in FIG.

One operation cycle consists of a precharge period T1 and a sample period T2.

Of these, during the period T2, the arithmetic control signal OPO to OF
2 maintains a predetermined value and the operand signal An and the operand signal B
n also does not change. During the precharge period of T1, the operation control signal Cout becomes high level, turns off the 2MO8 transistor group 4-10, 4-12, and turns off the 8MO8 transistor group 4-10.
Sister 4-5.

Turn on 4-7. As a result, the capacity is 4-6゜4-
The charges accumulated in 8 MO8) transistor 4-
5. Discharged via 4-7. Capacity 4-6, 4-8
Since the potentials of both become the GND level, the transistors 4-1 and 4-1 and 4-4 become in the OFI'' state, respectively.

T1 precharge period is 2MO8 transistor 4-3
A low level is input to the gate of 2MO8) through the inverter 4-13, and this 2MO8) transistor 43 is turned on. As already explained, 8MO8 transistor 4-4
is in the OFF state, charge is supplied to the carry/borrow signal line 4-2 via the 2MO8 transistor 4-3, and this potential becomes the Vcc level. Further, since the 8MO8) transistor 4-1 is also in the OFF state, the carry 7-digit borrow signal Cn-x from the previous digit is cut off by the 8MO8 transistor 4-1. In other words, the carry/borrow signal line 4-2 goes to the Vcc level during the precharge period of Tz, and at the same time each digit is cut off.

During the sampling period T2, the operation control signal Cout is at a low level.PMO8 transistor group 4-10.4-1
2 to ON state 2MO8) transistor 4-3 and NMO8
) Turn off transistors 4-5 and 4-7. T
In the sample period of 2, the calculation control signal OPO to OF2
Since the operand signal An and the operand signal Bn have already maintained a constant state, 2MO8) transistor group 4
The ON and OFF states of -9°4-11 are also determined in the same way. The potential of the capacitor 4-6 after moving to the sampling period of T2 is 2MO8) when the GND level is maintained based on the ON 10'FF state of the transistor group 4-9, the level of the operation control signal OPO to OF2, and the case where the OPO PMOS transistor group 4-9 from one of the operation control signals of OF2.
Since charge is supplied to the capacitor 4-6 through Vcc
It may rise to the level. After the potential of the capacitor 4-8 similarly moves to the sampling period T2, the 0N10FF state of the 2MO8 transistor 4-11 and the operation control signal OP4
, 0P50 level may be maintained at the GND level or may be raised to the Vcc level. Note that the arithmetic control signals OPO to OF2, the operand signal An, and the operand signal Bn
is constant during the period T2, so there is no danger that the potential of the capacitor 4-6°4-8 once rises to the VCC level and then returns to the GND level.

If capacitors 4-6 maintain the GND level during the T2 period, N
MO8) The carry/borrow signal Cn-1 from the previous digit is cut off while the transistor 4-1 remains in the OFF state. On the other hand, if the capacitor 4-6 changes to the VCC level during the T2 period, NMO8l-transistor 4-1 turns ON, and the carry 7 digit borrow signal Cn-1 from the previous digit is the carry 7 of the next digit. In conjunction with the digit borrow signal Cn, a carry/borrow signal is propagated on the carry 7-digit borrow signal line 4-2.

If capacitors 4-8 maintain the GND level during the period of T2,
NMO8) The transistor 4-4 maintains the OFF state.

When the capacitor 4-8 changes to the Vcc level during the period T2, the NMO8 transistor 4-4 is turned on and the charge accumulated on the 7-digit carry signal line 4-2 is discharged and its potential decreases. to GND level.

That is, in the sample period T2, the potential on the carry/borrow signal line 4-2 is determined based on the 0N10FF states of the NMO8 transistors 4-1 and 4-4.
After the carry 7-digit borrow signal Cn-1 on the digit borrow signal line 4-2 is determined, the calculation result Rn of that digit is determined by EX-OR4-14.
get.

In particular, NMO8) transistors 4-1 and 4-4 are both in the OFF state at the beginning of the sampling period T2, so at the moment of transition from the precharge period T1 to the sampling period T2, the carry/
There is no risk of erroneously discharging the charges accumulated on the debit signal line 4-2. Also, the direction of change of NMO8) transistors 4-1 and 4-4 is from OFF to ON.
Since the NMO transistor 4-1 or 4-4 is in the OFF state again after the charge on the carry/borrow signal line 4-2 is once discharged, there is no risk that the transistor 4-1 or 4-4 will be turned off again. Therefore, the charge on the carry 7-digit borrow signal line 4-2 is extremely safely held or discharged in a short time, ensuring reliable and high-speed operation.

In the circuit shown in FIG. 4, the capacitors 4-6, 4-8 are not provided as any special capacitors, and the gate capacitances of the capacitors 4-6, 4-8 can actually be used with the same transistors as the other transistors.

Also, by setting the calculation control signal OPO to OF2,
It is clear that logical operations such as , OR, EX, and OR are possible.

This embodiment performs exactly the same arithmetic operation as can be seen from the comparison of truth tables shown in Tables 1 and 2. Moreover, when comparing the number of components with the conventional example of the CMO8 structure shown in FIG. 3, the circuit in FIG. 3 has 34 transistors and 3 inverters.

For one EX-OR circuit, in the circuit of Fig. 4,
25 transistors (as mentioned above, capacitors are counted as transistors) 3 inverters, E)'-OR circuit 1
As a result, the number of transistors is reduced by nine. That is, according to this embodiment, (1) the number of transistors to be formed can be kept as small as possible and the conventional AL
It is possible to obtain an ALU that is capable of high-speed operation just like U.

Although the present invention has been described above with reference to an embodiment shown in FIG. 4, the present invention is not limited to this embodiment in any way, and can be similarly applied to cases where the number of arithmetic control signals is larger, for example. Needless to say.

(Effects of the Invention) As explained above in detail, according to the present invention, by adopting the above-mentioned structure, the number of constituent transistors is small and the structure is simple, and the chip area is minimized when integrated circuit is made using CMO8S structure. This has the effect of providing a high-speed ALU where possible. In particular, the practical effects on high-speed CMOS microcomputers are very high.

[Brief explanation of drawings]

Figure 1 shows a conventional example of high-speed A using NMO8 transistors.
The circuit diagram of LU, Figure 2 is the basic circuit diagram in CMO8 structure, Figure 3 is the N? A circuit diagram of an ALU when ~10S transistors are replaced with CMO8) transistors, FIG. 4 is a circuit diagram representing an embodiment of the present invention, and FIG. 5 is a timing diagram showing the operation of the circuit of FIG. 4. . 1-1, 1-2, 1-3, ]-4, 1-5,1
~6.1-7.1-8...NMO8) transistor group, 1-9.1-10, 4-1, 4-4. t-5
゜4-7...NMO8) transistor, 4-9.
4-10, 4-11, 4-12...i...2MO
8 transistors @L 4-3...2MO8)
Ransistor, 1-11.1-12.1-13.1-14
．． 4-13...Inverter, 1-15.4-1
4...EX-OR. 4-2...7-digit carry signal error, 4-6.4
- Death... Capacity, An... Operand signal,
Bn... Arithmetic number signal, 0Po-OF2...
...Arithmetic control signal, Cout...Operation control signal, Cn, Cn-z...Carry/borrow signal.

Claims (1)

[Claims] a first logic circuit to which the operand signal and the operand signal are supplied and which outputs a signal for inhibiting the propagation of the carry/digit operation control signal, respectively; a first operation control circuit that allows propagation of the carry/borrow signal, a second operation control circuit that inverts the value of the carry/borrow signal, and an output of the first logic circuit; A third method for obtaining a calculation result from the carry/borrow signal.
An arithmetic and logic operation circuit comprising: a logic circuit;