JPH04317212A - Latch circuit and flip-flop circuit appropriate for low voltage operation and microprocessor using them - Google Patents

Abstract

PURPOSE:To provide a latch circuit and a flip-flop circuit using a BiCMOS which is appropriate for a high speed operation at low power supply voltage and which has small power consumption and a microprocessor using them. CONSTITUTION:An npn transistor Q1 between a power supply Vcc and an output terminal DO and an npn transistor Q2 between an output terminal DO and a ground GND are provided. A pMOS MP1 and 2 between the Vcc and a base N1 of the Q1, a pM0S MP5 between the Vcc and a base N3 of the Q2, and nMOS MN 3 and 4, inverters MP8 and MN9 inputting an output signal and clocked inverters MP6, MP7, MN7 and MN8 between a gate N2 of the MP5 and the GND are provided. The gate of the MPI and the gate of the MN4 are connected, an input signal DI is supplied to the connection point, and control signals CK and CKN are supplied to the gates of the MP2 and the MN3.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to high-speed, low-power consumption latch circuits and flip-flop circuits that combine CMOS and bipolar transistors, as well as microprocessors using the same, and in particular to microprocessors using the same. It is suitable for integrated circuits using a power supply voltage of 4 V or less.

0002

[Prior art] Latch circuits and flip-flop circuits are
It is a basic component of a computer. Recently, advances in integrated circuit technology have dramatically increased the speed of computer machine cycles, and as a result, extremely high-speed latch circuits or flip-flop circuits have become necessary.

As a flip-flop circuit having a CMOS structure suitable for high-speed operation, T. Tokumaruet a
IEEE JOURNAL OF SOLID
-STATE CIRCUITS, Vol. 24,N
o. 4, August 1989, pp. 938-94
This has been previously discussed in 3.

On the other hand, bipolar transistors and CMOS
A high-speed, low-power B that combines on the same chip
iCMOS logic circuits are attracting attention as a means of increasing the speed of integrated circuits, and are currently rapidly expanding their range of applications. As a conventional BiCMOS combinational logic circuit, H.
Momose et al.
N DEVICES MEETING 1987, pp.
．． 838-840. This H. M
The conventional Bi disclosed in the document of omose et al.
FIG. 13 shows a two-input NAND circuit using CMOS.

[0005]

[Problem to be solved by the invention]T. Tokumaru
FIG. 7 constructed according to the technique disclosed in the document of et al.
In the flip-flop circuit using the CMOS circuit shown in
Application to high-speed microprocessors has the problem of slow operating speed. This problem becomes particularly serious when the output load capacity is large.

On the other hand, BiCMOS technology, which forms bipolar transistors on-chip, is attracting attention as a technology that achieves high-speed performance while taking advantage of the high degree of integration of CMOS, and it is expected that flip-flop circuits will also be faster using BiCMOS technology. be done. However, the CMOS in Figure 7
The circuit of FIG. 8, in which the circuit is simply replaced with the conventional BiCMOS circuit shown in FIG. 13, has a problem in that the through current is large for the following reason. This will be explained below.

That is, in the circuit of FIG. 8, when the input DI is high,
Consider the case where CK is high, CKN is low, and the output DO is high. At this time, N21 is charged by MP28 and MP29 and is high. When the clock signals CK0 and CK change from high to low (CKN changes from low to high), the MNs 29 and 30 are turned on. At this time, N22 becomes low, so Q9 is turned off. Also, N23 is MN3
1 and 32, Q10 is turned on. Therefore, DO is discharged through Q10 and changes from high to low. However, at this time, MP28, 29, M
Since N34 and 35 are in the off state, N21 remains high. Therefore, when DO goes low, Q11 turns on. Therefore, a large amount of through current flows from the power supply voltage Vcc through Q11 and Q10. For this reason, there are problems in that not only does the change of DO from high to low become slow, but power consumption increases.

Furthermore, the circuit shown in FIG. 8 has a problem in that the operating speed becomes extremely slow when the power supply voltage Vcc is 4V or lower. As shown in Figure 8, the DI is similar to BiC
If it is driven by a MOS circuit, the high level of DI will be Vcc-VBE. Here, Vcc is the power supply voltage, and VBE is the base-emitter voltage of the bipolar transistor in the on state. Further, in order for bipolar transistor Q10 to operate, node N23 needs to be at a potential higher than the ground potential by VBE. Therefore, in the operating state, only a maximum voltage of Vcc-2VBE is applied between the gate and source of MN32. Since VBE is approximately 1V, Vcc-2VBE is approximately Vc
c-2(V). FIG. 9(a) shows the gate-source voltage dependence of the drain current of a MOSFET. As is clear from this figure, the drain current of MN32 in the circuit of FIG. 8 is significantly reduced due to the influence of VBE, and the circuit operating speed is also slowed down. When the power supply voltage decreases, VBE becomes relatively large with respect to Vcc, so the effect of this decrease in drain current also becomes significant. Therefore, Figure 8
In this circuit, the operating speed becomes slow at low voltage. Conventionally, BiCMOS logic circuits operated at a standard power supply voltage of 5V, but now that it has become possible to fabricate integrated circuits with gate lengths of 0.5 microns or less, it is strongly recommended that they operate at a low power supply voltage of 4V or less. It has become desired. This is to prevent device deterioration due to hot carriers in the MOSFET and to reduce power consumption. It is impossible for the circuit shown in FIG. 8 to satisfy this requirement for low power supply voltage operation, and this has become a major barrier to increasing the speed of data processing devices such as microprocessors. This means that if a new high-speed flip-flop circuit that can operate at low voltages is invented, its industrial value will be extremely high. Therefore, it is an object of the present invention to
The object of the present invention is to provide a flip-flop circuit using S technology that is capable of high speed, low power consumption, and low voltage operation.

On the other hand, RISC (Reduced Instruction Set Computer) processors have recently attracted attention as high-speed CPUs for engineering workstations. RISC
In order to shorten the cycle time and increase speed by simplifying the instruction system, reducing the cycle time has become an important issue. Conventionally, registers for microprocessors have often used two-phase clocks. When a two-phase clock is used, a through-type latch can be used to hold data, so the flip-flop itself is fast. This through-type latch allows input data to pass through to the output when the clock is high or low.
This type of latch holds the output information without transmitting the input data to the output when the clock is on the other side, and is approximately twice as fast as the master-slave type. However, 2
In order to avoid overlap between the phase clocks, a waiting time is required between the two clocks, making it unsuitable for achieving high speed machine cycles. This is because when there is an overlap, the data advances by one step. On the other hand, in the case of a one-phase clock, this waiting time is unnecessary, so although the clock can be made faster, a master-slave type flip-flop is required, which poses a problem in that the delay time of the register itself increases. For this reason, with conventional techniques, it is difficult to create a register configuration suitable for ultra-high-speed RISC processors.

It is therefore another object of the present invention to provide a flip-flop suitable for high speed RISC processors operating with short cycle times.

[0011]

[Means for Solving the Problems] In order to achieve the above object, a latch circuit according to an embodiment of the present invention has a collector-emitter path between a first operating potential point (Vcc) and an output terminal (DO). a first npn transistor (Q1) connected to the above, and a second npn transistor (Q2) whose collector-emitter path is connected between the output terminal (DO) and a second operating potential point (GND). and first and second p-channel insulated gate FETs (MP
1, 2), and a third transistor whose source-drain path is connected to the current path between the first operating potential point (Vcc) and the base (N3) of the second npn transistor (Q2).
A source-drain path is provided between the p-channel insulated gate FET (MP5), the gate (N2) of the third p-channel insulated gate FET (MP5), and the second operating potential point (GND). First and second n-channel insulated gate FETs (MN3, 4) connected in series, and an inverter (M
P8, MN9) and the above inverter (MP8, MN9)
clocked inverters (MP6, MP7, MN7, MN8) which input the output signal (N4) of the clocked inverters (MP6, MP7, MN7).
, MN8) is connected to the above output terminal (DO),
The above clocked inverters (MP6, MP7, MN7,
MN8) connects the insulated gate F between the output terminal (DO) and the first operating potential point (Vcc) or the second operating potential point (GND) by control signals (CK, CKN).
ET (MP6, 7, MN7, 8), and the first p-channel insulated gate FET (MP1
) and the first n-channel insulated gate FET (
The first input signal (DI) is supplied to this connection point, and the gate of the second p-channel insulated gate FET (MP2) and the second n-channel insulated gate FET (MN4) are connected to the gate of the second p-channel insulated gate FET (MP2). The control signal (CK) and its opposite phase signal (CKN) are supplied to the gate of the MN3) (see FIG. 1).

Furthermore, the master-slave type flip-flop according to the preferred embodiment of the present invention has an input signal (N9
) and a control signal (CK, CKN) are supplied to the first latch circuit (L1), and the output terminal (N10) of the first latch circuit (L1) is used as an input signal, and the first latch circuit ( (See FIG. 4).

The latch circuit with logic function according to the preferred embodiment of the present invention also includes a first npn whose collector-emitter path is connected between the first operating potential point (Vcc) and the output terminal (N15). A transistor (Q13) and a pull-down element (Q14, MP35, M
N45), the first operating potential point (Vcc) and the first
A first p-channel insulated gate FET (MP34) whose source/drain path was connected to the current path between the base (N12) of the npn transistor (Q13) and the source/drain path was connected in series with the first p-channel insulated gate FET (MP34). A first switching circuit (MP
30-33) and the first npn transistor (Q1
3) base (N12) and the second operating potential point (GN
A first n-channel insulated gate FET (MN39) whose source/drain path is connected to the current path between the current path and the second n-channel insulated gate FET (MN39) whose source/drain path is connected in series with A switching circuit (MN40-43), an inverter (I9) that responds to the signal of the output terminal (N15) as input, and a clocked inverter (CI3) that receives the output signal of the inverter (I9) as input. The output of the clocked inverter (CI3) is connected to the output terminal (N15), and the clocked inverter (CI3) is connected to the output terminal (N15) by the control signal (CK, CKN).
and the first operating potential point (Vcc) or the second operating potential point (GND) through an insulated gate FET, and the clocked inverter (CI3)
uses an insulated gate FET to charge and discharge the output, and when the first switching circuit (MP30-33) is turned on, the second switching circuit (MN40) is turned on.
-43) is configured to be turned off, and when the first switching circuit (MP30-33) is turned off,
The second switching circuit (MN40-43) is characterized in that it is configured to be turned on (see FIG. 11).

[0014]

Operation: In the exemplary embodiment of the invention (FIG. 1), the base (N1) of the first npn bipolar transistor (Q1) for charging the output node is a p-channel MOSFET.
Driven by the drain output of (MP1,2), the base of the second npn bipolar transistor (Q2) for output node discharge is also a p-channel MOSFET (MP5
) is driven by the drain output of the On the other hand, when the power supply voltage (Vcc) decreases, n
The voltage applied between the drain and source of the p-channel MOSFET (MP5) is reduced due to the influence of the pn bipolar transistor (Q2). However, as shown in FIG. 9(b), even if the drain-source voltage decreases by VBE, the drain current of the MOSFET does not change much. Thus, exemplary embodiments of the present invention operate at high speed even at reduced power supply voltages. Therefore, conventional BiC
Even with power supply voltages below 4V, which are inoperable with MOS gate circuits, representative embodiments of the present invention can operate at high speed, thus significantly reducing power consumption.

Furthermore, when the bipolar transistor (Q2) discharges the output node (DO), the charging p-channel MOSFETs (MPN6, 7) are turned on, but the bipolar transistor (Q2) is
Since the current driving capability is significantly larger than that of P6, P7), the discharge operation will not be slowed down due to the current generated by this p-channel MOSFET. Therefore, the simple BiC shown in FIG.
It is possible to avoid the problem of deterioration of operating speed or large power consumption due to large through current, as in MOS-configured latches.

In another typical embodiment of the present invention (FIG. 4), a master-slave type flip-flop that can operate with a single-phase clock can be configured, making it suitable for operation in high-speed machine cycles, and with a high output speed. It can be driven at high speed using bipolar transistors and can be charged and discharged in a short time even under conditions of heavy load capacity, making it suitable for high-speed machine cycle operation. Therefore, it is possible to achieve high-speed RISC processors that require ultra-high-speed machine cycle operations.

In an exemplary embodiment of the invention (FIG. 1):
Although the source of the P-channel MOSFET (MP5) is connected to the first operating potential point (Vcc) via the emitter-collector path of the bipolar transistor (Q1), the present invention is not limited to this connection. For example, P
The source of the channel MOSFET (MP5) can be connected to the first operating potential point (Vcc) via a suitable voltage drop element. However, P-channel MOSFET (MP5
) is directly connected to the first operating potential point (Vcc), the bipolar transistor (Q2) will be saturated in the ON state of the bipolar transistor (Q2). Those skilled in the art will readily understand that the source of the P-channel MOSFET (MP5) should be connected to the first operating potential point (Vcc) via a voltage drop element that produces a voltage drop sufficient to prevent this saturation. Dew. Other objects and features of the present invention will become clear from the following examples.

[0018]

EXAMPLES Example 1 An example of the present invention will be described below with reference to FIG. FIG. 1 shows a circuit diagram of a latch circuit of the present invention. MP1-8 are p-channel MOSFETs, MN1-10 are n-channel MOSs
FET, Q1, 2 are npn bipolar transistors, I
1-I2 is a CMOS inverter.

First, the logical operation of this embodiment will be explained. When the clock signal CK is low, MP2, MN1,
Since MP4 and MN3 are in the on state, nodes N1 and N2
An inverted signal of the input DI is output. On the other hand, MP7,
Since MN7 is turned off, MP6-8 and MN7-9 do not affect the output. When N1, N2, DO are high, bipolar transistor Q1 is off, MP5 is off,
Since MN5 is turned on, N3 becomes low level and Q
2 is off. Therefore, DO is kept at a high level. When N1 and N2 are high and DO is low, bipolar transistor Q1 turns on and charges DO. Also,
Since MP5 is off and MN5 is on, N3 is at low level and Q2 is off. Therefore, DO changes from low to high. When N1, N2, and DO are low, the bipolar transistor (Q1) is off, MP5 is off, MN5 is off, and MN6 is on. Since N3 is at low level, Q2 is off. Therefore, DO is kept low. When N1 and N2 are low and DO is high, the bipolar transistor (Q1) is off and M
Since P5 is on and MN5 is off, N3 is charged by MP5 and Q2 is turned on. Therefore, DO changes from high to low. From the above, when N1 and N2 are high, DO is also high, and when N1 and N2 are low, DO is also low. Therefore, when CK is low, an inverted signal of DI is output to DO.

Next, when CK is high, MP2, MN1,
Since MP4 and MN3 are in the off state, N1 and N2 are neither charged nor discharged, and therefore maintain that state. Also, at this time, MP7 and MN7 are in the on state, and MP6, 7,
The circuit consisting of MN7 and MN8 outputs the inverted signal of N4 to DO. Therefore, when DO is high, it remains high, and when DO is low, it remains low. C.K.
Suppose that when is high and DO is high, DO becomes a level slightly lower than high due to noise. At this time, unless the level of DO drops below the logic threshold voltage of the CMOS inverters of MP8 and MP9, N4 is kept at the ground level, so MP6
, 7, DO is charged and returns to the high level (power supply voltage level). Also, if noise enters N2 and the voltage becomes lower than Vcc-VT (VT is the threshold voltage of MN10), MN10 is turned on and N2
Charge to Vcc-VT. Similarly, when DO is held low and noise causes DO to go from low to a slightly higher level, the level will recover. As described above, when CK is high, the output potential is held statically.

From the above, it can be seen that the present embodiment functions as an inverter when CK is low, and maintains the output level when CK is high. That is, it operates as a latch circuit. In this circuit, current only flows transiently when the input changes, and only leakage current flows at other times. Therefore, power consumption is as low as CMOS. Output D
Since the node O is driven by bipolar transistors Q1 and Q2, this circuit operates at high speed even if a large capacitive load is connected to the output DO. Next, the transient operation of this embodiment will be explained using a pull-down operation as an example. D.I.
Consider the case where CK is high, DO is high, and CK changes from high to low. When CK is high, the output DO is kept at high level, and N1 and N2 are also at high level. C
When K changes from high to low, via MN3 and 4,
The charge on N2 is discharged, and N2 becomes low level. Subsequently, MP5 is turned on, N3 is charged, and Q2 is turned on. Therefore, Q2 discharges the output DO. At this time, a current flows from Vcc to DO via MP6 and MP7. However, since the bipolar transistor Q2 has a large current driving capability, it is hardly affected by this current and can discharge DO at high speed. Therefore, this embodiment is capable of high-speed operation. Regarding the reverse pull-up operation, when the bipolar transistor Q1 charges the output node DO, the discharging n-channel MOSFET MN7,
The bipolar transistor Q1 has a much larger current driving capability than the MOSFETs MN7 and MN8, so the same is true of the bipolar transistor Q1. In addition, in order to drive the output DO by bipolar transistors Q1 and Q2 with large current drive capacity, MOSFETs (MP6-8,
MN7-9) has the characteristic that even if the gate width is designed to be large, the operating speed does not slow down much. Therefore, data is less likely to be destroyed by noise. In particular, it is highly effective in preventing data destruction (soft errors) caused by alpha particles, which cause data destruction in minute integrated circuits.

In the CMOS circuit shown in FIG.
Because they charge and discharge at the same time, the output changes slowly. In addition, in the all-BiCMOS circuit configuration shown in Figure 8, since the bipolar transistors charge and discharge at the same time, high-speed operation is still not possible, and since both bipolar transistors have a large current driving force, a large through current flows. There was a problem that the

Next, the operation of this embodiment at low voltage will be explained. Since MP1, MP2, MN1, and MN2 operate with the same input amplitude and output amplitude as normal CMOS, the voltage dependence of the operating speed is comparable to that of CMOS. Consider the time when node N2 changes from high (Vcc) to low (ground potential).

The source terminal DO of MP5 is at Vcc until just before N2 changes, and when N2 suddenly changes to low, the maximum voltage (in absolute value) of Vcc is applied between the gate and source of MP5. applied. This is CMO
This is equivalent to the voltage applied between the gate and source of a p-channel MOSFET in the S gate. After that, N3 becomes MP
5 and turns on the bipolar transistor Q2, but at this time N3 is at a potential higher than the ground potential by about VBE. Therefore, the voltage between the drain and source of MP5 is Vcc-VBE at the maximum. However, as shown in FIG. 9(b), the drain current of the MOSFET hardly changes in the saturation region even if the voltage between the drain and source becomes small.
The reduction in source-to-source voltage does not significantly affect operating speed. In this way, this embodiment can operate at high speed even at low voltage.

FIG. 2 shows the power supply voltage dependence of the delay time when a signal reaches the output from the input of the CMOS latch circuit, the BiCMOS latch circuit shown in FIG. 8, and the embodiment of FIG. 1, respectively. At voltages below 4V, the delay time of the circuit of FIG. 8 increases rapidly, whereas this embodiment operates at high speed. The breakdown voltage of an n-channel MOSFET with a gate length of 0.5 microns determined from device deterioration due to hot carriers is approximately 4V, and the breakdown voltage of a MOSFET with a gate length smaller than this is 4V or less. Therefore, the present invention is particularly effective in integrated circuits using MOSFETs with gate lengths of 0.5 microns or less. Embodiment 2 FIG. 3 shows a circuit diagram of a latch circuit according to a second embodiment of the present invention. The difference between this embodiment and FIG. 1 is that MN1 in FIG.
, 2, MP3, 4 are replaced by MN11, MP11 in FIG. 3, and the clock signals CK, CKN
and the order of the two series-connected MOSFETs connected to the input signal DI are reversed, and the nM of FIG.
The point is that OS (MN5, 6) is replaced by resistor R1 in FIG. MN11, MP11 is MN12
, 13, MO with a smaller gate width compared to MP9 and 10.
It is composed of SFET. MN11 and MP11 are N
When the potential difference between MN11 and N6 exceeds the threshold voltage (approximately 0.5V) of MN11 and MP11, a current flows to reduce the potential difference. Therefore, when CK is low,
The inverted signal of input DI is output to N5 and N6, and C
When K is high, N5 and N6 retain their previous potentials. Therefore, the logical operation of this embodiment is similar to that of the first embodiment. Input signal DI and clock CK, C
The vertical relationship of series-connected MOSFETs to which KN is input (
The vertical relationship between MP9 and MP10, and the vertical relationship between MN12 and MN13) are clearly equivalent in terms of logical operation,
Therefore, this embodiment operates in the same way as the first embodiment. The resistor R1 connected to the base N7 of Q4 discharges the charge accumulated in the base of Q4 during operation after the operation is completed, and the operation is the same as that of MN5 and MN6 in the first embodiment. Therefore, this embodiment also has exactly the same features and effects as the first embodiment.

In this embodiment, simply connecting N5 and N6 instead of MN11 and MP11 has the same effect, but the operating speed is slightly slower than in this embodiment. The reason for this is as follows. Consider the case where N5 is charged by MP9 and MP10. In this embodiment of FIG. 3, the current leaking through MN11 and MP11 having small gate widths is small, so MP10 quickly charges N5 by simply charging the base parasitic capacitance of Q3. On the other hand, N5 is N6
If MP10 is directly connected to MN12, it is necessary to simultaneously charge the drain parasitic capacitance of MN12 and the gate capacitance of MP12, and it is also necessary to drive the through current flowing through MN12, which has a large gate width. Therefore, if N5 and N6 are connected directly, the operating speed will be slow. However, such direct connection has the advantage of having fewer elements and therefore a smaller area.

Embodiment 3 A third embodiment of the present invention will be explained with reference to FIG. FIG. 4 shows a circuit diagram of a master-slave type flip-flop according to the invention. In FIG. 4, L1 and L2 are the latch circuits described in the first embodiment, and as described in the first embodiment, they can operate at high speed even at low voltage and have low power consumption. The clocked inverters CI1 and CI2 may have a configuration as shown in FIG. 5, but they all have the same logical function.

The operation of this flip-flop is as follows, and the operation timing is shown in FIG. When CK is low, L1
acts as an inverter, and L2 is in a data holding state. At this time, assume that the input N9 changes from low to high (time T1).

Along with this, N10 changes from high to low, but since L2 is in the data holding state, N11 does not change. When CK changes from low to high (time T2), L1 enters the data holding state, keeps N10 at low level, and L2 becomes an inverter, so N11 changes from low to high. In this way, in this example, CK
When changes from low to high, the input signal is transmitted to the output and remains in the held state. That is, it operates as a D-type flip-flop.

Recently, RISC (Reduced Instruction Set Computer) processors have been attracting attention as high-speed CPUs for engineering workstations. R.I.S.
In C, cycle time is shortened and speed is increased by simplifying the instruction system, so reducing cycle time is an important issue. Conventionally, registers for microprocessors have often used two-phase clocks. When using a two-phase clock, a through-type latch circuit can be used to hold data, so the register itself is high-speed. However, in order to avoid overlap between the two phase clocks, a waiting time is required between the two clocks, which makes it unsuitable for achieving high-speed machine cycles. On the other hand, in the case of a one-phase clock, this waiting time is unnecessary, so although the clock itself can be made faster,
This requires a master-slave type flip-flop, which has the problem of increasing the delay time of the flip-flop itself. Since the flip-flop of this embodiment shown in FIG. 4 drives the output with a bipolar transistor, high-speed operation is possible. Therefore, there is a great effect on speeding up the RISC processor.

Embodiment 4 A fourth embodiment of the present invention will be explained with reference to FIGS. 10 and 11. FIG. 10 shows an integer operation block according to the present invention, and FIG. 11 shows a master-slave flip-flop with selector logic used in this integer operation block.

The operation of the integer calculation block in FIG. 10 is as follows. The ALU (arithmetic and logic unit) performs arithmetic or logical operations using inputs from the two input registers RG1 and RG2, and outputs the result as 32-bit data D1. The result from this ALU is transmitted to output register RG3 and selector SL1. The selector SL1 selects data from the data from the general-purpose register RG4 and the operation results of the ALU using the operand select control signal, and inputs the selected data to the input register (RG1).
). What determines the performance of such an integer operation block is the path indicated by the bold line in the figure. That is, it is a path in which data in the input register is subjected to ALU operations, selected by a selector, and returned to the input register.

FIG. 11 shows a 1-bit circuit diagram of a portion corresponding to selector SL1 and input register RG1 in FIG. The present embodiment in FIG. 11 has the selection logic of SL1 and the RG
The feature is that the logic of the first flip-flop is integrated. That is, similar to the third embodiment in FIG. 4, L3
A master-slave flip-flop is formed by L4 and L3, and a selector function is incorporated in L3. Here, A1 and B1 are control signals for operand selection, A2 is an output signal of the ALU, and B2 is data from a general-purpose register. The configuration shown in FIG. 5 is used as the clocked inverters CI3 and CI4. L3,
The operation of L4 is similar to that of the latch circuit described in the second embodiment of FIG. However, the MOSFET in Fig. 3, MN11, MP
11, resistors R4,5 are used in FIG. 11, and FIG.
In FIG. 11, instead of the resistor R1, nMOS, MN45,
49 is used, but the operation is exactly the same.

MP30-33 and MN40-43 constitute a two-input selector, and when control signal A1 is high, A2 is selected, and when B1 is high, B2 is selected. According to the usual configuration method of a CMOS logic circuit, in a logic in which nMOS are connected in series (for example, MN41 and MN43), a selector logic can be configured by connecting pMOS in parallel (MP32 and MP33). C.K.
When N15 is low, the inverted signal of these selected signals is
is output to. Since the operation as a flip-flop is the same as in the third embodiment, the explanation will be omitted here. As described above, since the flip-flop of FIG. 11 has a built-in selector function, the number of gate stages from the input (A1, A2, B1, B2) to the output (N20) can be reduced. Therefore,
High-speed operation is possible. If the selector and flip-flop are configured as independent BiCMOS gates, the load capacitance of the selector output is small (fanout = 1), so the speed of this selector part will be about the same as that of CMOS, and even if it is BiCMOS, it will be fast. cannot be converted into With this embodiment shown in FIG. 11, the number of logic stages can be reduced, and BiC
You can take advantage of the high-speed performance of MOS. As described above, in microprocessors, such a selector is often required at the input section of the register.

On the other hand, for example, a register with a selector is also required in a program counter section for fetching instructions, which is essential in a microprocessor configuration. As shown in FIG. 12, in the program counter, register RG5 of the adder output section stores the address of the next instruction, and continues adding a constant every cycle unless there is a branch instruction. The data in RG5, which is the result of addition by the ALU, becomes the memory address at the time of instruction fetch. The input section of this output register RG5 requires a selector SL3 that selects the input depending on the presence or absence of a branch, and by applying the flip-flop with selector shown in FIG. 11 here, high-speed operation performance can be achieved.

[0036]

According to the present invention, it is possible to realize a latch circuit and a flip-flop circuit that can operate at high speed at a low voltage of 4 V or less and have low power consumption because of a small through current. Therefore, MOS with a fine gate length of 0.5 microns or less
It can be applied to integrated circuits using FETs, and has great effects on higher integration and lower power consumption.

Also, especially at high machine cycles, 1
Suitable for speeding up RISC processors that operate on phase clocks. In microprocessors, selectors and registers are often installed consecutively, so the present invention (Embodiment 4)
This makes it possible to achieve particularly high speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a latch circuit of a first embodiment according to the present invention.

FIG. 2 shows the power supply voltage dependence of the delay time of the latch circuit of the present invention.

FIG. 3 is a circuit diagram of a latch circuit of a second embodiment according to the present invention.

FIG. 4 is a circuit diagram of a third embodiment of a master-slave flip-flop according to the present invention.

FIG. 5 is a circuit diagram of a clocked inverter used in Example 3 according to the present invention.

FIG. 6 is a diagram showing the timing of the operation of the flip-flop of Example 3 according to the present invention.

FIG. 7 is a diagram illustrating a CMOS master-slave flip-flop circuit constructed according to the prior art.

[Fig. 8] C of Fig. 7 in the conventional BiCMOS gate of Fig. 13;
FIG. 3 is a circuit diagram of a latch circuit when a MOS circuit is replaced.

FIG. 9 is a diagram showing the gate-source voltage dependence and drain-source voltage dependence of the drain current of a MOSFET.

FIG. 10 is a block diagram of an integer operation block according to an embodiment of the present invention.

FIG. 11 is a circuit diagram of a master-slave flip-flop with selector according to an embodiment of the present invention.

FIG. 12 is a block diagram of a program counter according to an embodiment of the invention.

FIG. 13 is a circuit diagram of a conventional BiCMOS two-input NAND gate.

[Explanation of symbols]

MP1-38...p channel MOSFET, MN1-49
...n channel MOSFET, Q1-16...npn bipolar transistor, I1-10...inverter circuit, R1
-R5...Resistor, RG1-5...32-bit register, SL
1-3...32-bit selector.

Claims (5)

[Claims] 1. A first npn transistor having a collector-emitter path connected between a first operating potential point and an output terminal, and a collector-emitter path connecting the output terminal and a second operating potential point. a second npn transistor connected to the first npn transistor, and first and second p-channel insulated gate FETs each having a source/drain path connected in series between the first operating potential point and the base of the first npn transistor. and a third p-channel insulated gate FET whose source/drain path is connected to the current path between the first operating potential point and the base of the second npn transistor, and the third p-channel insulated gate FET. The gate of the insulated gate FET and the second
first and second n-channel insulated gate FETs whose source/drain paths are connected in series with the operating potential point of the inverter;
a clocked inverter that receives the output signal of the inverter as an input, an output of the clocked inverter is connected to the output terminal, and the clocked inverter is configured to operate the output terminal and the first operation according to a control signal. The potential point or the above-mentioned second operating potential point is connected to the insulated gate FE.
The gate of the first p-channel insulated gate FET is connected to the gate of the first n-channel insulated gate FET, and a first input signal is supplied to this connection point; The gate of the second p-channel insulated gate FET and the second n-channel insulated gate FE
A latch circuit characterized in that the control signal and a signal having an opposite phase thereof are respectively supplied to the gate of T. Claim 2: Claim 1 in which an input signal and a control signal are supplied.
The first latch circuit according to claim 1, and the second latch circuit according to claim 1, which takes an output terminal of the first latch circuit as an input signal and operates by a control signal having a phase opposite to that of the first latch circuit. A master-slave type flip-flop characterized by: 3. A first npn transistor having a collector-emitter path connected between a first operating potential point and an output terminal, and a pull-down transistor connected between the output terminal and a second operating potential point. an element, the first operating potential point and the first
A first p-channel insulated gate FET whose source/drain path is connected to the current path between the base and the base of the npn transistor; and a p-channel insulated gate FET whose source/drain path is connected in series with the current path. a switching circuit, and a source in a current path between the base of the first pnp transistor and the second operating potential point.
a second switching circuit consisting of a first n-channel insulated gate FET with a drain path connected thereto and an n-channel insulated gate FET with a source/drain path connected in series with the first n-channel insulated gate FET; and a clocked inverter that receives the output signal of the inverter as input, the output of the clocked inverter is connected to the output terminal, and the clocked inverter is connected to the output terminal by a control signal. The clocked inverter is electrically connected to the first operating potential point or the second operating potential point via an insulated gate FET, and the clocked inverter uses the insulated gate FET to charge and discharge the output. The second switching circuit is configured to be turned off when the first switching circuit is turned on, and the second switching circuit is turned on when the first switching circuit is turned off. A latch circuit with a logic function characterized by being configured as follows. 4. A microprocessor comprising an arithmetic and logic unit, and a selector connected to either an input or an output of the arithmetic and logic unit,
4. A microprocessor characterized in that said selector comprises a latch circuit with a logic function according to claim 3. 5. One input of the selector is connected to the output of the arithmetic and logic unit, the other input of the selector is supplied with a branch destination address, and the output of the selector is connected to the output of the arithmetic and logic unit. 5. A microprocessor as claimed in claim 4, characterized in that a constant is supplied to one input and the other input of said arithmetic and logic unit.