JPS5999518A - Timer device - Google Patents

Abstract

PURPOSE:To count pulses of relatively high frequency through a small amount of hardware with high resolution by utilizing a central processor. CONSTITUTION:A counter 11 counts clock pulses 11. A register 12 holds a count value sent from a CPU15 through a data bus 16. A comparing circuit 13 compares the value of the counter 11 with the value of the register 12 and outputs a signal when they coincide with each other. A permission flag circit 17 uses the coincidence signal sent from the comparing circuit 13 to decide on whether a coincidence flag circuit 14 is set or not. A reading circuit 19 reads the most significant digit bit of the counter 11 and outputs it to the CPU15 through the data bus 16. The CPU15 is capable of accessing the register 12 and reading circuit 19 and sets and resets the permission flag circuit 17 through the data bus 16.

Description

TECHNICAL FIELD The present invention relates to a timer device, and more particularly to a timer device for measuring time pulses in a data processing device.

(Prior Art) Conventionally, this type of timer device, as shown in FIG. The comparison circuit 3 compares the value of the register 2 that holds the value, and when the two values match, the match flag circuit 4 is activated and used as an interrupt signal to the CPU 5 or as a control signal for other hardware. I used to use it. When counting a relatively large value using this device, counter 1, register 2, and comparison circuit 3 all require hardware with the number of bits that satisfies the count value, so it is not recommended to count too large a value. It was economical.

When attempting to count using a counter with a smaller number of bits than the desired count value using this device, there is a method in which the software on the CPU 5 compensates for the counter that is insufficient in hardware. For example, when counting the value 17" using a timer with a word length of 4 bits, you should set the value 15° as the initial value and set the value 15" as the initial value.
), start the counter @15”
When this happens, an interrupt is generated to the CPU 5. CPU
In this case, a method is used in which the timer is set to .degree. 2", the timer is started, and the value when the next interrupt occurs is set to .degree. 17". However, with this method, 1
The disadvantage is that the time from the first interrupt until the next timer starts appears as an error, making it impossible to count an accurate value.

As an improvement on the one shown in FIG. 1, there is a method of incorporating a grease scaler 7 into the circuit shown in FIG. 1 as shown in FIG. There is a drawback that the resolution deteriorates by the frequency divided by the prescaler 7.

(Object of the Invention) The present invention aims to improve the above-mentioned drawbacks, and by utilizing a central processing unit, pulses with a relatively high frequency can be
The purpose of the present invention is to provide a timer device that can count with high resolution and a small amount of hardware.

(Structure of the Invention) According to the present invention, in a timer device in a data processing device that includes a counter, a register that holds a count value of the counter, and a comparison circuit, a readout device that can read out at least the most significant bit of the counter is provided. a permission flag circuit that can be set and reset by a central processing unit of the data processing device; a coincidence flag circuit that is controlled based on the output of the comparison circuit and the output of the permission flag circuit; and the permission flag circuit. is set, the coincidence flag circuit is set by the coincidence signal of the comparison circuit, and when the permission flag circuit is reset, the coincidence signal of the comparison circuit is controlled so as not to set the coincidence flag circuit. A timer device is obtained, characterized in that it includes a circuit.

(Explanation of Examples) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

11 in FIG. 3 is a counter that counts clock pulses, 12 is a register that holds the count value sent from the CPU 15 using the data bus 16;
3 is a comparison circuit that compares the values of the counter 11 and the register 13 and outputs a signal when they match. 17 is a permission flag circuit that determines whether or not to set the coincidence flag circuit 14 using the coincidence signal output from the comparison circuit 13; 18 is a permission flag circuit that transmits the coincidence signal to the coincidence flag circuit 14 according to the value of the permission flag circuit 17; This is an AND circuit that controls whether to send or not, and 14 is a coincidence flag circuit that is set when the output of the AND circuit becomes "1". 15 is a CPU including registers and ALU, readout circuit 19 and register 1.
2 can be accessed and the permission flag circuit 170 set/
Reset is performed through data bus 16.

Next, when the word length of this timer circuit is 4 bits,
The case where the value 7” is counted is shown in Figure 3 shown in Figure 4.
Description will be given with reference to timing charts of signals in the main parts of the figure.

Since the timer circuit has a length of 4 bits, it can count a value of 16". At this time, the register 12 is loaded with a value of 1", and the permission flag circuit 17 is reset. In this state, the counter 11 is started. At this time, when the clock pulse for - light is input, the value of the counter 11 becomes "do" as shown at point A in FIG. 4, and since it matches the value of the register, the comparison circuit 13 outputs a match signal. However, At this point, the permission flag circuit 17 is at "0°," so the AND circuit 18 detects a match and does not send the signal to the match flag circuit 14.
4 remains at "0". Thereafter, the count value is increased each time the count progresses. When the count value reaches "8", the most significant bit of the count becomes "1", and from then on, the most significant bit continues to be "1" until the count value reaches 15", and when the count value reaches °0", the most significant bit becomes "1". The bit also becomes O. Even when the count value returns to °0" and then reaches the value of 1", if the permission flag circuit 17 is in the state of °0°, the coincidence flag circuit 14 will not be set and the count will continue indefinitely. become. In this example, the purpose is to count the value "17", so the operation for that purpose will be described below.

After the count value reaches "1°" at point A, the count value increases each time a clock pulse is input. When 8 clock pulses are input, the count value becomes "°8" and the most significant bit of the counter 11 °1", and the CPU 15 can confirm this using the readout circuit 19. When the most significant bit becomes 1" (point B), the CPU 15 can confirm this using the readout circuit 19.
When the allowable secondary pressure count value reaches "1°" by the PU 5, the coincidence signal of the comparison circuit 3 reaches the coincidence flag circuit 14 through the AND circuit 18, and the coincidence flag circuit 14 can be set.

On the other hand, the count value of the counter 11 changes from °8" to °9", "10", and
......°15", then at the 0 point it becomes °0".

When one more clock pulse is input after the 0 point, the count value of the counter 11 becomes @1" and the comparison circuit 13 outputs a match signal. At this time, the permission flag circuit 17 outputs "
Therefore, the match signal passes through the AND circuit 8, reaches the match flag circuit 14, and sets the match flag circuit 14. In other words, the above operation has a count value of 1"...
・Proceeded to ``0'', ``1'' at 157 degrees, and the match flag 14 was set at the second 1 degree, making a total of 17
After counting pulses, the coincidence flag circuit 14
1”.

When the count value is smaller than 16", by setting the permission flag circuit 17 before starting the timer, the match flag circuit 14 can be set by the -th match signal, and the count value is smaller than 16". Small values can be counted.

The count value is °24"~"31" or "40"~"47"
When the 4th bit from the least significant bit is "1", counting is possible by counting as follows. For example, to count "28", set the count value to "12"(="28" - "16"), set the permission flag circuit 17 to 0, and start the timer. The timing chart becomes as shown in Fig. 5, and the CPU 15 checks the most significant bit by the readout circuit 19, and when the most significant bit changes from "0" to °12 and then to °0 (point A). When the permission flag circuit 17 is set in this case, when the count value reaches .degree. 12'', the coincidence flag circuit 14 is set in the same manner as in the previous example.

When the count value is '45'', the count value is changed to °13'' (
= "45" - °32"), and enable flag circuit 1
7 to 0" and starts the timer. The CPU 15 checks the most significant bit by the reading circuit 19, detects that the most significant bit has changed to 01, "1", "0", "1", and then starts the next When the flag becomes “0”, the permission flag circuit 1
Set 7. Thereafter, when the count value reaches .degree. 13", the coincidence flag circuit 14 is set.

As mentioned above, when counting a count value that is longer than the word length of the timer, divide the count value by the number that can be expressed by the word length of the timer (°16" in this example) and set the remainder in register 12. The most significant bit of the counter 11 is checked by the CPU 15 using the readout circuit 19, and the number of changes of that bit is counted by the CPU 1.5, and the least significant bit of the value that has to be counted is When the 4th bit from bit is 0.

The most significant bit of the counter 11 is @1 for the quotient of the above division.
When it reaches °, set permission flag 17.

The 4th bit from the least significant bit of the value to be counted is '1'
In this case, when the circuit 1-r counter 11 reaches 0'' by the number of division steps mentioned above, the desired count value is counted by setting the permission puffer 17 to 1. can do.

In this way, the CPU 15, which is the most significant bit, counts because the input clock signal is divided by the number that can be expressed by the word length of the timer device.
The time it takes for the CPU 15 to check the most significant bit of the counter 11 becomes longer, and it can be said that even clock pulses having a period much smaller than the instruction execution cycle of the CPU 15 can be counted with high accuracy.

(Effects of the Invention) As explained in detail above, according to the apparatus of the present invention, by adopting the above-mentioned configuration, even when counting relatively large values, that is, pulses with high frequency, the processing capacity is reduced compared to the conventional method. Since there is no need to use large hardware, interrupt processing, or a prescaler, the advantage is that highly accurate counting can be performed with less hardware.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of a conventional example, Figure 3 is a block diagram of an embodiment of the present invention, and Figures 4 and 5 are timing diagrams showing the operation timing of an embodiment of the present invention. be. In the figure, 11...counter, 12...
...Register, 13... Comparison circuit, 14...
... Match flag circuit, 15 ... CPU (Central Control Processing Unit), 16 ... Data bus, 17
...Permission flag circuit, 18...AND
Circuit, 19... Readout circuit.

Claims (1)

[Claims] A timer device in a data processing device comprising a counter, a register for holding a count value of the counter, and a comparison circuit, comprising: a reading circuit capable of reading out at least the most significant bit of the counter; and a central processing unit of the data processing device. a permission flag circuit that can be set and reset; a coincidence flag circuit that is controlled based on the output of the comparison circuit and the output of the permission flag circuit; A timer device comprising: a control circuit that controls the coincidence flag circuit so that the coincidence signal of the circuit does not set the coincidence flag circuit.