JPS5996849U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5996849U
JPS5996849U JP19220282U JP19220282U JPS5996849U JP S5996849 U JPS5996849 U JP S5996849U JP 19220282 U JP19220282 U JP 19220282U JP 19220282 U JP19220282 U JP 19220282U JP S5996849 U JPS5996849 U JP S5996849U
Authority
JP
Japan
Prior art keywords
metal
semiconductor equipment
reaction layer
gold
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19220282U
Other languages
Japanese (ja)
Inventor
角和　晴夫
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP19220282U priority Critical patent/JPS5996849U/en
Publication of JPS5996849U publication Critical patent/JPS5996849U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のダイオードチップの断面図、第２図は従
来のタイオードのパッケージへの組立図、第３図及び第
４図は何れもこの考案の半導体装置の生成品断面図、第
５図はこの考案ダイオードチップの断面図である。 各図で、１・・・金属、２・・・モリブテン層、３・・
・チタン層、４・・・酸化膜、１２・・・錫層、１３・
・・金−錫合金層、１４・・・厚い金層。Figure 1 is a cross-sectional view of a conventional diode chip, Figure 2 is a diagram of a conventional diode assembled into a package, Figures 3 and 4 are cross-sectional views of the semiconductor device of this invention, and Figure 5. is a cross-sectional view of this invented diode chip. In each figure, 1...metal, 2...molybdenum layer, 3...
・Titanium layer, 4... Oxide film, 12... Tin layer, 13.
...Gold-tin alloy layer, 14...Thick gold layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ポンディングパッドを形成する金属電極として、錫又は
インジウム等の低融点金属と金との金属反応層と、この
金属反応層上に金属を堆積形成させた積層電極を具備す
ることを特徴とする半導体装置。　　−A semiconductor characterized by comprising, as a metal electrode forming a bonding pad, a metal reaction layer of a low melting point metal such as tin or indium and gold, and a laminated electrode in which a metal is deposited on the metal reaction layer. Device. −
JP19220282U 1982-12-21 1982-12-21 semiconductor equipment Pending JPS5996849U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19220282U JPS5996849U (en) 1982-12-21 1982-12-21 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19220282U JPS5996849U (en) 1982-12-21 1982-12-21 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS5996849U true JPS5996849U (en) 1984-06-30

Family

ID=30413694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19220282U Pending JPS5996849U (en) 1982-12-21 1982-12-21 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5996849U (en)

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