JPS5996724A - Manufacture of semiconductor device with contact hole having no poor contact - Google Patents
Manufacture of semiconductor device with contact hole having no poor contactInfo
- Publication number
- JPS5996724A JPS5996724A JP20673582A JP20673582A JPS5996724A JP S5996724 A JPS5996724 A JP S5996724A JP 20673582 A JP20673582 A JP 20673582A JP 20673582 A JP20673582 A JP 20673582A JP S5996724 A JPS5996724 A JP S5996724A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- insulating film
- contact hole
- polycrystalline silicon
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 23
- 238000001259 photo etching Methods 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 239000012808 vapor phase Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 10
- 238000001947 vapour-phase growth Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかシ、とくに集積回
路のコンタクト孔の形成法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming contact holes in an integrated circuit.
集製回路の集積度上昇とともに微細加工技術が要求され
、コンタクト孔の開口は微細加工に有利な平行平板型ス
パッタ・エツチング装置によるＲ１．Ｅ （反応性イオ
ン・エツチング）技術が実用化されている。しかし、ガ
スにＣＦ４＋Ｈ２を用いた場合、几ＩＥのエツチング選
択比は、酸化珪素対珪素で約２０対１、窒化珪素対珪素
で約１０対１程度であり、十分大きいとは言えず、多様
なすべてのコンタクトをフォトエツチングにて開口する
場合などは絶縁膜厚の不均一、性等のため、かなシのオ
ーバーエツチングを要している。、
一方、集積回路は集積度向上、高性能化のため拡散層深
さは浅い方が好ましく肩側としてＭＯＳ ＦＥＴのソー
ス・ドレイン拡散層深さは０．２μｍ〜０．３μｍ程度
になっている。As the degree of integration of integrated circuits increases, microfabrication technology is required, and the opening of the contact hole is etched by R1. E (reactive ion etching) technology has been put into practical use. However, when CF4+H2 is used as the gas, the etching selectivity of the IE is approximately 20:1 for silicon oxide to silicon and approximately 10:1 for silicon nitride to silicon, which is not sufficiently large and can be used in various ways. When all contacts are opened by photo-etching, over-etching is required due to non-uniformity of the insulating film thickness, etc. On the other hand, in order to improve the degree of integration and performance of integrated circuits, it is preferable for the depth of the diffusion layer to be shallow.The depth of the source/drain diffusion layer of a MOS FET on the shoulder side is approximately 0.2 μm to 0.3 μm. .
しかしコンタクト孔開口時のオーバーエッチングは拡散
層へのくい込みとなり、最悪の場合拡散層と半導体基板
間の接合が破壊され、素子の特性劣化、歩留り低下につ
ながる。However, over-etching when opening a contact hole digs into the diffusion layer, and in the worst case, the bond between the diffusion layer and the semiconductor substrate is destroyed, leading to deterioration of device characteristics and lower yield.
本発明は従来の半導体装置製造設備を用い、集積度の低
下をともなうことなく、良好なコンタクト孔の開口を可
能にすることを目的としている。It is an object of the present invention to make it possible to form contact holes with good quality using conventional semiconductor device manufacturing equipment without reducing the degree of integration.
すなわち、本発明は第１の絶縁膜に対し第１のコンタク
ト孔をフォトエツチングによシ開口する工程と、前記コ
ンタクト上に多結晶珪素層を成長し、フォトエツチング
により所望の形状に形成する工程と、第２の絶縁膜を成
長し第２のコンタクト孔をフォトエツチングによシ開口
する工程とを有することを特徴とする半導体装置の製造
方法にある。That is, the present invention includes a step of opening a first contact hole in a first insulating film by photoetching, and a step of growing a polycrystalline silicon layer on the contact and forming it into a desired shape by photoetching. and a step of growing a second insulating film and opening a second contact hole by photo-etching.
本発明を以下図面を用いて説明する。The present invention will be explained below using the drawings.
第１図は従来技術によシ形成したコンタクト孔を含む半
導体装置の断面図である。ここでは例として一層配線シ
リコンゲートＭＯ８ＦＥＴを示している。半導体基板１
０１にリース・ドレイン領域１０２を形成した後、例え
ば酸化購のような絶縁膜１０５を気相成長法により付着
させ、所望の位置にソース・ドレイン、ゲートの各コン
タクト孔１０６をフォトエツチング法により開口する。FIG. 1 is a cross-sectional view of a semiconductor device including contact holes formed according to the prior art. Here, a single-layer wiring silicon gate MO8FET is shown as an example. Semiconductor substrate 1
After forming the lease/drain region 102 on the substrate 01, an insulating film 105 such as oxide film is deposited by vapor phase epitaxy, and source/drain and gate contact holes 106 are opened at desired positions by photoetching. do.
コンタクト孔のエツチング法は集積度上昇のためＲＩＥ
等の異方性エツチングが用いられている。七の後に配線
物質１０７を付着させ、フォトエツチング法にて配線系
を形成し、最後に保護膜１０８を気相成−長法により付
着させている。The etching method for contact holes is RIE to increase the degree of integration.
Anisotropic etching methods such as etching are used. After step 7, a wiring material 107 is deposited, a wiring system is formed by photoetching, and finally a protective film 108 is deposited by vapor phase growth.
第２図は本発明の一実施例の方法を示すものである。例
として一層配線シリコンゲー） ＭＯＳＦＥＴを示す。FIG. 2 shows a method according to one embodiment of the present invention. As an example, a single-layer wiring silicon MOSFET is shown.
従来技術によシンース・ドレイン領域２０２を半導体基
板２０１に形成した後、第１の絶縁膜２０９を気相成長
法によシ付着する。このとき第１の絶縁膜２０９の膜厚
は、コンタクト孔の大きさに対して十分薄くしておく。After a thin drain region 202 is formed on a semiconductor substrate 201 using conventional techniques, a first insulating film 209 is deposited using a vapor phase growth method. At this time, the thickness of the first insulating film 209 is made sufficiently thin relative to the size of the contact hole.
次に７オトレジスト２１０をマスクに第１のコンタクト
孔２１１を開口する（第２図Ａ）。第１のコンタクト孔
開口の際のエツチングは、第１の絶縁膜を薄くしである
ため、等方性エツチングを適用しても横方向のひろがシ
は小さく、なるべくエツチング選択比のよい方法を用い
ることができる。例えば第１の絶縁膜に酸化珪素を用い
た場合、第１のコンタクト孔のエツチングは弗化水素系
のウェットエツチングで行なえ、コンタクト開口時の基
板のオーバーエッチ量を最小限に留めることができろ。Next, a first contact hole 211 is opened using the No. 7 photoresist 210 as a mask (FIG. 2A). The etching for opening the first contact hole is to thin the first insulating film, so even if isotropic etching is applied, the lateral spread is small, so a method with a good etching selectivity is preferred. Can be used. For example, when silicon oxide is used for the first insulating film, the first contact hole can be etched using hydrogen fluoride-based wet etching, and the amount of overetching of the substrate when opening the contact can be kept to a minimum. .
第１のコンタクト孔開口径多結晶珪素膜２１２を成長し
、第１のコンタクト上に適当なマニジンをとって多結晶
珪素領域をフオ）エツチングにより形成する（第２図Ｂ
）０
次に第２の絶縁膜２１３気相成長法により成長し、第２
のコンタクト孔２１４を開口する。A polycrystalline silicon film 212 with a first contact hole opening size is grown, and a polycrystalline silicon region is formed on the first contact by photo-etching using an appropriate manufacturer (FIG. 2B).
)0 Next, a second insulating film 213 is grown by vapor phase epitaxy, and the second insulating film 213 is grown by vapor phase growth.
A contact hole 214 is opened.
第２のコンタクト孔開口の際のエツチングは、反応性イ
オンエツチング等の異方性エツチングを適用する。この
時、多少のオーバーエツチングを行なっても多結晶珪素
層がエツチングに対する緩衝膜２１３を気相成長法によ
り成長１第２のコンタクト孔２１４を開口する。第２の
コンタクト孔開口の際のエツチングは、反応性イオンエ
ツチング等の異方性エンチングを適用する。この時 多
少のオーバーエツチングを行なっても多結晶珪素層がエ
ツチングに対する緩衝層となり、拡散層２０２がエツチ
ングされてしまうことはない（第２図Ｃ）。For etching when opening the second contact hole, anisotropic etching such as reactive ion etching is applied. At this time, even if some over-etching is performed, the polycrystalline silicon layer forms a buffer film 213 against etching, and a second contact hole 214 is opened by the vapor phase growth method. For etching when opening the second contact hole, anisotropic etching such as reactive ion etching is applied. At this time, even if some overetching is performed, the polycrystalline silicon layer serves as a buffer layer against etching, and the diffusion layer 202 will not be etched (FIG. 2C).
第２のコンタクト孔開口後、配線物質２０７を付着させ
フォトエツチングにより配線系を形成し、保護膜２０８
を気相成長法により付着させＭＯＳ ＦＥＴは完成する
（第２図Ｄ）。After opening the second contact hole, a wiring material 207 is deposited and a wiring system is formed by photo-etching, and a protective film 208 is formed.
is deposited by vapor phase growth to complete the MOS FET (Fig. 2D).
以上、ＭＯＳ ＦＥＴを例にとシ祝明裟行なったが、本
発明は絶線膜を気相成長法によυ形成し、これに対しコ
ンタクト孔をフォトエツチング法にて開口する工程を持
つすべての集積回路は適用できる。The above has been carried out using a MOS FET as an example, but the present invention is applicable to all devices which include the process of forming an insulated film by a vapor phase epitaxy method and opening a contact hole using a photoetching method. integrated circuits are applicable.
以上の説明よシ明らかな如く本発明は、絶縁膜成長工程
での膜厚の不均一性等に起因するコンタクト不良を改善
し、集積回路の歩留シを上げる方法を提供している。As is clear from the above description, the present invention provides a method for improving contact defects caused by non-uniformity of film thickness during the insulating film growth process and increasing the yield of integrated circuits.
第１図は従来技術によ多開口したコンタクト孔を含むＭ
ＯＳ ＦＥＴの断面図である。第２図（５）〜（Ｄ）は
各々本発明の一実施例７ＭＯ８ＦＥＴを例にとシ示した
工程順断面図である。
同、図において、１０１，２０１・・・・・・半導体基
板、１０２．２０２・・・リースドレイン拡散層、１０
３゜２０３・・・・・・多結晶シリコンゲート、１０４
，２０４・・・・・・素子間分離酸化膜、１０５・・・
・・・絶縁ｊ漠、１０６・・・・・・従来技術で開口し
たコンタクト孔、１０７．２０７・・・・・・配線物質
、１０８，２０８・・・・・・保護膜、２０９・・・・
・・第１の絶縁膜、２１Ｏ・・山フォトレジスト、２１
１・ 第１のコンタクト孔、２１２・・・・・・多結晶
珪素、２１３・・・・・第２の絶縁膜、２１４・・・・
・・第２のコンタクト孔、である。
８１図FIG. 1 shows an M including contact holes with multiple openings according to the prior art.
FIG. 2 is a cross-sectional view of an OS FET. FIGS. 2(5) to 2(D) are sectional views in the order of steps, each showing a MO8FET according to an embodiment of the present invention as an example. In the same figure, 101, 201... Semiconductor substrate, 102, 202... Lease drain diffusion layer, 10
3゜203・・・Polycrystalline silicon gate, 104
, 204... Inter-element isolation oxide film, 105...
...Insulation, 106...Contact hole opened using conventional technology, 107.207...Wiring material, 108,208...Protective film, 209...・
...First insulating film, 21O...Mountain photoresist, 21
1. First contact hole, 212... polycrystalline silicon, 213... second insulating film, 214...
...Second contact hole. Figure 81
Claims (1)
る工程を有する半導体装置の製造方法において、第１の
絶縁膜を成長する工程と、前記第１の絶縁膜に第１のコ
ンタクト孔を開口する工程と、前記第１の・コンタクト
孔上に多結晶シリコン層を形成し所望の形状にパターン
ニングする工程と、前記第１のコンタクト上にパターン
ニングされた多結晶シリコンを持つ半導体基板上に、第
２の絶縁膜を成長し、第２のコンタクト孔を開口する工
程とを有することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device comprising the steps of simultaneously opening a contact hole in an insulating film on a semiconductor substrate, the step of growing a first insulating film, and opening a first contact hole in the first insulating film. a step of forming a polycrystalline silicon layer over the first contact hole and patterning it into a desired shape; A method for manufacturing a semiconductor device, comprising the steps of growing a second insulating film and opening a second contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20673582A JPS5996724A (en) | 1982-11-25 | 1982-11-25 | Manufacture of semiconductor device with contact hole having no poor contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20673582A JPS5996724A (en) | 1982-11-25 | 1982-11-25 | Manufacture of semiconductor device with contact hole having no poor contact |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5996724A true JPS5996724A (en) | 1984-06-04 |
Family
ID=16528231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20673582A Pending JPS5996724A (en) | 1982-11-25 | 1982-11-25 | Manufacture of semiconductor device with contact hole having no poor contact |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5996724A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6316671A (en) * | 1986-07-08 | 1988-01-23 | Nec Corp | Manufacture of silicide gate semiconductor device |
-
1982
- 1982-11-25 JP JP20673582A patent/JPS5996724A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6316671A (en) * | 1986-07-08 | 1988-01-23 | Nec Corp | Manufacture of silicide gate semiconductor device |
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