JPS5995730A - Semiconductor digital integrated circuit - Google Patents

Semiconductor digital integrated circuit

Info

Publication number
JPS5995730A
JPS5995730A JP57206612A JP20661282A JPS5995730A JP S5995730 A JPS5995730 A JP S5995730A JP 57206612 A JP57206612 A JP 57206612A JP 20661282 A JP20661282 A JP 20661282A JP S5995730 A JPS5995730 A JP S5995730A
Authority
JP
Japan
Prior art keywords
output
circuit
input signal
mutual conductance
trstr5
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57206612A
Other languages
Japanese (ja)
Inventor
Toshiaki Maiwa
真岩　寿昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57206612A priority Critical patent/JPS5995730A/en
Publication of JPS5995730A publication Critical patent/JPS5995730A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain high speed operation and to improve the reliability by inserting a depletion MOSFET to an output circuit and increasing the mutual conductance in synchronizing with the inversion of an input signal. CONSTITUTION:A current path of an utput circuit section of an integrated circuit comprising an inverter section consisting of MOS transistors (TRs)TR1, TR2 and the output circuit section consisting of MOS TRsTR3, TR4, is provided with D MOS TRsTR5, TR6 and an input signal s applied to the gate via a control circuit comprising an EXOREX and an inverter. An output of the EXOREX goes temporarily to H level at the inversion of the input signal and the mutual conductance of the TRsTR5, TR6 is increased, then the leading and trailing of the output voltage are quickened. When the input signalis not changed, the mutual conductance of the TRsTR5, TR6 is reduced and a flowing current is less even if there exists a short-circuit between the outputs.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体デジタル集積回路に係り、特に出力回路
部の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor digital integrated circuit, and particularly to an improvement in an output circuit section.

〔発明の技術的背景〕[Technical background of the invention]

第１図は従来の半導体デジタル集積回路の出力回路部の
一例を示す図で、デプレッション型のトランジスタＴｒ
ｌとエンハンスメント型のトランジスタＴｒ２を直列に
接続して電源ＶＣＣと基準電位との間に介挿している。FIG. 1 is a diagram showing an example of the output circuit section of a conventional semiconductor digital integrated circuit.
1 and an enhancement type transistor Tr2 are connected in series and inserted between the power supply VCC and the reference potential.

またエンハンスメント型のトランジスタＴｒ３１　’ｒ
、を直列に接続し電源ＶＣＣと基準電位との間に介挿し
ている。Also, an enhancement type transistor Tr31'r
, are connected in series and inserted between the power supply VCC and the reference potential.

そしてトランジスタＴｒｓ　ｒ　Ｔ　ｒ　２の直列接続
点にトランジスタＴｒＩ、　Ｔｒ３の各ゲートを接続し
ている。またトランジスタ’ｒｒ２１　’ｒｒ、のゲー
トを入力端子ＩＮに接続し、トランジスタＴｒ３　、　
Ｔｒ４の直列接続点を出力端子ＯＵ、Ｔに接続するとと
もに４準電位との間にコンデンサＣを介挿している。The gates of the transistors TrI and Tr3 are connected to the series connection point of the transistors TrsrTr2. Also, the gates of transistors 'rr21'rr, are connected to the input terminal IN, and the transistors Tr3,
The series connection point of Tr4 is connected to the output terminals OU and T, and a capacitor C is inserted between it and the quasi-potential of Tr4.

〔背景技術の問題点〕[Problems with background technology]

しかしながら第１図に示すような構成のものでは、出力
電流Ｉｈ、　ＩΦは出力回路部のトランジスタＴｒ３　
＊　Ｔｒ４のＧｍ　（相互コンダクタンス）。However, in the configuration shown in FIG. 1, the output currents Ih and IΦ are
* Gm (mutual conductance) of Tr4.

ＶＴＲ（スレッシホールド電圧）等の特性によって定ま
る。It is determined by the characteristics of the VTR (threshold voltage), etc.

一方半導体デジタル集積回路では常に高速性および高信
頼性を要求される。これに対して第１図に示すようなも
のでは高速性を満たすためには出力回路部のトランジス
タＴｒ、　（Ｔｒ、　　のＧｍを大きくシ、出力電圧ｅ
０の立上シ、立下り時間を小さくする必要がある。一方
、高信頼性を図るだめには、将に出力回路部の省消費電
力化を図９、配線材の損傷の機会を減少するとともにパ
スライン上における出力間短絡時に流出入する電流を小
さくする必要がある。このためには出力回路部のトラン
ジスタＴｒ５．　Ｔｒ４のａｍを小さくしなければなら
ない。On the other hand, semiconductor digital integrated circuits always require high speed and high reliability. On the other hand, in the device shown in Fig. 1, in order to achieve high speed, the Gm of the transistor Tr, (Tr, ) in the output circuit section must be increased, and the output voltage e
It is necessary to reduce the rise and fall times of 0. On the other hand, in order to achieve high reliability, it is necessary to reduce the power consumption of the output circuit section, reduce the chance of damage to the wiring material, and reduce the current that flows in and out when short circuits occur between outputs on the pass line. There is a need. For this purpose, transistor Tr5. The am of Tr4 must be made small.

したがって第１図に示すような従来の回路構成では高速
性と高信頼性を同時に満たすことは困維であった。Therefore, with the conventional circuit configuration as shown in FIG. 1, it is difficult to simultaneously satisfy high speed and high reliability.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みてなされたもので高速性と高
信頼性を共に満たすことができる半４体デジタル果槓回
路を提供することを目的とするものである。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semi-quadruple digital fruit casing circuit that can satisfy both high speed and high reliability.

〔発明の（既製〕[Invention (ready-made)]

すなわち本発明は出方回路部のトランジスタに直列Ｋ）
ランシフタを介挿し、このトランジスタのＣ）ｍを入力
信号の反転に同期して一時的に大きくすることを特徴と
するものである。In other words, in the present invention, the transistor is connected in series with the transistor in the output circuit section.
This is characterized by inserting a run shifter and temporarily increasing C)m of this transistor in synchronization with the inversion of the input signal.

〔発明の実施レリ〕[Practice of the invention]

以下本発明の一実施しυを第１図と同一部分に同一符号
を付与して第２図に示すブロック図を参照して詳Ｊ１朋
に説明する。すなわち出力回路部のトランジスタＴｒ３
　、　Ｔｒ４０間に２個のデプレッション型の制御トラ
ンジスタＴｒ！ｌ　ｒ　’ｒｒ、を直列に接続して介挿
する。そしてこの制御トランジスタＴｒ！ｉ　ｒ　Ｔｒ
６の直列接続点を出力端子ＯＵＴに接読するようにして
いる。Hereinafter, one embodiment of the present invention will be explained in detail with reference to the block diagram shown in FIG. 2, in which the same parts as in FIG. 1 are given the same reference numerals. In other words, the transistor Tr3 in the output circuit section
, two depression type control transistors Tr! between Tr40. l r 'rr, are connected in series and inserted. And this control transistor Tr! i r Tr
The series connection point of 6 is connected directly to the output terminal OUT.

、　そして入力信号の反転に同期した信号を得るＭ；ｌ
制御回路は、入力端チェＮから入力信号をＥＸ−ＯＲゲ
ートＥｘの一方の入力へは直接、他方の入力へはインバ
ータエＮ’Ｖを介して与える。, and obtain a signal synchronized with the inversion of the input signal M;l
The control circuit applies an input signal from an input terminal N directly to one input of the EX-OR gate Ex, and to the other input via an inverter N'V.

そして上記ＥＸ−ＯＲゲートＥＸの出力を上記制御トラ
ンジスタＴｒ、　、　Ｔｒ６のゲートへ与えるようにし
ている。なおここで制御トランジスタＴｒ、、　、　Ｔ
ｒ６の相互コンダクタンスを入力信号の反転に同期して
増大させる期間に対応してインバータＩＮＶで信号を遅
延させる。The output of the EX-OR gate EX is applied to the gates of the control transistors Tr, Tr6. Note that here, the control transistors Tr, , , T
The signal is delayed by the inverter INV corresponding to a period in which the mutual conductance of r6 is increased in synchronization with the inversion of the input signal.

このような構成であれば、第３図に示すように入力端子
ＩＮの入力信号の反転時にだけ一定期間制御回路から”
Ｈ”レベルの制御信号が出力される。一方制御トランジ
スタＴｒ５　、　Ｔｒ６　はディプレッション型であシ
、上記制御信号がＬ”レベルの期間は、Ｇｍは小さくそ
れによって出力回路部のトランジスタＴｒ、、　、　Ｔ
ｒ４の見かけのＧｍを小さくでき出力電流Ｉｈ、Ｉｅを
小さくし、信頼１生を向上することができる。また、入
力信号の反転に同期して一定期間、：Ｉｌ」両信号が″
Ｈルベルになると、それによって制御トランジスｐ　Ｔ
ｒ５１　’Ｔｒ６のＧｍを大きくする。したがって出力
回路部のトランジスタＴｒ３　、　Ｔｒ、の見かけの（
）ｎｎ　ｆ大きくでき出力′電圧ｅ。の立ち上がり、立
ち下がシ時間を小さくシ、高速化を図ることができる。With such a configuration, as shown in FIG. 3, "
An H" level control signal is output. On the other hand, the control transistors Tr5 and Tr6 are depletion type, and during the period when the control signal is L" level, Gm is small, so that the output circuit transistors Tr, , T
The apparent Gm of r4 can be reduced, the output currents Ih and Ie can be reduced, and reliability can be improved. Also, for a certain period of time in synchronization with the inversion of the input signal, both the :Il'' and ``
H level, thereby controlling the control transistor p T
r51' Increase Gm of Tr6. Therefore, the apparent (
) nn f can be increased to output 'voltage e. It is possible to reduce the time required for the rise and fall of the signal, thereby increasing the speed.

したがって第５図で出力端子ＯＵＴの波形で破線で示す
ものに比して立ち上り、立ち下Ｄ　Ｉ＋＝性を著るしく
改善できる。Therefore, compared to the waveform of the output terminal OUT shown by the broken line in FIG. 5, the rise and fall characteristics can be significantly improved.

なお本発明は上記実施例に限定されるものではなく、た
とえば制御トランジスタＴｒ６　ｒ　Ｔｒ　６は一個だ
けを出力回路部のトランジスタＴｒｓ　。Note that the present invention is not limited to the above-mentioned embodiment, and for example, only one control transistor Tr6 r Tr 6 is used as the transistor Trs of the output circuit section.

Ｔｒ＋の直列接続点と出力端子ＯＵＴとの間に介挿して
もよい。また上記制御回路も実施レリに限定されること
なく内部動作に同期して動作するもの、出力電位の検出
信号で制御トランジスタの相互コンダクタンスを可変す
るもの等を適宜に用い得る。It may be inserted between the series connection point of Tr+ and the output terminal OUT. Furthermore, the control circuit described above is not limited to the actual implementation, but may be appropriately used such as one that operates in synchronization with internal operation, one that varies the mutual conductance of the control transistor using a detection signal of the output potential, etc.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば簡単な構成によシ高速性と
高信頼性を共に満すことができる半導体デジタル集積回
路を提供することができる。As described above, according to the present invention, it is possible to provide a semiconductor digital integrated circuit that can satisfy both high speed and high reliability with a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体デジタル集積回路の一例を示すブ
ロック図、第２図は本発明の一実施例を示すブロック図
、第３図は上記実施例の動作を説明するタイミング図で
ある。 Ｔｒｌ〜Ｔｒ４・・・トランジスタ、Ｔｒ５１　Ｔｒ６
・・・制御トランジスタ、ＩＮ・・・入力端子、ＯＵＴ
・・・出力端子、ＥＸ・　ＥＸ−ＯＲゲート、Ｉ　Ｎ　
Ｖ−／１ンバータ。 第１図 第２図 第３図FIG. 1 is a block diagram showing an example of a conventional semiconductor digital integrated circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart explaining the operation of the above embodiment. Trl~Tr4...Transistor, Tr51 Tr6
...Control transistor, IN...Input terminal, OUT
・・・Output terminal, EX/EX-OR gate, IN
V-/1 inverter. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 出力回路部のトランジスタの出力電流の流れる径路に介
挿したデプレッション型の制御トランジスタと、入力信
号の反転に同期して一定期間だけ上記制御トランジスタ
の相互コンダクタンスを大きくする制御回路とを具１腑
する半導体デジタル集積回路。A depletion type control transistor is inserted in the path through which the output current of the transistor of the output circuit section flows, and a control circuit that increases the mutual conductance of the control transistor for a certain period of time in synchronization with the inversion of the input signal. Semiconductor digital integrated circuit.
JP57206612A 1982-11-25 1982-11-25 Semiconductor digital integrated circuit Pending JPS5995730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57206612A JPS5995730A (en) 1982-11-25 1982-11-25 Semiconductor digital integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57206612A JPS5995730A (en) 1982-11-25 1982-11-25 Semiconductor digital integrated circuit

Publications (1)

Publication Number Publication Date
JPS5995730A true JPS5995730A (en) 1984-06-01

Family

ID=16526256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57206612A Pending JPS5995730A (en) 1982-11-25 1982-11-25 Semiconductor digital integrated circuit

Country Status (1)

Country Link
JP (1) JPS5995730A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0889592A2 (en) * 1997-06-30 1999-01-07 Siemens Aktiengesellschaft OCD With low output capacitance
WO2003075464A1 (en) * 2002-03-06 2003-09-12 Igor Anatolievich Abrosimov Line driver with reduced power consumption
US7203243B2 (en) 2003-03-10 2007-04-10 Acuid Corporation (Guernsey) Limited Line driver with reduced power consumption

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0889592A2 (en) * 1997-06-30 1999-01-07 Siemens Aktiengesellschaft OCD With low output capacitance
EP0889592A3 (en) * 1997-06-30 1999-03-17 Siemens Aktiengesellschaft OCD With low output capacitance
WO2003075464A1 (en) * 2002-03-06 2003-09-12 Igor Anatolievich Abrosimov Line driver with reduced power consumption
US7203243B2 (en) 2003-03-10 2007-04-10 Acuid Corporation (Guernsey) Limited Line driver with reduced power consumption

Similar Documents

Publication Publication Date Title
KR930008859A (en) DC-Current Data Output Buffer
US4870609A (en) High speed full adder using complementary input-output signals
KR860007783A (en) Comparator Circuit with Improved Output Characteristics
JPS5995730A (en) Semiconductor digital integrated circuit
JPS62159910A (en) Semiconductor integrated circuit
JPS6134690B2 (en)
JP2666347B2 (en) Output circuit
JP2654275B2 (en) Bidirectional buffer
JPS63266921A (en) Power-on reset signal generating circuit
JPH03179814A (en) Level shift circuit
KR100268948B1 (en) Transmission gate circuit
JP2864494B2 (en) Semiconductor integrated circuit
JPS61214817A (en) Cmos integrated circuit
JP2697024B2 (en) Output circuit
JPH01228214A (en) Semiconductor integrated circuit
JP2735268B2 (en) LSI output buffer
JP2932858B2 (en) Level conversion circuit
JPH07283717A (en) Through current preventing circuit for cmos inverter circuit
SU1615877A1 (en) Logic cell with bipolar and mos-transistors
JPS58175324A (en) Input circuit
KR940006659Y1 (en) Boot strapping data output buffer
JPH0347012B2 (en)
JPS61202519A (en) Comparator circuit
JPS60117820A (en) Input circuit
JPH06232728A (en) Input output circuit