JPS59953A - Mos type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the difference of the characteristics of two sets of elements by connecting each of the drains, and each of the gate electrodes of two MOS transistors which are disposed in a point symmetrical positional relationship to the central point of a common source region. CONSTITUTION:A common source region 22 is extended in the prescribed direction on a semiconductor substrate 20. Drain regions 22C, 22D which have the same areas as drain regions 22A, 22B are arranged by two along a pair of long sides of the region 21. Gate electrodes 25A-25D are formed on the surface of the substrate 20 between the region 21 and four regions 22A-22D. MOS transistors 27A, 27D and 27B, 27C are disposed in a point symmetrical relationship to the central point of the region 21. The regions 22A and 22D, the regions 22B and 22C, the electrodes 25A and 25D, the electrodes 25B and 25C are respectively connected via diffused wiring layers 24A-24G, and wiring layers 26A-26G.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an MO8 type semiconductor integrated circuit in which each element is constituted by a pair of MOB transistors connected in parallel.

[Technical background of the invention]

Figure 1 is composed of MOB) Ranjisushi.

This figure shows a differential amplifier circuit. In the figure, two P-channel MOB transistors 1.2 constitute a differential pair l,
Further, two N-channel MO8) transistors 4 and 5 constitute a current Giller circuit i.

Then, from the output terminal 1 provided at the connection point between MOB) transistors 1 and 4, the f-
) Reference voltage VREF applied to the electrode and input voltage vIN applied to the dirt electrode of MOB transistor 2
700 voltages are output according to the difference between the two.

By the way, when integrating a differential amplifier circuit as shown in Figure 1 above, in order to match the characteristics of each MO8 transistor, each MO8 transistor 1v2w4*5 is constructed by connecting a pair of MOB transistors in parallel. be done.

Figure 5 shows the P-channel MO8) transistor 1 of the circuit in Figure 1.
, 2 are actually integrated.

In the figure, a pair of P-type source regions 11 11B are formed on an N-type semiconductor substrate 10 by a diffusion method. Maintaining a predetermined distance from each of the two opposing sides of one source region 11A, this source region 11A
1 in a pair of P-type drain regions 12 so as to sandwich the
2B is formed. Furthermore, in the same way, 13B is formed in a pair of P-type drain regions 13 so as to sandwich the source region 11B at a predetermined distance from each of the two opposing sides of the other source region 11B. There is. In addition, 11 people from these source areas.

JIB and drain region z2A*x2B+J, 9A,
JJB is usually formed simultaneously in - times of diffusion steps.

1 in the 11 source regions and the pair of drain regions 12.
A dirt insulating film 14A is formed on the ground surface of the substrate U between each of the substrates 2B and 2B.

Similarly, the source region JIB and a pair of drain regions 13A are formed by deposition.

e-) Insulating films 15 A t 15 B are deposited on the surfaces of the substrates 13 B and 15 A t 15 B, respectively. Furthermore, a pair of P-type diffusion wiring layers 161.1fjB are formed in parallel between the pair of source regions 114°JIB.

The above f-) is made of aluminum on the insulating film 14A.
A second electrode J7A is deposited, and furthermore, this electrode J7A is extended and its tip is connected to the one diffusion wiring layer 16B.

Similarly, each of the remaining dirt insulating films 14B.

15, dirt electrode 1 made of aluminum is on 16B.
7B, 17C, and 17D are deposited, and furthermore, these electrodes J7B and J7C are formed.

J7D is extended, and the tips of electrode 17B and electrode 17C are connected to the other diffusion wiring layer 16A, and electrode J7D is extended.
The tip end of 7D is connected to the one diffusion wiring layer 16B. Further, each of the diffusion wiring layers 16 and 16B is connected to the wiring layer 18 made of aluminum and to other circuit parts through each of the wiring layers 18B. The pair of drain regions JJA and 13B are the wiring layer 1 made of aluminum.
8C, and this wiring layer 18C is further connected to other circuits/circuit parts. The pair of drain regions 12B and J, IA are connected via another wiring layer 18D made of aluminum, and this wiring layer 18D is further connected to other circuit parts. The pair of source regions 11A and JIB are interconnection layers 18E made of aluminum.
This wiring layer IRE is connected to other circuit parts.

In the circuit shown in the 4' turn plan view of FIG. 2, as shown in the figure, four P-channel MO transistors 19 - and -190 are integrated, and MOS transistors 19 and 19D are integrated. Also MOS) transistor 19B
and 19C are connected in parallel, respectively, to constitute the differential pair portion of the circuit shown in FIG. In the four MOS transistors 19A to 19D, MOS transistor 1
The reason why 9A and 19D and 19B and 19C are connected in parallel and used is as follows.

That is, in general, the impurity concentration in a semiconductor substrate (wafer) is not uniform, but has a concentric concentration gradient as shown in FIG. In general, the closer to the center of this concentration gradient, the higher the concentration. Therefore, if each of the differential pair parts of the circuit shown in FIG. The on-resistance value, parasitic capacitance, and other characteristics of the two do not match. However, when the MOS transistors of this differential pair 1 part are configured with each pair of MOS transistors 19, 19D and υ' and 19C connected in parallel as shown in Fig. 2, the concentration distribution of the substrate becomes Assume that the situation is as shown in Figure 3. At this time,
The concentration difference between the portions forming the pair of MOS transistors 19C and 19B is small. Also MOS transistor 19
The concentration of the part formed in the MOS) transistor 19 is higher than that in the B forming part, and the MOS) range meta 19C
The density of the MOS) run raster 190 forming part is lower than this, and the difference between the density of each of the 19B and 19C forming parts and the density of each of the 19119D forming parts is almost equal. Therefore, by connecting 198.19C and 19B in parallel to the MOS transistor 19, the non-uniformity of the impurity concentration on the wafer can be compensated for, thereby making it possible to make the characteristics of the two sets of MOS transistors the same. be.

[Problems with background technology]

In the conventional circuit having a four-turn configuration as shown in FIG. 2, the source regions are separated into two regions, 11 and IIB, so that the potentials of both source regions do not match and differ. For this reason, we took the trouble to install two MOS) transistors for each transistor 19 and 190'! , - and 19C and 19B to form two sets of MOS transistors, there is a drawback that the characteristics of both transistors differ due to the difference in source potential.

Further, in the conventional circuit, a pair of source regions 11A.

Two diffusion wiring layers 16A + 16B between JJBs
MOS transistor 19A#
The distance between the set of MOS transistors 19B and the set of MOS transistors 19C1J9D becomes large. .

Therefore, there is a drawback that the effect of compensating for the non-uniformity of impurity concentration in the wafer as described above is small.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to create a pair of MOS transistors in which individual elements are connected in parallel.
) An object of the present invention is to provide a MOS type semiconductor integrated circuit consisting of nine transistors, in which the difference in characteristics between two sets of elements is extremely small.

[Summary of the invention]

In order to achieve the above object, in the present invention, two drain regions are arranged along each long side of a pair of common source regions, and the drain regions are formed in two locations between the common source region and each drain region. Dirt electrodes are formed on the surface of the substrate to configure four MOS transistors, and the drain regions of each two MOB transistors are positioned point-symmetrically with respect to the center of the common source region. The conductor and dart electrodes are connected together to form two sets of two M(js transistors connected in parallel to each other).

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a four-turn plan view showing the element structure of the MOS type semiconductor integrated circuit according to the present invention, and similar to FIG. 2, the circuit of FIG. This is a case where the first part of the dynamic pair is actually integrated. In the figure, a P-type source region 21 is formed extending in a predetermined direction on an N-type semiconductor substrate u. 22B is formed in a pair of P-shaped drain regions 22 having the same area, keeping a predetermined distance from the long side located on the upper side in the figure among the pair of long sides of the source region 21 and keeping a predetermined interval from each other. has been done.

Similarly, each of the drain regions 22A is arranged at a predetermined distance from the long side of the source region 21 located on the lower side in the figure, and at a predetermined interval from each other.

A pair of P-type drain regions 22C having the same area as 22B,
22D is formed. Note that these source regions 21 and drain regions 22A.

~22D are usually formed simultaneously in - times of diffusion steps. The source region 21 and each drain region 221 to 22D
There is an insulating film jJ on the surface of the substrate between each
Each of A to 23D is deposited. Further, at a predetermined position on the substrate, a total of seven
~24G is formed in the P-type diffusion wiring layer 24 at a location.

Each of the above? -) On the insulating films 23A to 23D, each of the aluminum ff-) electrodes 25 to 25D are deposited, and furthermore, two of these electrodes 25A to 25D are
The two electrodes 25A and 25C are extended in the left direction in the figure, and their tips are connected to the respective diffusion wiring layers 2 at the two locations above.
4 and 24C, respectively. In addition, the remaining 92 electrodes 25B and 25D are extended in the right direction in the figure, and their respective tips are located at the two diffusion wiring layers 24B and 25D.
Each is connected to 4D.

The diffusion wiring layer 24 includes a wiring layer J made of aluminum.
It is connected to another wiring layer 26B via 1fA and the diffusion wiring layer 24E in series.

The diffusion wiring layer j4D is the wiring layer 2 made of aluminum.
6C and the diffusion wiring layer 24F are connected to the wiring layer 26B in series.

This wiring layer 26B is further connected to other circuit parts. The diffusion wiring layer 24C is connected to the aluminum wiring layer j6K via the aluminum wiring layer 26D and the diffusion wiring layer 34G in series. Further, the diffusion wiring layer 24B is connected to this wiring layer 26E, and this wiring layer 26g is further connected to other circuit parts. The above pair of drain regions 2
2A and 22D are connected via a wiring layer 26F made of aluminum, and this wiring layer 26F is further connected to other circuit parts. The pair of drain regions 22B and 2
2C through a wiring layer 26G made of aluminum, and this wiring layer 26.0 is further connected to other circuit parts. Further, the source region 21 is connected at its center to other circuit parts via a wiring layer 26H made of aluminum.

That is, in the circuit shown in the p4 turn plan view of FIG.
Four P-channel MO8) transistors 27A to J7D are integrated. And ? to the MOS transistors 27 which are in a point-symmetrical positional relationship with respect to one central point of the source region 21? Drain regions 22 and dirt electrodes 25 of FD, 27B and 2rC are connected to diffusion wiring layer 24. A pair of MOS transistors are connected via a wiring layer 26.

JFD is connected in parallel, and another pair of MOS transistors J and J7C are connected in parallel.

In a circuit with such a pattern configuration, four MOS
) The source regions of transistors m to 27D are common.

Therefore, unlike conventional circuits, there is no difference in characteristics between MOS transistors due to a difference in source potential.

Further, since the source region is shared, it is not possible to provide a diffusion wiring layer that crosses this source region 2, and each dirt electrode and pole 25A to 25D is connected to the center point a of the source region 21.
When viewed from the point, each extends outward. Therefore, the four MOS transistors 27A to 27D can be formed within a narrower range than before, and each MO8)
The distance between transistors j7A to j2rD can be reduced. This greatly increases the effect of compensating for the non-uniformity of the impurity concentration in the wafer as described above.As a result, a MOB formed by connecting two sets of elements (MOS) transistors j7A and m and transistors 21C and 21B in parallel, respectively. ) Differences in transistor characteristics can be made extremely small.

FIG. 5 shows another embodiment of the present invention, and shows the fourth embodiment.
FIG. 3 is a plan view of a main turn showing an element structure when the differential pair 1 portion is actually integrated, similar to the figure. In the embodiment shown in FIG. 4 above, the areas of all the drain regions jjA to 22D were made equal, but in this embodiment, the areas of the drain regions 22C and 22D were made equal to each other in order to reduce the overall area. This is set smaller than the case shown in FIG. 4 above.

In the circuit configured in this way, both drain regions 22A of MOS transistors j7A and 2rD.

Sum of areas of 22D and MOB) Lanzosta 27B and 2
Since the sum of the areas of both drain regions 22B and 22D of 7C is equal, the total area can be reduced without changing the characteristics.

6th line shows an example of application of this invention, and shows the above-mentioned first line.
FIG. 4 is a four-turn plan view showing an element structure when the differential amplifier circuit shown in the figure is actually integrated. In this application example circuit, the present invention is also applied to a current mirror circuit component composed of two N-channel MOS transistors 4.5. Since the differential pair 1 portion in this circuit is similar to that in FIG. 4, only the current mirror circuit portion will be described.

In the figure, υ is an alanyl region, and a P-shaped guard ring 31 having a uniform width is formed around this alanyl region υ. Alanyl region U above
An N-type source region 32 is formed above and extends in the same direction as the source region 21 . And this source area 3
33B is formed in a pair of N-shaped drain regions 33 having the same area, keeping a predetermined distance from the long side located on the upper side in the figure among the pair of long sides of 2, and keeping a predetermined interval from each other. . Similarly, each of the drain regions 33A is arranged at a predetermined distance from the long side of the source region 3 located on the lower side in the figure and at a predetermined interval from each other.

A pair of N-type drain regions 33C having the same area as 33B.
w33D is formed.

The source region 3 and each drain region, ? JA~33D
On the surface of the alanyl region -L between each
Insulating films 34A and 34D are deposited.

Further, the wiring layer 261 is extended, and this wiring layer 26F
is the in area 33B for the above pair of dots.

Connected to 3°3C. Furthermore, the wiring layer 26G is formed as an extension, and this wiring layer 26G is connected to the pair of drain regions 33 and 33D, and is connected to each of the above drain regions 33 and 33D.
-) It is also connected to a common dart electrode 35 commonly deposited on the insulating films 341 to 34D. Further, the source region 31 and the guard ring 31 are connected to a wiring layer 36 made of aluminum.

That is, P' of the circuit shown in the zigzag plan view of FIG.
Four N-channel MOS transistors LIJh to 37D are integrated within the well region circle, and the source region 31
M that is in a point-symmetrical positional relationship with respect to the center point of
OS transistors J7A and 37D and 36B and 36C
The respective drain regions are connected to each other via a wiring layer 26. In addition, the four MOS transistors J
7AγU” has a common dart electrode but is connected in parallel,
Also, another pair of MOS) Run Sister 37B, 37C
are connected in parallel. Therefore, even within this P-well region LJ, for the same reason as mentioned above, the difference in characteristics between the six pairs of MOS transistors can be made extremely small. An equivalent circuit of the circuit shown in the figure is shown in Figure 7.-.

〔Effect of the invention〕

As described above, according to the present invention, two drain regions are arranged along each long side of a pair of common source regions, and the drain regions are formed on the surface of the substrate between the common source region and each drain region. Dart electrodes are formed on the MOS transistors to form four MOS transistors, and two MOS transistors are arranged point-symmetrically to each other with respect to the center of the common source region. By connecting the meter electrodes to form two sets of elements in which two MOS transistors are connected in parallel to each other, it is possible to create an MOg type semiconductor integrated circuit in which the difference in characteristics between the two sets of elements is extremely small. can be provided.

[Brief explanation of drawings]

°Figure 1 shows MOS)? Fig. 2 is a 9-turn plan view showing the conventional element structure when the circuit shown in Fig. 1 is integrated, and Fig. 3 shows the impurity concentration in the wafer. Diagram showing the distribution state, 4th
The figure is a 4-turn plan view showing one embodiment of the present invention.
The figure is a 4-turn plan view showing another embodiment of Jin's invention, FIG. 6 is a 4-turn plan view showing another embodiment of Jin's invention,
FIG. 7 is an equivalent circuit diagram of FIG. 6. 20... N-type semiconductor substrate, 21... Source region,
22... Drain region, 23... Dirt insulating film, 2
4... Diffusion wiring layer, 26... Dirt electrode, 26...
・Wiring layer, 27...P channel MOS transistor,
30...P well region, 81... Guard ring, 3
2... Source region, 33...-Drain region, 34...
... f-to insulating film, 36... common f-) electrode, 36.
...Wiring layer, 32...N-channel MOS transistor.

Claims (1)

[Claims] forming a common source region extending in a predetermined direction on the semiconductor substrate; forming a total of four drain regions, two each along each pair of long sides of the common source region;
A P-meter electrode is formed on the substrate surface between the common source region and each of the four drain regions, and four M
OB) Two M transistors each forming a transistor and having a point-symmetrical positional relationship with respect to the center point of the common source region.
OB)? between the drain regions of the Nzosta and r-)
An MO characterized by connecting an electrode and an insulator.
Type 8 semiconductor integrated circuit.