JPS5994852A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5994852A JPS5994852A JP20475882A JP20475882A JPS5994852A JP S5994852 A JPS5994852 A JP S5994852A JP 20475882 A JP20475882 A JP 20475882A JP 20475882 A JP20475882 A JP 20475882A JP S5994852 A JPS5994852 A JP S5994852A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- back surface
- oxide films
- type
- strain stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は選択酸(1’法を用いた半導体装置の製造方法
にかかり、特に選択酸化によるi巌化膜形成時、基板結
晶に加わる歪応力に起因して発生する反り及び結晶欠陥
がデバイス特性全劣化させることを防止することが出来
る半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using a selective acid (1' method), and in particular, when forming an i-oxide film by selective oxidation, stress generated due to strain stress applied to a substrate crystal. The present invention relates to a method of manufacturing a semiconductor device that can prevent warpage and crystal defects from completely deteriorating device characteristics.
一般に選択酸化法を用いて製造された)(イボーラIC
の製造過程全表わした断韻図を第1図(a)〜(b)に
示す。先ず第1図(a)に示すように、P型半導体基板
1の上にN−型のエピタキシャル層2を成長する。次い
でエピタキシャル層の表面に極めて薄い酸化膜(SiU
z)3を介して窒化膜(SiaNs)を基板の表面に形
成し、この窒化膜4に所望のノくターンを選択エツチン
グにより形成する(第11(b))。さらに第1図(c
)VC示すように買化膜4以外の基板をP型基板1に達
するまで選択畝化を行ない、選択1夜化による厚い1反
化膜5にてエピタキシャル層全絶縁分離する。次いで分
離された領域2′に選択拡散技術によりP型のベース拡
散領域6N +型コレクタ拡散領域7、さらにベース拡
散領域6中にN+型エミッタ領域8を拡散することによ
りトランジスタが形成される(i1図(d))。(generally produced using selective oxidation method) (Ibora IC
Figures 1(a) and 1(b) are diagrams showing the entire manufacturing process. First, as shown in FIG. 1(a), an N- type epitaxial layer 2 is grown on a P-type semiconductor substrate 1. Next, an extremely thin oxide film (SiU) is applied to the surface of the epitaxial layer.
z) A nitride film (SiaNs) is formed on the surface of the substrate via the nitride film 4, and a desired notch is formed in the nitride film 4 by selective etching (No. 11(b)). Furthermore, Figure 1 (c
) As shown in VC, selective ridge formation is performed on the substrates other than the protective film 4 until it reaches the P-type substrate 1, and the entire epitaxial layer is insulated and separated by a thick single-layer film 5 formed by selective heating. Next, a transistor is formed by diffusing a P type base diffusion region 6N + type collector diffusion region 7 into the separated region 2', and further diffusing an N + type emitter region 8 into the base diffusion region 6 using a selective diffusion technique (i1 Figure (d)).
この場合選択酸化による厚い酸化膜5の形成時裏面全面
にも同時にj9い酸化膜5’75Et杉成され(第1図
(C) ) 、基板表口の厚いL’&イヒ膜5の面積よ
りはるかに基板裏面の厚い酸化膜5′の面状の方〃(大
きくなる為、裏面の酸化膜による膨張力の方が表面より
勝り基板を凹型に反らせる。この為基板中央部に歪応力
が集中して結晶欠陥9を相生させデバイス特性を劣化さ
せる。In this case, when the thick oxide film 5 is formed by selective oxidation, a thin oxide film 5'75Et is simultaneously formed on the entire back surface (Fig. 1(C)), which is larger than the area of the thick L'&Ihi film 5 on the front surface of the substrate. The planar shape of the thick oxide film 5' on the back side of the substrate is much larger (because it is larger, the expansion force due to the oxide film on the back side is stronger than that on the front side, causing the board to warp in a concave shape.For this reason, strain stress is concentrated in the center of the board. This causes crystal defects 9 to coexist and deteriorates device characteristics.
この様に基板に発生する反り及び結晶欠陥は、選択酸化
の1夜化膜厚及びパターン面績等に強く影響されるため
製造条1牛の選定に困難があった。As described above, warpage and crystal defects occurring in the substrate are strongly influenced by the overnight film thickness of selective oxidation, pattern surface quality, etc., so it was difficult to select one manufacturing process.
本発明は、上記した問題点に対処してなされたもので選
択は化による悪影響を除き、デバイス特1生の良好な半
導体装置の製造方法を提供するにある。The present invention has been made in response to the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device that eliminates the adverse effects of selection and has good device characteristics.
不発明の特徴は半導体基板全選択酸化による厚い酸化膜
を形成する際、あらかじめ裏面に窒化膜やタングステン
等の高温耐熱金@等の耐ば化物を形成しするか石英板等
と密着させるなど裏面に厚い酸化膜全形成しにくい状態
vcすることにより、歪応力の発生を押え、歪応力に起
因する基板の反り及び結晶欠陥を防止することにある。The unique feature of this invention is that when forming a thick oxide film by selectively oxidizing the semiconductor substrate, it is necessary to form a nitride film or a heat-resistant metal such as tungsten on the back surface in advance, or to make it adhere to a quartz plate, etc. By creating a state in which it is difficult to fully form a thick oxide film, the purpose is to suppress the generation of strain stress and prevent warping of the substrate and crystal defects caused by strain stress.
以下図ll1Iを参照し本発明の詳細な説明第2図(a
)〜((1)は本発明の一果施例説明のための半導体装
置の・膚造工程断面図である。先ず第2図(a)に示す
ように、P型のシリコン基板1金準備しその上VCN一
型のエピタキシャル層2全成長する。Detailed explanation of the present invention with reference to Figure ll1I below Figure 2 (a
)~((1) is a cross-sectional view of the fabrication process of a semiconductor device for explaining an embodiment of the present invention. First, as shown in FIG. 2(a), a P-type silicon substrate is prepared. A VCN-type epitaxial layer 2 is entirely grown on top of this.
次に、エピタキシャル層2全有する基板10表面及び裏
面VC0.03μ程度の厚さの極めて薄い酸化膜3を膨
成し、さらにその上に畳化11〆4を形成した後、基板
表面のみ窒化膜全絶縁領域に対応したパターンに選択エ
ツチングして除去する(第2図(b))。Next, an extremely thin oxide film 3 having a thickness of about 0.03 μm is expanded on the front and back surfaces of the substrate 10 having the entire epitaxial layer 2, and a layer 11 and a layer 4 are formed thereon, and then a nitride film is formed only on the surface of the substrate. A pattern corresponding to the entire insulating region is selectively etched and removed (FIG. 2(b)).
さらに第2図(C) Kポアように選択酸化を行なって
窒化膜を有する領域以外の部分の基板表面全P型基板i
vc達するまで例えば1.5μ程度の選択酸化を行ない
、選択酸化による厚い酸化膜5Vcてエピタキシャル層
を絶縁分離する。In addition, selective oxidation is performed like the K pore in FIG.
For example, selective oxidation of about 1.5 μm is performed until vc is reached, and the epitaxial layer is insulated and isolated by a thick oxide film 5Vc by selective oxidation.
次に分離された領域2′に選択拡散技術によりP型のベ
ース拡散領域6sN”!J!コレクタ拡散領域7、さら
にベース拡散領域6中Vr−N+型エミッタ領域8を拡
散することにょクトランジスタが形成される(第2図(
d))。Next, a P-type base diffusion region 6sN"!J! collector diffusion region 7, and further a Vr-N+ type emitter region 8 in the base diffusion region 6 are diffused into the separated region 2' by a selective diffusion technique. formed (Fig. 2 (
d)).
以上説明したような方法だと選択酸化による厚い酸化膜
5全形成する際裏面に残した窒化膜にょり裏面にはさほ
ど酸化膜が形成されない(第2図(C))。この為基板
裏面の膜質にほとんど変化がなく又、基板表lでもパタ
ーンにより厚い酸化膜5の形成時に発生する歪応力を吸
収出来ることから基板に歪応力が発生しにくくなる。従
って歪応力に起因する基板の反り及び結晶欠陥の発生が
防止できる為、デバイス特性の良好な半導体装直音製造
することができる。With the method described above, the oxide film is not formed much on the back surface due to the nitride film left on the back surface when the thick oxide film 5 is entirely formed by selective oxidation (FIG. 2(C)). For this reason, there is almost no change in the film quality on the back side of the substrate, and since the strain stress generated when forming the thick oxide film 5 can be absorbed by the pattern on the front side of the substrate, strain stress is less likely to occur on the substrate. Therefore, it is possible to prevent warping of the substrate and the occurrence of crystal defects due to strain stress, and therefore it is possible to directly manufacture semiconductor devices with good device characteristics.
以上説明したように選択酸化による悪影響を除き、デバ
イス特性の優れた半導体装置の製造方法を提供するもの
である。As explained above, the present invention provides a method of manufacturing a semiconductor device with excellent device characteristics by eliminating the adverse effects of selective oxidation.
第1図(a)〜(d)は従来の半導体装置の製造方法と
それに伴う結晶欠陥の発生状況を示す製造工程模式断面
図、第2図(a)〜(d)は本発明の一夷′倫例による
半導体装置の製造方法を示す製造工程模式断l図である
。
1・・、・・・P型シリコン基板、2・・・・・・N−
型エピタキシャル層、2′・・・・・・絶縁分離された
エピタキシャル層領域、3・・・・・・極めて薄い酸化
膜、4・・・・・・窒化膜、5・・・・・・選択酸化に
よる厚い酸化膜、5′・・・・・・選択は化により裏面
に形成した厚い酸化膜、6・・・・・・P型のベース拡
散領域、7・・・・・・N+型コレクタ拡赦碩域、8・
・・・・・N十型エミッタ領域。FIGS. 1(a) to (d) are schematic cross-sectional views of the manufacturing process showing the conventional manufacturing method of a semiconductor device and the occurrence of crystal defects associated therewith, and FIGS. 2(a) to (d) are one example of the present invention. FIG. 1 is a schematic cross-sectional view of a manufacturing process showing a method of manufacturing a semiconductor device according to the Rin Example. 1...P-type silicon substrate, 2...N-
type epitaxial layer, 2'... isolated epitaxial layer region, 3... extremely thin oxide film, 4... nitride film, 5... selection Thick oxide film formed by oxidation, 5'... Thick oxide film formed on the back surface by oxidation, 6... P type base diffusion region, 7... N+ type collector Amnesty area, 8.
...N-type emitter region.
Claims (1)
あらかじめ基板元素窒化膜や高温耐熱金属等の耐酸化物
層を形成するか、裏面を石英板などの耐酸化物板と密着
させるなど、裏面を表面より酸化膜が形成され難い状態
にすることを特徴とする半導体装置の製造方法。When selectively converting the surface of a semiconductor substrate, it is necessary to form an oxide-resistant layer such as a substrate element nitride film or a high-temperature heat-resistant metal on the back side of the substrate in advance, or to bring the back side into close contact with an oxide-resistant plate such as a quartz plate. 1. A method of manufacturing a semiconductor device, comprising: bringing the surface of the semiconductor device into a state where it is more difficult to form an oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20475882A JPS5994852A (en) | 1982-11-22 | 1982-11-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20475882A JPS5994852A (en) | 1982-11-22 | 1982-11-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5994852A true JPS5994852A (en) | 1984-05-31 |
Family
ID=16495857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20475882A Pending JPS5994852A (en) | 1982-11-22 | 1982-11-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5994852A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100430582B1 (en) * | 2001-12-20 | 2004-05-10 | 동부전자 주식회사 | Method for manufacturing semiconductor device |
-
1982
- 1982-11-22 JP JP20475882A patent/JPS5994852A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100430582B1 (en) * | 2001-12-20 | 2004-05-10 | 동부전자 주식회사 | Method for manufacturing semiconductor device |
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