JPS5992562A - Formation of buried channel - Google Patents

Formation of buried channel

Info

Publication number
JPS5992562A
JPS5992562A JP57202993A JP20299382A JPS5992562A JP S5992562 A JPS5992562 A JP S5992562A JP 57202993 A JP57202993 A JP 57202993A JP 20299382 A JP20299382 A JP 20299382A JP S5992562 A JPS5992562 A JP S5992562A
Authority
JP
Japan
Prior art keywords
bccd
substrate
impurity concentration
ion implantation
smear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57202993A
Other languages
Japanese (ja)
Inventor
Toshihiro Kuriyama
俊寛 栗山
Yoshimitsu Hiroshima
広島 義光
Shigenori Matsumoto
松本 茂則
Hiroko Fujiwara
宏子 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57202993A priority Critical patent/JPS5992562A/en
Publication of JPS5992562A publication Critical patent/JPS5992562A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14887Blooming suppression

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To contrive to optimize conditions for driving a BCCD device by a method wherein the impurity concentration of a BCCD part is selectively increased by performing As and B ion implantation into a semiconductor substrate at the same time by means of the same mask. CONSTITUTION:P<+> channel stoppers 2, the BCCD parts 3, photo diodes 4 are formed in the p type substrate 1. The BCCD parts 3 are formed by the simultaneous ion implantation of As<+> and B<+> by means of the same mask. Then, a shallow part is n, and a deep part is p<+>. That the substrate impurity concentration under the BCCD is high and p<+> means that it functions as a barrier to a smear phenomenon caused by the mixture of a signal charge, generated at depth of the substrate in an interline transfer system image pick-up element, into the BCCD by lateral diffusion. As a result, the smear can be reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、埋め込みチャンネルの形成方法に関し、特に
BCCDのしきい値電圧vTに対する埋め込み層の空乏
化電圧の低下が図れ、またBCCDを用いた撮像素子に
おけるスミア低減が図れる不純物プロファイルを持った
埋め込みチャンネルの形成方法を提供する0 従来例の構成とその問題点 インターライン転送方式固体撮像素子において、ダイナ
ミックレンジを大きくしたい場合に特に問題となるのは
垂直BCCDの量大転送電荷量とス2ベーレ゛ ミア現象が上げられる。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming a buried channel, and in particular, to a method for forming a buried channel, which can reduce the depletion voltage of a buried layer with respect to the threshold voltage vT of a BCCD, and also to an image sensor using a BCCD. To provide a method for forming a buried channel with an impurity profile that can reduce smear in conventional configurations and their problems In interline transfer type solid-state image sensors, when it is desired to increase the dynamic range, vertical The large amount of transferred charge and the swell beam phenomenon of BCCD are mentioned.

転送電荷量を上げるためには、埋め込みチャンネルのド
ーズ量を上げればよいが、そうすると空乏化電圧φmi
nが高くなり、素子の駆動条件に制約を受ける。そこで
空乏化電圧φminをおさえるために低抵抗基板を用い
るとしきい値電圧VTが高くなる。これも素子の駆動条
件に制約を与える。
In order to increase the amount of transferred charge, it is sufficient to increase the dose of the buried channel, but in this case the depletion voltage φmi
As n becomes higher, the driving conditions of the element are restricted. Therefore, if a low resistance substrate is used to suppress the depletion voltage φmin, the threshold voltage VT will increase. This also imposes restrictions on the driving conditions of the element.

以上のように、空乏化電圧φmin、 Lきい値電圧V
Tは基板の不純物濃度と密接な関係があり、それぞれの
駆動条件に制約を受け、特に素子の特性を劣化させるこ
となく低電圧化を図ることが困難であった。
As described above, the depletion voltage φmin, the L threshold voltage V
T is closely related to the impurity concentration of the substrate, and is constrained by each driving condition, making it particularly difficult to lower the voltage without deteriorating the characteristics of the element.

発明の目的 本発明は上記欠点を解消するためになされたもので、B
CCD部の基板不純物濃度を選択的に高くする方法によ
り、BCCDデバイスの駆動条件の最適化を図ることを
目的とする。
Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks, and
The purpose of this invention is to optimize the driving conditions of a BCCD device by a method of selectively increasing the substrate impurity concentration in the CCD section.

発明の構成 本発明は半導体基板に同一マスクによりAsとBを同時
にイオン注入することによりBCCD部3 ページ の不純物濃度を選択的に高くするものである。
Structure of the Invention The present invention selectively increases the impurity concentration in the BCCD section 3 by simultaneously implanting As and B ions into a semiconductor substrate using the same mask.

実施例の説明 以下図面を参照しながら本発明の詳細な説明する。第1
図に示す不純物濃度プロファイルを形成する場合、P+
とB+という組み合せも考えられる。しかしこの場合、
P+とB+の拡散係数がほぼ同程度なので、B+の拡散
長をN型拡散層に比べて延ばす必要上B+のドライブイ
ンの工程が必要となる。すなわち、B+をイオン注入し
、ドライブインを行い、その後P+のイオン注入を行う
という順序で形成する必要がある。
DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to the drawings. 1st
When forming the impurity concentration profile shown in the figure, P+
A combination of and B+ is also possible. But in this case,
Since the diffusion coefficients of P+ and B+ are approximately the same, a drive-in process for B+ is required to extend the diffusion length of B+ compared to the N-type diffusion layer. That is, it is necessary to perform the formation in the order of B+ ion implantation, drive-in, and then P+ ion implantation.

ところが、本発明のようにA8+とB+の組み合せを用
いれば八8+とB+の拡散係数の違いにょシ同時にイオ
ン注入を行なっても以後のプロセスによる熱履歴によっ
て、As+、B+それぞれは、第2図の様な濃度プロフ
ァイルとなり、それらが合成されて第1図の実効的なプ
ロファイルとなる。
However, if a combination of A8+ and B+ is used as in the present invention, due to the difference in the diffusion coefficients of 88+ and B+, even if ions are implanted at the same time, As+ and B+ will differ depending on the thermal history of the subsequent process, as shown in Figure 2. This results in a concentration profile like this, and these are combined to form the effective profile shown in FIG.

前述の戸とB+による組み合せのものに比べて、イオン
注入も同一マスクで行い、ドライブインも不要であるの
で、プロセスが簡単である。また従来からある埋め込み
層に単一の不純物(P+、Am”)を用いるものと比べ
ても、B+イオン注入が工程が1つ増えるだけで済む。
Compared to the combination of the door and B+ described above, ion implantation is performed using the same mask and no drive-in is required, so the process is simpler. Furthermore, compared to the conventional method in which a single impurity (P+, Am'') is used in the buried layer, only one additional process is required for B+ ion implantation.

次に本発明を用いてインターライン転送方式撮像素子を
P型基板上に形成する場合の具体的な実施例を説明する
Next, a specific example will be described in which an interline transfer type image sensor is formed on a P-type substrate using the present invention.

(実施例り 第3図は、本発明の方法により形成した撮像素子の断面
図を示す。同図において、1はP型基板、2 (d、 
P+チャンネルストソバ−1S ij B CCD 部
、4はホトダイオードを示している。同素子において、
8000部3は同一マスクによりA8+とB+の同時イ
オン注入を行なうことにより浅い部分はn、深い部分は
P+になっている。
(Example) FIG. 3 shows a cross-sectional view of an image sensor formed by the method of the present invention. In the figure, 1 is a P-type substrate, 2 (d,
In the P+ channel source bar-1S ij B CCD section, 4 indicates a photodiode. In the same element,
In the 8000 part 3, ions of A8+ and B+ are simultaneously implanted using the same mask, so that the shallow part is n and the deep part is p+.

第3図に示すようにBCCD下の基板不純物濃度が高く
P+であるということは、インターライン転送方式撮像
素子における、基板深部で発生した信号電荷が、横方向
拡散により、BCCDに混入することによって起こるス
ミア現象に対して、バリアーとして働き、その結果スミ
アを低減させ5 ページ ることかできることになる。
As shown in Figure 3, the fact that the substrate impurity concentration under the BCCD is high and P+ means that signal charges generated deep in the substrate in the interline transfer type image sensor mix into the BCCD due to lateral diffusion. It acts as a barrier against the smear phenomenon that occurs, and as a result, the smear is reduced and 5 pages can be printed.

本実施例によるとAs”、B+のドーズ量の絶対値、そ
れらの比率を変えることにより、BCCD部の基板不純
物濃度、及び埋め込み層の不純物濃度を、埋め込み層の
横方向拡散を延ばすことなく認意に選択することができ
る。その結果最大転送電荷量を増大でき、空乏化電圧を
下げることが出来る。そのためしきい値電圧vTと空乏
化電圧φminの最適化が図れ、高抵抗基板を用いるこ
とにより、低電駆動が可能となる。
According to this embodiment, by changing the absolute values of the doses of As'' and B+ and their ratio, the substrate impurity concentration of the BCCD part and the impurity concentration of the buried layer can be checked without prolonging the lateral diffusion of the buried layer. As a result, the maximum transfer charge amount can be increased and the depletion voltage can be lowered.Thus, the threshold voltage vT and depletion voltage φmin can be optimized, and a high resistance substrate can be used. This enables low-current driving.

(実施例2) 固体撮像素子の一つの構造として、過剰信号電荷を基板
方向に排出するための第4のウェル構造がある。
(Example 2) One structure of a solid-state imaging device includes a fourth well structure for discharging excess signal charges toward the substrate.

同図において、21はn型基板、22はB CCD部、
23はホトダイオード部である。
In the figure, 21 is an n-type substrate, 22 is a B CCD section,
23 is a photodiode section.

これは、ホトダイオード部22のウェルは、バックバイ
アスで完全空乏化し、BCCD部23のウェルは、その
電圧で空乏化しないような、ウェルの濃度、横方向拡散
長xiが必要である。
This requires a well concentration and a lateral diffusion length xi such that the well of the photodiode section 22 is completely depleted by back bias, and the well of the BCCD section 23 is not depleted by that voltage.

6 ベージ゛ 本発明を用いてこのよう々ウェルを形成する方法を第6
図(a)、 (b)により説明する。まず、第6図(a
)に示すようにホトダイオード部33の上記条件を満た
す濃度の低いp型ウェル34をn型基板31に形成して
おいて、第5図すに示すようKBCCD部32のウェル
は空乏化しない濃度になるよう妬B+のドーズ量を増や
すことにより可能となる。
6. The method for forming wells using the present invention is described in the sixth section.
This will be explained with reference to Figures (a) and (b). First, Figure 6 (a
), a p-type well 34 with a low concentration that satisfies the above conditions for the photodiode section 33 is formed on the n-type substrate 31, and the well of the KBCCD section 32 is formed with a concentration that does not cause depletion, as shown in FIG. This can be done by increasing the dose of Envy B+ so that it becomes possible.

この方法によればECCD部32のウェルの横方向の広
がりもせいぜい2μ程度なのでセルファラインでウェル
を形成できる。
According to this method, the lateral extent of the well of the ECCD section 32 is at most about 2 μm, so the well can be formed in a self-aligned manner.

さらにプロセスの最初に上記の条件のウェルを形成する
方法ではBCCD部のウェルは濃度を高くする必要上横
方向拡散長xjが伸び横方向の広がりが無視できなくな
り、従来例を示す第4図のような形となるが、この発明
方法によれば、第5図(b)に示すように横方向の広が
りが低くおさえられる。
Furthermore, in the method of forming a well under the above conditions at the beginning of the process, the concentration of the well in the BCCD region must be increased, and the lateral diffusion length xj increases, and the lateral spread cannot be ignored. However, according to the method of this invention, the spread in the lateral direction can be suppressed to a low level, as shown in FIG. 5(b).

発明の詳細 な説明したように本発明の方法によれば、簡単な方法で
BCCDの空乏化電圧の低下が図れ、7ベーン またBCCDを用いた撮像素子のスミアの低減が図れる
もので工業上の利用価値が高い。
As described in detail, according to the method of the present invention, the depletion voltage of a BCCD can be reduced in a simple manner, and smear in an image sensor using a 7-vane or BCCD can be reduced. Highly useful.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の方法による不純物濃度のプロファイル
を示す図、第2図は、八8+とB+の個々の不純物の濃
度プロファイルを示す図、第3図は本発明の方法で形成
したインターライン転送方式撮像素子の断面図、第4図
は過剰電荷を基板へ排出するための従来のp型ウェル構
造の断面図、第6図(a) 、 (b)は本発明の方法
により形成した過剰電荷を基板へ排出するためのp型ウ
ェル構造の断面図である。 1・・・・・・p型基板、2・・・・・・チャンネルス
トッパー、3.32・・・・・・BCCD部、4,33
・・・・・・ホトダイオード。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第 3 図
FIG. 1 is a diagram showing the impurity concentration profile formed by the method of the present invention, FIG. 2 is a diagram showing the concentration profile of individual impurities of 88+ and B+, and FIG. 3 is a diagram showing the interline formed by the method of the present invention. FIG. 4 is a cross-sectional view of a conventional p-type well structure for discharging excess charge to the substrate, and FIGS. FIG. 2 is a cross-sectional view of a p-well structure for draining charge to a substrate. 1...P-type substrate, 2...Channel stopper, 3.32...BCCD section, 4, 33
・・・・・・Photodiode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体基板に同一マスクによりA8とBを同時にイオン
注入を行なうことにより、BCCD部の不純物濃度を選
択的に高くすることを特徴とする埋め込みチャンネルの
形成方法0
Method 0 of forming a buried channel characterized by selectively increasing the impurity concentration in the BCCD portion by simultaneously implanting A8 and B ions into a semiconductor substrate using the same mask.
JP57202993A 1982-11-18 1982-11-18 Formation of buried channel Pending JPS5992562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57202993A JPS5992562A (en) 1982-11-18 1982-11-18 Formation of buried channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57202993A JPS5992562A (en) 1982-11-18 1982-11-18 Formation of buried channel

Publications (1)

Publication Number Publication Date
JPS5992562A true JPS5992562A (en) 1984-05-28

Family

ID=16466550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57202993A Pending JPS5992562A (en) 1982-11-18 1982-11-18 Formation of buried channel

Country Status (1)

Country Link
JP (1) JPS5992562A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53138284A (en) * 1977-05-09 1978-12-02 Fujitsu Ltd Manufacture for semiconductor part
JPS57162364A (en) * 1981-03-30 1982-10-06 Matsushita Electric Ind Co Ltd Solid state image pickup device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53138284A (en) * 1977-05-09 1978-12-02 Fujitsu Ltd Manufacture for semiconductor part
JPS57162364A (en) * 1981-03-30 1982-10-06 Matsushita Electric Ind Co Ltd Solid state image pickup device

Similar Documents

Publication Publication Date Title
US5446297A (en) CCD type solid-state image sensor
EP0605958B1 (en) Solid state imaging device having high-sensitivity and low-noise characteristics by reducing electrostatic capacity of interconnection
EP0059547A1 (en) Clock controlled anti-blooming for virtual phase CCD&#39;s
JP2964571B2 (en) Solid-state imaging device
US5804844A (en) Solid-state imager with container LOD implant
JPS5992562A (en) Formation of buried channel
JP2964541B2 (en) Vertical overflow drain type solid-state imaging device
JP2573582B2 (en) Method for manufacturing solid-state image sensor
JP2909158B2 (en) Charge coupled device
JPH08288492A (en) Solid-state image pickup device and its manufacture
JPS6393149A (en) Solid-state image sensing device and manufacture thereof
JP3176300B2 (en) Solid-state imaging device and manufacturing method thereof
JPH0697416A (en) Solid-state image sensing device and manufacture thereof
JPH0424871B2 (en)
JPS63155759A (en) Image sensor
JPS62269355A (en) Solid-state image sensing element
JPS6149462A (en) Solid-state image pickup device
JPS61229356A (en) Solid-state image pickup device
JPS61124169A (en) Manufacture of solid image sensor
JPS62234368A (en) Photodetector
JP2005209673A (en) Photoelectric converter, method of manufucturing the same, and solid state imaging device
JPH0570947B2 (en)
JPH0653474A (en) Solid state image sensor and fabrication thereof
JPH0219632B2 (en)
JPH08186243A (en) Solid image pickup element