JPS61229356A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To suppress stably and efficiently the blooming phenomenon in a solid-state image pickup device by a method wherein the device is constituted in such a structure that the P-type well layers are eliminated, the opening part of each P<+> buried layer is completely covered with each N<+> photo diode and the excess charge is swept out by controlling the size of the opening part of each buried layer and the impurity concentration of the buried layer. CONSTITUTION:P<+> buried layers 2 are formed in an N-type semiconductor substrate 1, and after that, the layers 2 are covered and an N-type semiconductor layer is formed on the whole surface of the substrate 1. Then, P<+> regions 3 for channel isolation and insulating films 9 for element isolation are formed. Then, P-type ions for an enhancement type readin gate (a) are implanted, and furthermore, N-type ions for transfer gate and N-type well are implanted, and readin gates 7 and N-type well layers 8 are formed. Then, gate insulating films, common polycrystalline Si gate electrodes 5 and insulating films 10 for protection are formed, and after that, an N<+> photo diode (charge storage part) 4 is formed on the opening part 12 of each layer 2 by implanting N-type ions. The size of the opening part 12 of each layer 2 and the impurity concentration of the layer 2 are respectively controlled at the optimum value.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a solid-state imaging device equipped with a blooming phenomenon suppressing structure.

2. Description of the Related Art In a conventional solid-state imaging device, as a structure for suppressing the blooming phenomenon, as shown in FIG. There is a method of forming a so-called vertical npn structure of 1 directly under the n" diode 4. In this method, a reverse bias voltage is applied between the p well 2o and the n type semiconductor substrate 1, and the p well 20 is completely depleted. Read the potential when the signal charge is transferred to the gate 6I.
By setting the potential higher than the potential directly below L, excess charges generated when strong light is incident are swept out to the n-substrate, thereby suppressing blooming (for example, Japanese Patent Laid-Open No. 125962/1982). In FIG. 6, 2 is a P buried layer, 3 is a P region for channel isolation, 4 is an n buried layer, 6b is a transfer gate, 8 is an n well, 9 is an insulating film for element isolation, and 1o is for protection. The insulating film 11 is a light shielding film.

Problems to be Solved by the Invention In such a conventional device, in order to optimize the potential of the P well, the depth of the P well layer, the impurity concentration, the depth of the n+ photodiode part, and the depth of the P buried layer must be adjusted. The controllability was complicated, as it was necessary to take into consideration the impurity concentration of the semiconductor and the accuracy of mask alignment with the n+ photodiode section.

The present invention has been made in view of this problem, and an object of the present invention is to provide a pluming phenomenon suppressing structure that has a simple structure and is easy to control.

Means for Solving the Problems In order to solve the above problems, the present invention eliminates the P well layer, completely covers the opening of the P buried layer with the n+ photodiode, and allows the n+ photodiode to reach the surface of the n-type semiconductor substrate. , the potential for sweeping out excess charge is controlled by the size of the opening in the P buried layer and the impurity concentration.

Effect of the present invention is based on the above-described structure. When a reverse bias voltage is applied between the P buried layer and the n substrate, the P buried layer contacts the female diode due to the influence of the aperture size and impurity concentration. The n-type semiconductor substrate region is depleted and has an arbitrary potential, making it possible to sweep out only excess charge to the substrate.

Embodiment FIG. 1 is a cross-sectional structural diagram showing an embodiment of the pluming phenomenon suppressing structure of the present invention. The same components as in Figure 3 are numbered the same, 1 is the n-type semiconductor substrate, 2 is the ? 3 is a buried layer, 3 is a P increase area for channel separation, 4 is an n+ photodiode region which is a charge storage region, 6 is a common polysilicon gate electrode for the read gate and transfer gate, and furthermore, through the gate insulating film 6, an enhancement type A read gate 7, an n-well layer 8, a thick insulating film 9 for element isolation, a protective insulating film 10, and a light shielding film 11 are provided.

The difference between this conventional example shown in FIG. 1 and FIG. 6 is that there is no P well layer 2o, and the n+ photodiode 4 is formed so as to completely cover the opening of the P well layer 2. .

This forming method will be explained using FIG. 2.

First, a high-concentration P-type impurity layer is formed on the n-type semiconductor substrate 1 by ion implantation or thermal diffusion in the region corresponding to the buried layer 2 through the oxide film mask 19 using the usual IJ soger flow technique. (Figure 2(a)). Thereafter, an n-type semiconductor layer 22 of the same or opposite conductivity type as the substrate, in this case the same, is formed by, for example, vapor phase growth.

The heavily doped P-type buried layer 2 is diffused into the n-type semiconductor layer 20 by subsequent heat treatment, resulting in a p+J layer as shown in FIG. 2(b).
Openings 12 in the embedded layer are formed. Next, the selective oxidation method and B
+ Using the ion implantation method, a channel isolation layer P region 3 and a thick insulating film 9 for element isolation are formed (FIG. 2(C))
). Next, as shown in Figure 1, P-type ion implantation is performed for the engineering type read gate, and then n-type ion implantation is performed for the n-well for the transfer gate.
7. Next, a gate insulating film 6 and a common polysilicon gate electrode 6 for forming an n-well layer 8 are formed, and the surface is oxidized to form a protective insulating film 1o. Next, n-type ions are implanted to form a cod photodiode 4 so as to reach the n-type semiconductor substrate, which is the opening of the P buried layer.

Next, the operation of suppressing the pluming phenomenon in the solid-state imaging device of this embodiment will be explained.

Figure 3 shows I-I directly below the n+ photodiode shown in Figure 1.
It shows the potential distribution on the line, that is, in the depth direction. Now the first
The potential of the channel separation layer P region 3 shown in the figure is set to the reference potential (
In this case, it is set to 0 volts). If the potential of the read gate 7 is Vrn and the threshold voltage is 7, then the n+ photodiode 4 is set at a potential of VTR-7. Furthermore, when the reverse bias voltage applied to the P00 buried layer and the n-type semiconductor substrate 1 is increased from the low voltage shown by the curve 3o to a higher reverse bias voltage, the opening 12 of the P00 buried layer 2 is increased as shown by the curve 31. The surface of the n-type semiconductor substrate 1 in contact with the n+ photodiode 4 is completely depleted. When the n+ photodiode 4 is irradiated with light and signal charges are accumulated, the potential of the n+ photodiode 4 decreases as shown by a curve 31 to a curve 32, and finally the potential of the n+ photodiode 4 and the n-type semiconductor substrate 1 decreases as shown by a curve 33. is in the forward direction, and all further generated signal charges flow into the n-type semiconductor substrate 1. That is, directly below the reading gate shown in Figure 1, directly below the p++ area 3 for channel separation, and the n+ photodiode 4 (not shown).
The surface potential of all the areas surrounding the n+ photodiode 4
By applying a reverse bias voltage to the n-type semiconductor substrate 1 and the P+ buried layer 2 so that the junction potential 34 formed between the n-type semiconductor substrate 1 and the n-type semiconductor substrate 1 becomes high, the excess charge generated in the n+ photodiode 4 is completely removed. It can be swept out onto an n-type semiconductor substrate. In particular, the setting of the junction potential between the n+ photodiode 4 and the n-type semiconductor substrate 1, which is important in the present invention, will be explained.

FIG. 4 (IL), (b), and (0) are the openings 1 of the P+ buried layer 2 directly under the n+ photodiode shown in FIG.
This diagram schematically shows the potential distribution on the nn line of 2, that is, in the lateral direction, with respect to the dimensional change (12a, 12b) of the opening 120 of the P+ buried layer 2, and the potential of the P+ buried layer 2 is now referenced. potential (here 0 volts), P+ buried layer 2 and n
A constant reverse bias v! between type semiconductor substrates 1. When l is applied, the potential distribution becomes 4o in the case where the opening size is wide and the surface of the n-type semiconductor substrate is not completely depleted and there is a depletion layer 21 with the P+ buried layer 2 as shown in FIG. 4(b). Same figure (&
)). However, as shown in Figure 4(C), the opening size is 12b.
When the width is narrowed as shown in FIG. 1, the surface of the In type semiconductor substrate 1 is completely depleted due to the two-dimensional effect, and the potential distribution 4° approaches O volts (FIG. 2(a)). P41 is the reason why this potential distribution becomes low.
The same can be said when the impurity concentration of the 1-layer 2 is increased. Due to this two-dimensional effect, when the charge (here, electrons) in the n+ photodiode is small, it becomes a barrier, and when a large amount is stored, it becomes a potential curve 33 in FIG. 3. Like this P+
By controlling the size of the opening in the buried layer 2 and the impurity concentration, the junction potential between the n+ photodiode and the surface of the n-type semiconductor substrate can be set arbitrarily, making it possible to sweep out excess charge to the substrate. .

This simple structure and operation can completely suppress the pluming phenomenon.

Here, the n-type semiconductor layer 22 may be of P type. Also, the film thickness is n+
It is necessary to take the depth of the photodiode into account when setting 90
．． 5-2 microns is preferred. As can be seen from the structure shown in FIG. 1, the precision of mask alignment between the opening in the p+s layer and the n+ photodiode is not required.

Effects of the Invention As described above, according to the present invention, the pluming phenomenon can be suppressed stably and accurately with an extremely simple structure, and is extremely useful in practice.

[Brief Description of the Drawings] Fig. 1 is a cross-sectional view of a solid-state imaging device that suppresses the pluming phenomenon in an embodiment of the present invention, Fig. 2 is a diagram showing the potential distribution in the line nn direction, Fig. 6 is a cross-sectional view of a conventional solid-state imaging device. 1... Semiconductor substrate, 2... Buried layer,
4... Charge storage region, 7... Enhancement type read gate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5

Claims (2)

[Claims] (1) A buried layer having a conductivity type opposite to that of the substrate is partially formed on the main surface of a semiconductor substrate, and a semiconductor layer having one conductivity type is formed over the entire main surface of the substrate so as to cover the buried layer. and a device for forming a charge storage region on the main surface of the semiconductor layer where the buried layer is not formed, and transferring and reading signals from the charge storage region on the semiconductor layer where the buried layer is formed. A solid-state imaging device characterized by: (2) The solid-state imaging device according to claim 1, wherein the charge storage region reaches at least the main surface of the semiconductor substrate on which no buried layer is formed.