JPS599111B2 - Manufacturing method of planar magnetic bubble element overlay - Google Patents
Manufacturing method of planar magnetic bubble element overlayInfo
- Publication number
- JPS599111B2 JPS599111B2 JP4969179A JP4969179A JPS599111B2 JP S599111 B2 JPS599111 B2 JP S599111B2 JP 4969179 A JP4969179 A JP 4969179A JP 4969179 A JP4969179 A JP 4969179A JP S599111 B2 JPS599111 B2 JP S599111B2
- Authority
- JP
- Japan
- Prior art keywords
- sio
- protective film
- manufacturing
- magnetic bubble
- planar magnetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【発明の詳細な説明】
この発明は、工程の簡略化ならびに信頼性の向上を期す
るようにしたプレナ型磁気バブル素子オーバレイの製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a planar magnetic bubble element overlay, which is intended to simplify the process and improve reliability.
磁気バブル素子のオーバレイ構造は駆動用パーマロイ素
子の下部に絶縁層を介して導体を配置し、ゲート機能を
もたせたいわゆるコンダクタファースト型が主流である
。The mainstream overlay structure of magnetic bubble elements is the so-called conductor-first type, in which a conductor is placed below a driving permalloy element via an insulating layer to provide a gate function.
この場合、ゲート機能部上部のパーマロイ膜はこの段差
部で膜厚が薄くなる、いわゆるステツプカバレツジ不良
を生じ、断線や磁気特性不良を起こす。また、たとえ、
ステツプカバレツジが良好であつてもパターン設計にお
いて段差部の磁気特性を考慮する必要があるなど、多く
の問題点があつた。これらの問題点を解決するために、
平面化プロセスがいくつか考案されたが、いずれも工程
が非常に複雑で非実用的なものであつたり、導体パター
ンを形成するために用いた有機レジストをそのままの状
態でその上に絶縁層を形成するレジストリフトオフ法の
ため種々問題があつた。In this case, the thickness of the permalloy film above the gate function portion becomes thinner at this stepped portion, resulting in so-called step coverage defects, resulting in wire breakage and poor magnetic properties. Also, even if
Even if the step coverage was good, there were many problems, such as the need to consider the magnetic characteristics of the step portion in pattern design. In order to solve these problems,
Several planarization processes have been devised, but all of them are extremely complex and impractical, or require the use of an insulating layer on top of the organic resist used to form the conductor pattern. Various problems arose due to the resist lift-off method.
すなわち、レジストリフトオフ法においては、有機レジ
ストを炭化させないように、絶縁層形成を特に5102
低温スパッタあるいはSi0低温蒸着により行つている
。しかし、SiO2低温スパッタでは、レジスト側面へ
のSiO2の付き廻りがあつて、レジストリフトオフが
難しく、またSi0低温蒸着では密着力に不安があつた
。In other words, in the resist lift-off method, the insulating layer is formed in particular at 5102 to prevent carbonization of the organic resist.
This is done by low-temperature sputtering or low-temperature deposition of SiO. However, in low-temperature SiO2 sputtering, SiO2 clings to the side surfaces of the resist, making resist lift-off difficult, and in low-temperature evaporation of Si0, there are concerns about adhesion.
さらに、有機レジストリフトオフ後に再び絶縁層を形成
する工程を必要とする欠点があつた。この発明は、上記
従来の欠点を除去するためになされたもので、有機レジ
ストを用いたリフトオフ法ではなく、導体金属を使用し
たリフトオフ法を採用し、工程数の減少化および信頼性
の向上を期することのできるプレナ型磁気バルブ素子オ
ーバレイの製造方法を提供することを目的とする。Furthermore, there was a drawback that a step of forming an insulating layer again was required after lift-off of the organic resist. This invention was made to eliminate the above-mentioned drawbacks of the conventional method, and adopts a lift-off method using a conductive metal instead of a lift-off method using an organic resist, thereby reducing the number of steps and improving reliability. It is an object of the present invention to provide a method for manufacturing a planar magnetic valve element overlay that can be manufactured with high efficiency.
以下、この発明のプレナ型磁気バブル素子オーバレイの
製造方法の実施例について図面に基づき説明する。第1
図ないし第1図はその一実施例を説明するためのプレナ
型磁気バルブ素子の平面化のための製造工程を示す図で
ある。まず、第1図に示すように、洗浄したウェハ1上
にスパッタによりSiO22を約1.4μ厚さに形成す
る。このSiO22の膜厚がパーマロイ転送パターンと
ウェハ1の表面との最終的な間隔である。次に、有機レ
ジストをマスクとして第2図のように、導体パターン配
置部2a0)SiO22を反応性スパツタエツチング(
エツ千アンドCF4+H2ガス圧力3X10−2t0r
r、電力密度0.3W/Clll)で、0.8μの深さ
にエツチングする。Embodiments of the method for manufacturing a planar magnetic bubble element overlay according to the present invention will be described below with reference to the drawings. 1st
The drawings and FIG. 1 are diagrams showing a manufacturing process for flattening a planar type magnetic valve element for explaining one embodiment thereof. First, as shown in FIG. 1, SiO22 is formed to a thickness of about 1.4 .mu.m on a cleaned wafer 1 by sputtering. This film thickness of SiO22 is the final distance between the Permalloy transfer pattern and the surface of the wafer 1. Next, using the organic resist as a mask, as shown in FIG.
Etsu thousand and CF4+H2 gas pressure 3X10-2t0r
Etch to a depth of 0.8 μm at a power density of 0.3 W/Clll).
このとき、SiO,エツチング断面はウエハ1の表面に
ほとんど垂直となる。At this time, the SiO etching cross section becomes almost perpendicular to the surface of the wafer 1.
次いで、第3図に示す工程に移行し、上記有機レジスト
を剥離し、しかる後に、導体金属としてAl−Cu3を
約0.4μの厚さでSiO22の表面全体に真空蒸着す
る。Next, the process moves to the step shown in FIG. 3, where the organic resist is peeled off, and then Al--Cu3 is vacuum-deposited as a conductor metal to a thickness of about 0.4 .mu.m over the entire surface of the SiO22.
この蒸着時における基板加熱温度は150℃程度である
。さらに、第4図に示すように、SiO4をAl−Cu
3の表面全体に同一真空内で0.5μ蒸着する(このと
きも、蒸着時の基板加熱温度は150℃程度とする)。The substrate heating temperature during this vapor deposition is about 150°C. Furthermore, as shown in Fig. 4, SiO4 was replaced with Al-Cu.
A thickness of 0.5 μm is deposited on the entire surface of No. 3 in the same vacuum (also at this time, the substrate heating temperature during deposition is about 150° C.).
次に、導体パターン配置部2a以外のAl−Cu3を塩
酸対水の割合を1対1でスプレーエツチングすると同時
に、その上部に付着させたSiO4の膜を第5図に示す
ごとくに除去する。Next, the Al--Cu3 other than the conductor pattern arrangement area 2a is spray-etched at a ratio of hydrochloric acid to water of 1:1, and at the same time, the SiO4 film deposited on the top is removed as shown in FIG.
以上の工程により、SiO4によつて導体パターン配置
部2aにおけるA2−0u3が絶縁される。Through the above steps, A2-0u3 in the conductor pattern arrangement portion 2a is insulated by SiO4.
しかも、SiO4とSiO22の表面はほとんど段差の
ない平面となる。しかる後に、パーマロイ膜5を第6図
に示すように、0.4μスパツタ法で形成する。さらに
、フオトエツチング技術によりパターン化し、しかる後
に保護膜として、第7図に示すようにSiO26の膜を
0.5μの厚さで全面にスパツタ法で形成する。Moreover, the surfaces of SiO4 and SiO22 are flat with almost no difference in level. Thereafter, a permalloy film 5 is formed by a 0.4μ sputtering method, as shown in FIG. Further, it is patterned by photo-etching technology, and then, as a protective film, a film of SiO26 with a thickness of 0.5 .mu.m is formed on the entire surface by sputtering as shown in FIG.
以上詳述したように、この発明のプレナ型磁気バブル素
子オーバレイの製造方法によれば、ウエハ上にその保護
膜としてのSiO,を形成し、このSiO2をその上面
の有機レジストをマスクとして反応性スパツタエツチン
グで所定の深さにエツチングして導体パターン配置部を
形成した後SiO2の表面全体に導体金属を蒸着し、こ
の導体金属の表面全体にSiOを蒸着した後に導体パタ
ーン配置部以外の導体金属と、その上部に形成されたS
iOを選択的に除去して、残されたSiOとSiO2の
上面に段差をなくして平面化を行い、このSiOとSi
O,上にパーマロイパターンを形成するようにしたので
、リフトオフ終了時点に、すでに導体金属上に絶縁層が
形成されることになり、リフトオフ後の絶縁層を形成す
る工程が省ける。As described in detail above, according to the method for manufacturing a planar magnetic bubble element overlay of the present invention, SiO is formed as a protective film on a wafer, and this SiO2 is used as a reactive layer using an organic resist on the upper surface as a mask. After etching to a predetermined depth using sputter etching to form a conductor pattern placement area, a conductor metal is vapor deposited on the entire surface of the SiO2, and after SiO is vapor deposited on the entire surface of the conductor metal, conductors other than the conductor pattern placement area are formed. metal and S formed on top of it
After selectively removing iO, the top surfaces of the remaining SiO and SiO2 are flattened without any steps, and the SiO and SiO2 are flattened.
Since the permalloy pattern is formed on O, the insulating layer is already formed on the conductive metal at the end of lift-off, and the step of forming an insulating layer after lift-off can be omitted.
これにともない、最も工数の少ない非平面化プロセスに
比しても導体金属除去工程が増すのみであり、導体金属
上の絶縁層形成を特に低温で行う必要がなくなる。Accordingly, even when compared to the non-planarization process which requires the least number of steps, the number of steps for removing the conductor metal is increased, and there is no need to form an insulating layer on the conductor metal at a particularly low temperature.
また、この発明の方法は、始めに保護膜に導体パターン
配置部(溝)を形成し、その壽に導体を埋め込むという
方法により、他の平坦化技術に比較して大幅に工程が簡
単になる。さらに、この発明の方法は、従平の磁気バブ
ル素子形成やIC製造に用いられている信頼性の高い材
料を使用して磁気バブル素子のオーバレイ構造を製造で
きる。また、導体金属および絶縁層を同一真空内に形成
できるため、金属、絶縁層間の密着性にすぐれた膜の形
成が可能となるとともに、作業時間の短縮が可能な信頼
性の高い回路パタ一を形成できるなどのすぐれた効果を
奏するものである。In addition, the method of the present invention involves first forming a conductor pattern placement portion (groove) in the protective film and embedding the conductor in the groove, which greatly simplifies the process compared to other planarization techniques. . Furthermore, the method of the present invention allows the overlay structure of a magnetic bubble device to be manufactured using highly reliable materials used in conventional magnetic bubble device formation and IC manufacturing. In addition, since the conductive metal and insulating layers can be formed in the same vacuum, it is possible to form a film with excellent adhesion between the metal and insulating layers, and to create highly reliable circuit patterns that can shorten work time. It has excellent effects such as being able to form.
第1図ないし第7図はそれぞれこの発明のプレナ型磁気
バブル素子オーバレイの製造方法の一実施例を説明する
ための工程図である。
1・・・・・・ウエハ 2・・・・・・SiO2,2a
・・・・・・導体パターン配置部、3・・・・・・Al
−Cul4・・・・・・SiO、6・・・・・・SiO
,、5・・・・・・パーマロイ膜。1 to 7 are process diagrams for explaining one embodiment of the method for manufacturing a planar magnetic bubble element overlay according to the present invention. 1... Wafer 2... SiO2, 2a
......Conductor pattern arrangement section, 3...Al
-Cul4...SiO, 6...SiO
,,5...Permalloy film.
Claims (1)
膜をその上面の有機レジストをマスクとして反応性スパ
ッタエッチングで所定の深さにエッチングして導体パタ
ーン配置部を形成した後に上記保護膜の表面全体に導体
金属を蒸着し、この導体金属の表面全体にSiOを設け
た後に上記導体パターン配置部以外の導体金属と、その
上部に形成されたSiOを選択的に除去して、残された
SiOと上記保護膜の上面との平面化を行い、このSi
Oと保護膜上にパーマロイパターンを形成することを特
徴とするプレナ型磁気バブル素子オーバレイの製造方法
。1 A protective film of SiO_2 is formed on the wafer, and this protective film is etched to a predetermined depth by reactive sputter etching using the organic resist on the upper surface as a mask to form a conductor pattern arrangement area, and then the surface of the protective film is etched to a predetermined depth. After depositing a conductive metal over the entire surface and providing SiO on the entire surface of the conductive metal, the conductive metal other than the conductor pattern arrangement area and the SiO formed on the top thereof are selectively removed, and the remaining SiO The upper surface of the protective film is planarized, and this Si
A method for manufacturing a planar magnetic bubble element overlay, comprising forming a permalloy pattern on an O and a protective film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4969179A JPS599111B2 (en) | 1979-04-24 | 1979-04-24 | Manufacturing method of planar magnetic bubble element overlay |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4969179A JPS599111B2 (en) | 1979-04-24 | 1979-04-24 | Manufacturing method of planar magnetic bubble element overlay |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55142480A JPS55142480A (en) | 1980-11-07 |
JPS599111B2 true JPS599111B2 (en) | 1984-02-29 |
Family
ID=12838199
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4969179A Expired JPS599111B2 (en) | 1979-04-24 | 1979-04-24 | Manufacturing method of planar magnetic bubble element overlay |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS599111B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0511286Y2 (en) * | 1986-07-14 | 1993-03-19 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6074192A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Method for forming bubble memory |
-
1979
- 1979-04-24 JP JP4969179A patent/JPS599111B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0511286Y2 (en) * | 1986-07-14 | 1993-03-19 |
Also Published As
Publication number | Publication date |
---|---|
JPS55142480A (en) | 1980-11-07 |
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