KR0157893B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR0157893B1 KR0157893B1 KR1019950024983A KR19950024983A KR0157893B1 KR 0157893 B1 KR0157893 B1 KR 0157893B1 KR 1019950024983 A KR1019950024983 A KR 1019950024983A KR 19950024983 A KR19950024983 A KR 19950024983A KR 0157893 B1 KR0157893 B1 KR 0157893B1
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- insulating film
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- sog
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 4
- XUIIKFGFIJCVMT-GFCCVEGCSA-N D-thyroxine Chemical compound IC1=CC(C[C@@H](N)C(O)=O)=CC(I)=C1OC1=CC(I)=C(O)C(I)=C1 XUIIKFGFIJCVMT-GFCCVEGCSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 231100000614 poison Toxicity 0.000 description 2
- 231100000572 poisoning Toxicity 0.000 description 2
- 230000000607 poisoning effect Effects 0.000 description 2
- 230000007096 poisonous effect Effects 0.000 description 2
- 229940034208 thyroxine Drugs 0.000 description 2
- XUIIKFGFIJCVMT-UHFFFAOYSA-N thyroxine-binding globulin Natural products IC1=CC(CC([NH3+])C([O-])=O)=CC(I)=C1OC1=CC(I)=C(O)C(I)=C1 XUIIKFGFIJCVMT-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Computer Hardware Design (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로 제1전도층이 형성되어 있는 절연막 상에 제1절연막, 상기 제1절연막 위에 SOG 및, 상기 SOG 위에 제2절연막을 형성하는 공정과; 주변회로부 상의 제1전도층에 대응되는 영역의 제1절연막, SOG 및, 제2절연막을 식각하여 접촉 홀을 형성하는 공정과; 상기 접촉 홀 측면에 절연막 측벽을 형성하는 공정과; 상기 접촉 홀에 제2전도층을 형성하는 공정 및; 상기 제2전도층과 제2절연막 상에 제3전도층을 형성하는 공정을 구비하여 소자 제조를 완료하므로써, 1) SOG를 이용한 평탄화 공정시 필수적으로 요구되는 에치백 공정을 스킵(skip)할 수 있어, 에치백시 야기되던 평탄도 저하 문제나 식각 선택성을 이용한 식각 공정의 어려움 및 좁은 전도층패턴 스페이스에 증착된 얇은 CVD 산화막 위에서의 SOG 에치백에 따른 공정 마진 감소 등과 같은 제반 문제점들을 제거할 수 있게 될 뿐 아니라, 2) SOG을 이용한 평탄화 공정시 넌-에치백 공정으로 인하여 야기되는 접촉 홀의 포이저니 현상 및 콘택 저항 증가 현상을 제거할 수 있게 되어 SOG와 제2전도층 사이에서 문제시되던 소자의 특성 저하 문제를 개선할 수 있게 된다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a first insulating film, an SOG on the first insulating film, and a second insulating film on the SOG on the insulating film having the first conductive layer formed thereon; Etching the first insulating film, the SOG, and the second insulating film in a region corresponding to the first conductive layer on the peripheral circuit portion to form contact holes; Forming an insulating film sidewall on the contact hole side; Forming a second conductive layer in the contact hole; Comprising the process of forming a third conductive layer on the second conductive layer and the second insulating layer to complete the device manufacturing, 1) it is possible to skip the etchback process is required in the planarization process using SOG This eliminates problems such as flatness deterioration caused by etch back, difficulty in etching process using etch selectivity, and process margin reduction due to SOG etch back on thin CVD oxide deposited in narrow conductive layer pattern space. In addition, 2) it is possible to eliminate the poisony of the contact hole and the increase of the contact resistance caused by the non-etch back process in the planarization process using the SOG. The problem of deterioration can be improved.
Description
제1(a)도 내지 제1(e)도는 종래 기술에 따른 반도체 소자 제조공정을 도시한 공정수순도.1 (a) to 1 (e) are process flowcharts showing a semiconductor device manufacturing process according to the prior art.
제2(a)도 내지 제2(f)도는 본 발명에 따른 반도체 소자 제조공정을 도시한 공정수순도.2 (a) to 2 (f) is a process flowchart showing a semiconductor device manufacturing process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : BPSG막 20 : 제1전도층 패턴10: BPSG film 20: first conductive layer pattern
30 : 제1CVD 산화막 40 : SOG30: first CVD oxide film 40: SOG
50 : 제2CVD 산화막 60 : 절연막50: second CVD oxide film 60: insulating film
60' : 절연막 측벽 70 : 제2전도층60 ': insulating film sidewall 70: second conductive layer
80 : 제3전도층80: third conductive layer
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 SOG를 이용한 평탄화 공정시 넌-에치백(non-etch back) 공정으로 인하여 야기되는 접촉 홀 영역의 유기(organic) SOG에 의한 포이저니(poisoniy) 현상을 방지하기 위하여 접촉 홀에 절연막 측벽(dielectric sidewall)을 형성한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, poisoniy due to organic SOG in a contact hole region caused by a non-etch back process during a planarization process using SOG. The present invention relates to a method for manufacturing a semiconductor device in which an insulating sidewall is formed in a contact hole.
종래의 반도체 소자는 제1(a)도 내지 제1(e)도에 도시된 공정수순도에서 알 수 있듯이, 먼저 제1(a)도에 도시된 형태로 BPSG막(1) 상의 셀 형성부 및 주변회로부에 제1전도층 패턴(2)을 형성하고, 제1(b)도에 도시된 바와 같이 상기 제1전도층 패턴(2)을 포함한 BPSG막(1) 상에 이후 증착될 SOG와 제1전도층 패턴(2) 간의 접촉(contact)을 방지하기 위한 제1CVD 산화막(3)을 증착한 후, 갭 채움(gap fill) 특성 및 크랙 레지스턴스(crack resistance) 특성이 우수한 유기 SOG(4)를 제1CVD 산화막(3) 상에 코팅하고 열처리하여 산화막(SiO2)을 증착한다.A conventional semiconductor device has a cell formation portion on the BPSG film 1 in the form shown in FIG. 1 (a), as can be seen from the process steps shown in FIGS. 1 (a) to 1 (e). And a SOG to be subsequently deposited on the BPSG film 1 including the first conductive layer pattern 2, as shown in FIG. 1 (b). After depositing the first CVD oxide film 3 to prevent contact between the first conductive layer pattern 2, the organic SOG (4) excellent in the gap fill characteristics (crack resistance) and crack resistance characteristics (crack resistance) Is coated on the first CVD oxide film 3 and heat treated to deposit an oxide film (SiO 2).
이때, 상기 SOG(4)로는 실리케이트(silicate) SOG를 증착할 수도 있고, 사이록신(siloxine) SOG를 증착할 수도 있으나, 상기 실리케이트 SOG의 경우는 평탄도에 한계가 따르므로 여기서는 평탄도 특성이 우수한 사이록신 SOG를 증착한 경우에 대하여 살펴본다.At this time, the SOG (4) may be deposited silicate (Silicate) SOG, it may be deposited a siloxine (SiOxine) SOG, but in the case of the silicate SOG there is a limit in the flatness is excellent here flatness characteristics The case of depositing thyroxine SOG will be described.
그후, 접촉 홀이 형성될 주변회로부의 제1전도층 패턴(2) 상의 SOG(4)를 완전히 제거할 목적으로 SOG(4)와 제1CVD 산화막(3) 간의 식각 선택비(selectivity)를 조절하여 제1(c)도에 도시된 바와 같이 상기 SOG(4)를 다단계(multi-step) 에치백하고, 이후 증착될 제3전도층과 유기 SOG의 접촉을 막기 위하여 노출된 상기 제1CVD 산화막(3) 및 SOG(4) 상에 제2CVD 산화막(5)을 증착한다.Thereafter, an etching selectivity between the SOG 4 and the first CVD oxide film 3 is adjusted to completely remove the SOG 4 on the first conductive layer pattern 2 of the peripheral circuit portion where the contact hole is to be formed. As shown in FIG. 1 (c), the SOG 4 is multi-etched back and the first CVD oxide film 3 exposed to prevent contact between the third conductive layer to be deposited and the organic SOG is deposited. And the second CVD oxide film 5 are deposited on the SOG 4.
이어서, 제1(d)도에 도시된 바와 같이 주변회로부의 제1전도층 패턴(2) 상에 형성된 제2CVD 산화막(5) 및 제1CVD 산화막(3)을 제1전도층 패턴(2)의 표면 일부가 드러나도록 식각하여 제1전도층 패턴(2)과 제3전도층을 연결할 접촉 홀(contact hole)을 형성하고, 상기 접촉홀에 생성되는 자연산화막을 제거하기 위하여 스퍼터링법으로 식각을 실시한 후, 제2전도층(6)을 이용하여 상기 접촉 홀 영역을 채운다.Subsequently, as shown in FIG. 1 (d), the second CVD oxide film 5 and the first CVD oxide film 3 formed on the first conductive layer pattern 2 of the peripheral circuit portion are formed on the first conductive layer pattern 2. A portion of the surface is etched to form a contact hole for connecting the first conductive layer pattern 2 and the third conductive layer, and etching is performed by sputtering to remove the natural oxide film formed in the contact hole. After that, the contact hole region is filled using the second conductive layer 6.
그 다음, 제1(e)도에 도시된 바와 같이 상기 제2전도층(6)을 포함한 제2CVD 산화막(5) 상에 제3전도층(7)을 증착하고, 이를 식각처리하여 제3전도층 패턴을 형성하므로써 소자 제조공정을 완료한다. 이때, 접촉 홀에 제2전도층(6)을 채우는 공정과 이후의 제3전도층(7)을 증착하는 공정은 동시에 진행할 수도 있다.Next, as shown in FIG. 1 (e), a third conductive layer 7 is deposited on the second CVD oxide film 5 including the second conductive layer 6, and then etched to form a third conductive layer. The device manufacturing process is completed by forming a layer pattern. In this case, the process of filling the second conductive layer 6 in the contact hole and the subsequent process of depositing the third conductive layer 7 may be performed simultaneously.
그러나, 상기 공정은 넌-에치백 공정을 진행하기 위하여 실리케이트 SOG를 증착할 경우에는, 작은 사이즈의 갭 채움, 크랙 레지스턴스 및, 로우컬 플레이너제이션(local planarization) 등에 문제점이 발생하게 되고, 에치백 공정을 진행하기 위하여 상기와 같이 사일록신(siloxzne) SOG를 증착할 경우에는, SOG와 그 서브-층(sub-layer)인 CVD 산화막 간의 식각 선택비 조절의 어려움 및 평탄도 저하 등과 같은 단점이 발생될 뿐 아니라 소자가 고집적화되어 감에 따라 제1전도층 패턴의 스페이서가 더욱 좁아져 CVD 산화막 증착 두께가 낮아지게 되므로 에치백시 충분한 공정 마진(margin)이 확보되지 못하는 문제점이 발생하게 된다.However, when the silicate SOG is deposited to proceed with the non-etchback process, problems such as small gap filling, crack resistance, and local planarization occur, and the etchback In the case of depositing siloxzne SOG as described above, there are disadvantages such as difficulty in controlling the etching selectivity between SOG and its sub-layer CVD oxide film and lowering flatness. In addition, as the device is highly integrated, the spacer of the first conductive layer pattern is further narrowed and the CVD oxide deposition thickness is lowered. Therefore, sufficient process margin is not secured during etch back.
또한, 사이록신을 코팅한 후 충분히 에치백 하지 않을 경우, SOG에 의한 접촉 홀의 포이저니 현상으로 인하여 접촉 홀의 콘택 저항 증가 및 소자의 특성 저하 등과 같은 문제가 야기되기도 한다.In addition, if the etchin is not sufficiently etched back after coating the thyroxine, problems such as an increase in contact resistance of the contact hole and a deterioration of the characteristics of the device may occur due to the poisoning phenomenon of the contact hole by SOG.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 이루어진 것으로, 접촉 홀 영역에 절연막 측벽을 형성하므로써 접촉 홀에서의 유기 SOG에 의한 포이저니 현상을 억제하여 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and by forming an insulating film sidewall in the contact hole region, the semiconductor device fabrication can improve the reliability of the device by suppressing the poisoning phenomenon caused by organic SOG in the contact hole. The purpose is to provide a method.
상기와 같은 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법은 제1전도층이 형성되어 있는 절연막 상에 제1절연막, 상기 제1절연막 위에 SOG 및, 상기 SOG 위에 제2절연막을 형성하는 공정과; 주변회로부 상의 제1전도층에 대응되는 영역의 제1절연막, SOG 및, 제2절연막을 식각하여 접촉 홀을 형성하는 공정과; 상기 접촉 홀 측면에 절연막 측벽을 형성하는 공정과; 상기 접촉 홀에 제2전도층을 형성하는 공정 및; 상기 제2전도층과 제2절연막 상에 제3전도층을 형성하는 공정을 구비하여 형성되는 것을 특징으로 한다.A semiconductor device manufacturing method according to a preferred embodiment of the present invention for achieving the above object is a first insulating film on the insulating film on which the first conductive layer is formed, SOG on the first insulating film, and a second insulating film on the SOG Forming a; Etching the first insulating film, the SOG, and the second insulating film in a region corresponding to the first conductive layer on the peripheral circuit portion to form contact holes; Forming an insulating film sidewall on the contact hole side; Forming a second conductive layer in the contact hole; And forming a third conductive layer on the second conductive layer and the second insulating layer.
상기 공정 결과, 접촉 홀 영역에서의 유기 SOG에 의한 포이저니 현상을 방지할 수 있게 된다.As a result of the above process, it is possible to prevent the poisonous phenomenon caused by organic SOG in the contact hole region.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은 접촉 홀 영역에서의 유기 SOG에 의한 포이저니 현상을 방지하기 위하여 SOG를 에치백 하지 않은 상태에서 접촉 홀을 오픈(open)한 뒤, 웨이퍼 전면에 절연막을 증착하고, 이를 이방성 식각(unisotropic etch) 또는 스퍼터링 식각법으로 식각하여 접촉 홀 영역 내측에 절연막 측벽을 형성하므로써, 이후 접촉 홀 영역에 채워지는 전도층을 접촉 홀 측벽에 드러난 SOG로 부터 격리토록 한 것으로, 이를 제2(a) 내지 제2(f)도에 도시된 공정수순도를 이용하여 구체적으로 살펴보면 다음과 같다.In order to prevent poisonous phenomenon caused by organic SOG in the contact hole area, the contact hole is opened without the SOG being etched back, and an insulating film is deposited on the entire surface of the wafer, which is then anisotropically etched. etch) or sputter etching to form an insulating film sidewall inside the contact hole region, thereby separating the conductive layer filled in the contact hole region from the SOG exposed on the contact hole sidewall. Looking in detail using the process purity shown in Figure 2 (f) as follows.
먼저, 절연막인 BPSG막(10) 상의 셀 형성부 및 주변회로부에 제1전도층을 증착한 후 이를 선택 식각하여 제2(a)도에 도시된 바와 같이 서로 소정 간격 이격된 형상의 제1전도층패턴(20)을 형성한다.First, the first conductive layer is deposited on the cell forming portion and the peripheral circuit portion on the BPSG film 10, which is an insulating film, and then selectively etched to form a first conductive material spaced apart from each other by a predetermined distance as shown in FIG. The layer pattern 20 is formed.
그후, 제2(b)도에 도시된 바와 같이 상기 제1전도층패턴(20)을 포함한 BPSG막(10) 상에 이후 증착될 SOG와 제1전도층패턴 간의 접촉을 방지하기 위하여 제1CVD 산화막(30)을 증착하고, 갭 채움(gap fill) 특성 및 크랙 레지스턴스(crack resistance) 특성이 우수한 유기 SOG(40)를 제1CVD 산화막(30) 상에 코팅한 후 열처리하여 산화막(SiO2)을 증착한다.Thereafter, as shown in FIG. 2 (b), the first CVD oxide film is prevented to prevent contact between the SOG to be subsequently deposited on the BPSG film 10 including the first conductive layer pattern 20 and the first conductive layer pattern. (30) and the organic SOG 40 having excellent gap fill characteristics and crack resistance characteristics is coated on the first CVD oxide layer 30 and then heat-treated to deposit an oxide layer (SiO 2). .
이어서, 제2도에 도시된 바와 같이 상기 SOG(40) 상에 제2CVD 산화막(50)을 증착하고, 주변회로부에 형성된 BPSG막(10) 위의 제1전도층 패턴(20) 표면이 소정 부분 노출되도록 상기 제2CVD 산화막(50) 과 SOG(40) 및, 제1CVD 산화막(30)을 순차적으로 식각하여 접촉홀을 형성한 후, 상기 접촉홀을 포함한 제2CVD 산화막(50) 전면에 100-5000Å 두께의 얇은 절연막(60)을 형성하여 제2(d)도에 도시된 바와 같은 패턴을 형성한다.Subsequently, as shown in FIG. 2, a second CVD oxide film 50 is deposited on the SOG 40, and the surface of the first conductive layer pattern 20 on the BPSG film 10 formed in the peripheral circuit portion is formed at a predetermined portion. The second CVD oxide film 50, the SOG 40, and the first CVD oxide film 30 are sequentially etched to form contact holes so as to be exposed. A thin insulating film 60 of thickness is formed to form a pattern as shown in FIG. 2 (d).
그 다음 상기 절연막(60)을 이방성 식각이나 스퍼터링 식각 방법을 이용하여 식각하여 접촉 홀 내측에 제2(e)도에 도시된 형태의 절연막 측벽(60')을 형성하고, 다시 스퍼터링 식각 방법으로 접촉 홀 하부의 자연산화막을 제거한다 .Then, the insulating film 60 is etched using an anisotropic etching or sputtering etching method to form an insulating film sidewall 60 'of the type shown in FIG. 2 (e) inside the contact hole, and then contacted by a sputtering etching method. Remove the native oxide film under the hole.
계속해서, 제2(f)도에 도시된 바와 같이 제2전도층(70)으로 접촉홀 영역을 채우고, 상기 제2전도층(70)을 포함한 제2CVD 산화막(50) 상에 제3전도층(80)을 증착한 후, 이를 선택 식각하여 제3전도층패턴을 형성하므로써 본 공정을 완료한다.Subsequently, as shown in FIG. 2 (f), the third hole is filled with the second conductive layer 70 and the third conductive layer is formed on the second CVD oxide film 50 including the second conductive layer 70. After the 80 is deposited, this process is selectively etched to form the third conductive layer pattern to complete the present process.
상술한 바와 같이 본 발명에 의하면 1) SOG를 이용한 평탄화 공정시 필수적으로 요구되는 에치백 공정을 스킵(skip)할 수 있어, 에치백시 야기되던 평탄도 저하 문제나 식각 선택성을 이용한 식각 공정의 어려움 및 좁은 전도층패턴 스페이스에 증착된 얇은 CVD 산화막 위에서의 SOG 에치백에 따른 공정 마진 감소 등과 같은 제반 문제점들을 제거할 수 있게 될 뿐 아니라, 2) SOG을 이용한 평탄화 공정시 넌-에치백 공정으로 인하여 야기되는 접촉 홀의 포이저니 현상 및 콘택 저항 증가 현상을 제거할 수 있게 되어 SOG와 제2전도층 사이에서 문제시되던 소자의 특성 저하 문제를 개선할 수 있게 된다.As described above, according to the present invention, 1) it is possible to skip an etch back process that is essential during the planarization process using SOG, and thus, the problem of flatness caused by etch back or the difficulty of the etching process using etching selectivity. And reduction of process margins due to SOG etch back on thin CVD oxide films deposited in narrow conductive layer pattern spaces, as well as 2) non-etch back processes during planarization using SOG. It is possible to eliminate the cause of the contact hole caused by the contact hole and the increase of the contact resistance, thereby improving the problem of deterioration of the device, which is a problem between the SOG and the second conductive layer.
Claims (4)
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| KR100457407B1 (en) * | 1997-12-30 | 2005-02-23 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection |
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| KR100457407B1 (en) * | 1997-12-30 | 2005-02-23 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to improve electrical characteristic of metal interconnection |
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