JPS5990129A - Input and output controller - Google Patents

Abstract

PURPOSE:To continue the processing of an input/output controller by providing an input/output control circuit between a processor and an input/output device and detecting a delimiter out of a series of data during the data input or output processing to invert the input or output state. CONSTITUTION:An input/output controller 20 is provided between a processor 1 and an input/output device 30. An input/output control circuit 2 of the controller 20 refers to a command register 4 in an output control mode and confirms that the contents of a transfer amount count register 5a are not zero in an ON state. Then the circuit 2 refers to the contents of an address register 6a to read the data out of an address of a main memory and transfers the data to a buffer register 9a. This data is sent to the device 30 via an output gate 10 and an output driver 12. In this case, 1 is added to the address of the register 6a. At the same time, 1 is subtracted from the register 5a. The same processing is carried out also with input. Thus the processing is continued by detecting 8a and 8b a stop code out of a series of data or inverting the input and output modes when the count registers 5a and 5b are set at 0.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output side fffll device.

This invention is particularly applicable to man-machine interfaces (
For example, it is applied to an input/output control device for a display device (keyboard + CRT display) for interlocutor output, a personal computer, an intelligent terminal, an input/output quiwriter, etc., and its outline is as follows: For example, when transferring data between an input/output device such as a display device,
It has two control states: an output control state for sending output data to the input/output device side, and an input control state for sending input data to the CPU side, and a delimiter for data sent from the CPU side. This is an input/output control device that shifts from an output control state to an input control state by detecting.

By configuring in this way, an electronic computer (hereinafter referred to as
A device that reduces the input/output processing program on the computer side (simply referred to as a computer), and can perform input processing in response to output messages from the computer without waiting for input permission from the computer side, and can perform input/output processing continuously. It is.

In recent years, with advances in the price of computers and advances in their software, computers have been introduced and used in many fields. Moreover, in recent years, there has been an increase in the number of ways computers and humans interact through man-machine interfaces (devices). In particular, this can be said to be indispensable when handling information such as one figure, one image, etc. This man-machine interface performs the work of mutually converting between information expressions in a form suitable for human work, thinking, judgment, etc., and the machine's internal language expressions that can be understood by a δ1 calculator. Therefore, man-machine interfaces (devices) play a vital role in designing systems that are easy for humans to use.

Generally, interaction with a man-machine interface (device) occurs as follows.

(2) The computer outputs a message to the man-machine interface device to prompt the user to input instructions.

■The person follows the message and follows the instructions.
It is input from a machine interface device and transmitted to the computer.

(2) The computer processes the data according to the instructions, and outputs a message to the man-machine interface device to prompt the user to input the next instruction.

The forms of these dialogue systems are computers, man-machines,
One-to-one interface devices (personal computers, etc.) and computers with multiple man-machines
There are devices to which interface devices are connected (such as intelligent terminals in TSS), but in the latter case in particular, the frequency of interaction with the computer is high, resulting in slow response characteristics from the computer side to the man-machine interface device. In order to prevent this, the number of connected input/output devices that interact is limited. Therefore, such an interactive system has the disadvantage that the number of connected input/output devices is limited.

On the other hand, in the above-mentioned dialogue, generally, as a process on the computer side, the computer starts the process of prompting for the input of instructions, and then
While waiting for the output, the main memory is opened and handed over to another program to perform other processing. Then, when the output is completed, the own program is returned to the main memory and output termination processing is performed. Next, perform instruction input start processing, and between the input start processing and the actual input of instruction input, the main memory is similarly opened and handed over to other programs, and during this time, another Process. When the specified input is completed, the program returns to the main memory and processes the input information.

As described above, a computer generally operates the input processing ((2) above) and the output processing ((2) above) separately, and the overall processing steps are large and the load on the computer is high. Moreover,
Since the control priority for the man-machine interface device is high, there is a disadvantage that the processing load on the man-machine interface device on the computer side is correspondingly large.

The present invention eliminates the drawbacks of the prior art, allows input/output control processing to be performed simultaneously on the computer side without having to separate it as described above, reduces the processing for the interactive input/output device in the computer, and improves human interaction. It is an object of the present invention to provide such an input/output control device that can increase the number of connected machine interface devices or improve the response characteristics of a computer.

In order to achieve the above objects, the present invention controls the transfer of data between a processing device (for example, the computer 1) and the input/output device 30, as shown in the embodiments described later and the attached drawings. In the input/output control device 20, the data sent from the processing device (computer 1) is controlled to be sent to the input/output device 30 side as output data; and an input control state that controls sending data to the processing device (computer 1) as input data, and the processing device (computer 1)
Detects the break in a series of data sent from the computer 1) (eg, stop code registers 7a, 7b, stop code detection circuit 3a).

8b), the input/output control device 20 shifts from the output control state to the input control state.

By configuring the input/output control device in this way, the control to move from output to input is automatically performed, so data transfer processing of human output can be performed continuously, and the total time is reduced.
There is no need to separate input/output control processing in the machine, and simultaneous processing can be performed. As a result, the load on the computer's interactive input/output device can be reduced and the number of connected man-machine interface devices can be increased, or
1. It is possible to improve the response characteristics of a computer.
bear fruit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an input/output control device to which the present invention is applied, which controls data transfer between a computer and an input/output device.

This input/output control device 20 is connected to a computer via a CPU bus, and to an input/output device 30, which is a -7-inch machine interface device, via an input/output cable line.

In the figure, 1 is a computer, and 30 is an input/output device. An input/output control device 20 that controls data transfer between the computer 1 and the input/output device 30 is disposed between them, and the computer 1 is a lotus 1a (CPU lotus).
It is connected to the input/output device 30 via signal lines 25 and 26, which are input/output cables.

The configuration of the input/output control device 20 includes an input/output control circuit 2, a status register 3, a command register 4, a control register group for an output control state and a control register group for an input control state, which will be described later, an output gate circuit 10, and an output driver circuit 12. , an input gate circuit 11, and an input receiver circuit 13, and has an output control state and an input control state. Here, except for the output driver circuit 12 and the input receiver circuit 13, these registers and circuits are interconnected via a data bus 22, and a control bus 21,
It is controlled by the input/output control circuit 2 via the address bus 23. Further, the input gate circuit 11 is connected to the input/output control circuit 2 via an interrupt bus 24.

Here, the control register group in the output control state includes a transfer amount count register 5a, an address register 5a, a stop code register 7a, and a stop code detection circuit 3.
The control register group in the input control state includes a transfer amount count register 5b, an atrus register 6b, a stop code register 7b, a stop code detection circuit 3b, and a buffer resistor 9b. We are prepared. The stop code detection circuits 8a and 8b are each connected to the input/output control circuit 2 via an interrupt hash 24.

Here, the input/output control circuit 2 processes data from the computer 1 (main memory) in accordance with control information from the computer 1, and also processes data from the input/output device 30 to the computer 1.
(main memory), so-called DMA (direct memory access) control.

On the other hand, the status register 3 is a register that displays the operating state of the input/output control device 20. When the input/output control device 20 is in operation, information indicating that it is in operation is written, and when a predetermined operation is completed, operation end information is written. It will be done. The command register 4 also stores commands sent from the calculation ta I. Further, the output gate circuit 10 takes in data from the data bus 22 under the control of the human output control circuit 2 and sends output data to the input/output device 30 via the output driver circuit 12. On the other hand, input gate circuit 1
1 receives input data from the input/output device 30 via the input receiver circuit 13, interrupts the input/output control device 2 via the interrupt bus 24, and puts the input data onto the data bus 22.

The no\nofa register 9a of the control register group in the output control state is for storing a series of data transferred from the computer 1 and output to the input/output device 30, and should be the transfer amount count register 5a. In this case, the amount of transfer is seven times. The block code register 7a stores a code for the block code 1 sent from the computer 1, such as raJ+ [line feed mark J+ r predetermined amount of space J+ 'return', etc., which does not indicate the end of a series of data (message). Remember. The stop code detection circuit 8a has a stop code register 7a and a buffer register 9.
Upon receiving the signal from a, the noku/nofa register 9a4
：：、、Self 1. This detects the match between the code at the end of the sent message and the code stored in the knob code register 7a, and when they match, a match detection signal is generated and an interrupt is triggered. An interrupt is applied to the input/output 1t11 control circuit 2 via the bus 24. Further, the address register 6a stores the address where the transfer data of the main memory IJ of the computer 1 is stored.

On the other hand, each register in the control information register group in the input control state has almost the same function as the control information register group in the output control state, although there are differences in input and output. Far register gbt, input/output control circuit 2
is input from the input/output device 30 under the control of the computer 1.
A series of data to be transferred to 1. The transfer amount in this case is stored in the transfer amount count register 5b. The stop code register 7b stores stop codes sent from the input/output device 30, such as ".", "line feed mark J", "
Codes for "predetermined amount of space", "r return", etc. are stored. The block code detection circuit 8b receives the signals from the stop code register 7b and the buffer register 9b, and detects the message (code) written in the buffer register 9b and stored in the stop knob code register 7b. It detects a match with the code, and when they match, it generates a match detection signal and sends it to the interrupt bus 2.
An interrupt is applied to the input/output control circuit 2 via the input/output control circuit 2. On the other hand, the address register 6b is stored in the computer 1 to which the transfer data is transferred.
Stores the main memory address of.

Here, the control register group in the output control state indicates the output control state of the input/output control device of the present invention under the control of the input/output control circuit 2; , a specific circuit configuration for realizing the input control state of the input/output control device. However, these may be realized not in the form of such a circuit, but in a program, for example, with a device composed of a microprocessor and memory, or by a combination of a program, various registers, and logic circuits. You may.

Each of the stop code detection circuits 8a detects a break in the data sent from the processing device of the present invention, shifts to an input control state, and stops the stop code detection circuit 81.
b is a concrete example p+i of a circuit that detects a break in data sent from an input/output device and shifts to an output control state, but this may also be implemented in a program as described above.

Next, the interactions between the registers and circuits of the input/output control device 20 having the above configuration will be explained.

First, the input/output control circuit 2 controls the status register 3, command register 4, transfer amount count registers 5a, 5b, and address registers 5a, 5b using an address signal carried on the address bus 23.

Stop code registers 7a, 7b, no\7 registers 9a, 9b, output gate circuit 10. A predetermined one is selected from among the input game 1-circuits 11. Then, the data signal is output to the data bus 22 and sent to the selected register or circuit, or the data signal sent by the selected register or circuit is received via the data bus 22. Here, whether the selected register or circuit sends a data signal to the data node 22 or receives it from there is determined based on the control signal sent from the input/output control circuit 2 onto the control path 21. Note that this human output control circuit 2 is internally equipped with a T constant circuit and a detection circuit, or a determination program and/or a detection program, and each register has the following information. It has the function of determining the contents of the received information and detecting interrupts.

In addition, status register 3, command register 4, transfer amount count registers 5a, 5b, address register 6
a, 6b, and stop code registers 7a, 7b can write data from the computer 1 and output the data to JJε via the input/output control circuit 2 and path 1a. Therefore,
Information indicating the usage status is written into the status register 3 from the computer 1. In the command register 4, information such as a start command signal and whether the command has a stop code is written from the computer 1, and the transfer amount count registers 5a, 5
The amount of message data and input/output data transferred is written in b. Further, the address of the main memory for transferring transfer data between the computer 1 and the input/output device 30 is stored in the address registers 6a and 6b. Furthermore, when the command signal is stop code I1, the stop code registers 7a and 7b store a predetermined stop code corresponding to the message sent from the computer 1 or the message input from the input/output device 30. be done.

Incidentally, the input/output control circuit 2 sends a comparison command signal to the stop code detection circuit 8a or 8b via the control lot 21. Upon receiving this, the stop code detection circuit 8a outputs the code stored in the knob code register 7a and the buffer register 9a, while the stop code detection circuit 8b outputs the code stored in the stop code register 7b and the buffer register 9a. The message (code) stored in 9b is compared to detect a match.

When these match, the stop load detection circuit 8a
Alternatively, 8b generates a coincidence detection signal and interrupts the input/output control circuit 2 via the interrupt hash 24. When the input/output control circuit 2 receives an interrupt from the snub-knob code detection circuit 8a, it detects this, shifts the control from the output control state to the manual control state, and transfers the control from the input/output device 30 to the input receiver circuit. 13. The data input through the input gate circuit 11 is temporarily stored in the buffer register 9b, and then transferred to the computer 1 side.

On the other hand, when an interrupt is received from the stop code detection circuit 8b, the control is transferred to the control register group in the output control state, and the data sent from the computer 1 is temporarily written in the buffer register 9b at tQ L, and the data is stored in the buffer register 9b. is outputted to the input/output device 3o side via the output data 1-circuit 10 and the output driver circuit I2.

By the way, the input/output control device 2o and the input/output device 30 are as follows.
Here, they are connected by a current loop interface, and the output circuit 10 outputs the data signal of the data bus 22 via the output driver circuit 12 to the current on line 1b 25 for output data. Convert to intermittent. The large-scale circuit 11 also converts the intermittent current on the signal line 26 for input data into a data signal on the data bus 22 via the input receiver circuit 13, and sends an interrupt signal to the interrupt bus 24. do.

When the input/output control circuit 2 receives this interrupt signal, the input/output control circuit 2 performs control to store input data from the input/output device 3o in the buffer register 9b.

Next, the overall operation of the input/output blade side (Ku circuit 2) will be explained.

First, from the computer 1, the status register 3, command register 4, and transfer amount counter 1-register 5a.

5b, predetermined initial information ta is written into address registers 6a, 6b, and stop code registers 7a, 7b.

The input/output control circuit 2 refers to the contents of the :2 cape register 4 as the output control state, and outputs a start command without indicating a start command.
- Determine whether the bit is in the “on °′ state.

When this is “on”, next check the contents of the transfer amount count register 5d and see if it is “0゛”.
Make sure it's not.

If this value is "0", control proceeds to the input control state, which will be described later.

Next, the input/output control circuit 2 refers to the contents of the address register 6a and writes 1. The data is read from the address in the main memory at address a, transferred to the hanosa register 9a, and recorded. Then, write 1 in the address register 6a. 2 is added to the address specified by a, and this is updated to address 1. Next, subtract 1 from the value of the transfer amount count register 5a, and add this value to the transfer amount count register 5a.
cent to a.

After that, the contents of the buffer register 9a are output.
Input/output bag 'I via circuit 10 and output driver circuit 12
Output to L30 side.

The above is the output processing, but the input/output control circuit 2 further refers to the 2J mantle register 4 and determines whether the content is an output command of a stop code (=j).

If it is an output command with a stop code, the input/output control circuit 2 will detect the stop code by
A detection command signal is sent to the knob code detection circuit 8a via the control bus 21. If it is not an output command with a stop code, refer to the transfer amount count register 1-register 5a again, and hold the address register 6a until the value of the transfer amount count register 5a becomes "0".
According to the sequentially updated main memory addresses shown in , data is read out sequentially from that address, stored in the buffer register 9a, and passed through the output gate circuit 10 and output driver circuit 12. Output to the input/output device 30 side. Then, the value of transfer amount Karan 1 - Renostar 5a is subtracted.

When the stop code detection circuit 8a receives a detection command signal from the input/output control circuit 2, it starts its detection operation. As a result, if a stop coat is detected, an interrupt signal is sent from the stop coat detection circuit 8a to the input/output control circuit 2 through the interrupt bus 24. Therefore, the input/output control circuit 2 moves to the next input control state, but if the interrupt signal υ- is not sent here, it again refers to the contents of the transfer amount count register 5a and returns the value "ζ". or “0”
”. If it is “’0゛,”
The same operation is repeated until this becomes "o" or an interrupt signal is sent from the block code detection circuit 8a through the interrupt hash 24, and the main memory shown in the address register row a is sequentially updated. Data is sequentially read from the address, and the value of the transfer amount callan 1 minus the register 5a is subtracted. Then, the data is written in the buffer register 9;
Output to the 0 side.

For reference, an example of the above control shown in a flow diagram is shown in the second example.
This is shown in the figure.

Here, when the value of the transfer amount count register 5a becomes "0" or when an interrupt signal is sent from the stop code detection circuit 8;1 through the interrupt hash 24, the input/output control circuit 2 It will move to input control state,
This will be explained next.

When the input/output control circuit 2 determines that the value of the transfer amount count register 5a is 0'' or when an interrupt signal is sent from the stop code detection circuit 8a through the interrupt bus 24, the contents of the transfer amount count register 5a are Check to make sure it is not "0". If this value is "0", as a termination process, information indicating termination is written to the status register 3,
Interrupts computer 1, notifies it that the operation is complete, and turns off the start bit of command register 4.
state.

Here, when the input/output control circuit 2 determines that the value of the transfer amount count register 5a is not "0", an operation command is given to the input gate circuit 11 in order to receive the input signal from the personnel and force device 30. Send a signal. Then, an interrupt signal is sent from the input gate circuit 11 via the interrupt bus 24. Here, the input/output control circuit 2 waits for an interrupt signal and detects it.

When an interrupt occurs, the input/output control circuit 2 transfers the input signal sent onto the data bus 21 to the buffer register 9.
Transfer to b. Next, referring to the contents of the address register 6b, the input data stored in the buffer register 9b is transferred to the main memory address stored in this address register 6b and written there. Then, 1 is added to the address stored in the address register 6b to update the address by 1. Next, transfer amount count register 5b
1 is subtracted from the value of , and this value is placed in the transfer amount Curlan I register 5b.

Then, with reference to the command register 4, it is determined whether the contents are an input command with a stop code.

If the input command has a stop code, the input/output control circuit 2 will detect the stop code by
A detection command signal is sent to the stop code detection circuit 8b via the control bus 21. If it is not an input command with a stop code, refer to the transfer amount count register 5b again and enter the transfer amount count register 5b.
According to the sequentially updated main memory address indicated in the address register 6b, until the value becomes "0",
Data is transferred there, data is sequentially written to that address, and the value of the transfer amount count register 5b is subtracted.

As a result, if a stop code is detected, an interrupt signal is sent from the stop code detection circuit 8b to the input/output control circuit 2 through the interrupt path 24. When this interrupt signal is sent through the interrupt hash 24, as a termination process, information indicating termination is written to the status register 3, an interrupt is applied to the computer 1, and the completion of the operation is notified to the command register 4. Turn the start bit to the “off” state.

Then, the next output control state is entered, but if no interrupt signal is sent out, the contents of the transfer amount count register 5b are again referred to and whether or not the value is "0°°" is determined. Determine. If it is not “0”, this is “
0'' or until an interrupt signal is sent from the stop code detection circuit 8b through the interrupt bus 24, the same operation is repeated, and the signals are input and sequentially stored.
The data in buffer register 9b is transferred to address register 6b.
The data is transferred to the sequentially updated addresses of the main memory stored in the main memory and written there. Then, the value of the transfer amount count register 5b is subtracted.

For reference, an example of the above control shown in a flow diagram is shown in the third example.
This is shown in the figure.

As can be understood from the above description, in this embodiment, control information for input and output is simultaneously written from the computer 1, and data information transferred between the computer 1 and the input/output device 30 is transferred to the input/output control device. At 20, it can be processed continuously.

As a result, input/output processing can be integrally executed as program processing on the computer 1 side.

As an example, if the processing flow on the calculation tJ 111 side is shown, as shown in FIG. 4, the instruction input reminder message output and instruction input start processing, the output and input end processing,
It can be done simultaneously and sequentially, without separating input/output control processing. Therefore, the processing load on the interactive input/output device of the computer can be reduced.

In the embodiments described above, the case in which the human output control device performs DMA transfer is particularly taken as an example.
Of course, the Bromram control method can also be applied.

In addition, in the embodiment, the explanation has focused on the control to shift to the output control state or input control state by the stop code or the value of the transfer amount count register (O"), but in this case, the value of the transfer amount count register (“0”) alone may be used for switching control.Also, in the input control state,
If the input/output control circuit 2 detects a return code, line feed code, etc. input from an input/output device without providing a stop code resistor, a transition to the output control state may be made.

In short, control to shift to the output control state or the input control state can be performed by detecting a break in a series of input or output data, such as one transferred - times, indicating a break in a series of data. Anything is fine as long as it is something. In particular, in the above embodiments, in order to facilitate understanding,
Specifically, the explanation is divided into several circuits and registers, but these circuits and registers may be realized as larger circuits, and one circuit or register may be implemented in a time-sharing manner. may be used and realized. In particular, by combining with various programs, these circuits and registers can take various forms.

Furthermore, in the embodiment described above, the control operation is started by first inputting command information from the computer side to the input/output control device, but with an input signal from the input/output device side,
The control operation may be activated by generating predetermined command information.

Further, in the embodiments, the data transfer side is a computer, but it goes without saying that it may be a so-called processing device, or any other type of processing device.

As described above in detail, in the present invention, in an input/output control device that controls data transfer between a processing device and an input/output device, data sent from the processing device is converted into output data. has an output control state in which data is controlled to be sent to the input/output device side, and a manual control state in which data sent from the input/output device is controlled to be sent to the processing device side as input data, Since the output control state is shifted to the input control state by detecting a break in a series of data sent from the processing device, control to shift from input to output is automatically performed. This allows input/output data transfer to be continuous, eliminates the need to separate input/output control processing on the processing device side, and allows simultaneous processing.

As a result, the processing load on the interactive input/output device of the computer can be reduced, the number of connected man-machine interface devices can be increased, or the response characteristics of the computer can be improved.

[Brief explanation of drawings]

FIG. 2 is a block diagram of an input/output control device that is an embodiment of the present invention, which controls data transfer between a computer and an input/output device, and FIG. 2 is an implementation of FIG. 1. FIG. 3 is a flow diagram of the input control state of the input/output control circuit in the embodiment of FIG. 1, and FIG. FIG. 3 is a processing flow diagram on the computer side of the control device. l...Calculation R2...Human output control circuit 3...Status register 4...Command registers 5a, 5b...Transfer amount count register Ga, 6b...
...Address registers 7a, 7b...Store code registers 8a, 8b.
...stop code detection circuits 9a, 9b...hasher register 10...output gate circuit 11...input gate circuit 12...output driver circuit 13...input receiver circuit 21...control bus 22 ... Data transfer side 23 ... Address register 24 ... Interrupt lotus 30 ... Input/output device Patent applicant Fuji Electric Manufacturing Co., Ltd. Fuji Facom Control Co., Ltd. Agent Patent attorney Tetsuya Mori Figure 2 Figure 4 Procedural amendment (spontaneous) February XO, 1980 Kazuo Wakasugi, Commissioner of the Patent Office 1 Indication of the case 1982 Patent Application No. 199241 2 Title of the invention Input/output control device 3 Person making the amendment Relationship to the case Patent application Person name: Fuji Electric Manufacturing Co., Ltd. (and 1 other person) 4 Agent address: 5, Nichiei Patent Office, 917-ku, 9th floor, Tsukugin Building, 4-2 Marunouchi-chome, Chiyoda-ku, Tokyo Target of amendments Figures 2 and 3 6 Contents of correction (1) "Count register 5aJ" on page 21, line 18 of the specification is corrected to "count register 5b." (2) Change the "transfer amount count register 5aJ" on the 5th line of page 22 of the specification to "transfer amount count register 5bJ".
I am corrected. (3) Figures 2 and 3 of the drawings are corrected as shown in Figures 2 and 3 of the attached drawings. Figure 2 above

Claims (2)

[Claims] (1) In an input/output control device that controls data transfer between a processing device and an input/output device, control is performed to send data sent from the processing device to the input/output device as output data. and an input control state that controls sending the data sent from the input/output device to the processing device side as input data, and delimits a series of data sent from the processing device. An input/output control device characterized in that the input/output control device shifts from the output control state to the input control state by detecting the output control state. (2) In response to a command signal from a processing device or an input/output device, the output control state or the input control state is set, and by detecting a break in a series of data sent from the processing device, A patent characterized in that the output control state is shifted from the output control state to the input control state, and the input control state is shifted to the output control state by detecting a break in a series of data sent from the input/output device. An input/output control device according to claim 1.