JPH04274545A - Channel controller - Google Patents

Abstract

PURPOSE:To reduce the burden of data transfer by eliminating the execution of transferring futile data and to prevent the occurrence of the overrun of another channel controller. CONSTITUTION:The channel controller is provided with a register file 6 for matching a peripheral controller 3 and input-output controller 1 to each other, channel control circuit 5 which manages the file 6 and communicates with the controller 3, interruption generating circuit 4 which controls the communication with the controller 1, and overrun detection circuit 7 for detecting overruns and, when the detection circuit 7 detects an overrun at the time of transferring an input, the generation circuit 4 generates a firmware interruption even when input data are stored in the register file 6 and executes service code processing by initializing the file 6 while firmware process is performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel control device, and more particularly to a channel control device that does not perform necessary data transfer as a process when an overrun occurs.

0002

Conventionally, this type of channel control device has different data transfer widths when transferring input/output data, for example, a 1-byte width for a peripheral control device and a 4-byte width for an input/output control device. It has a register file for coordination between the control unit and the input/output control unit.

In output transfer, if there is an empty area of 4 bytes or more in the register file, a request is made to the input/output control unit to read data from the main memory, and when the read data is returned, 4 bytes are simultaneously written to the register file. It will be done. The data stored in the register file is read out one byte at a time and sent to the peripheral control device. In addition, during input transfer, data is written from the peripheral control device to the register file one byte at a time, and when 4 bytes or more of data can be stored, a data transfer request is sent to the input/output control device, and the transfer request is accepted. Then, 4 bytes of write data is sent. However, if the input/output control device is unable to accept data transfer requests from the channel control device for a long time, write data from the peripheral control device is written to the register file from time to time, and eventually the register file becomes An overrun occurs that exceeds the area. At this time, communication with the peripheral control device is stopped, but in communication with the input/output control device, since the write data is stored in the register file, a firmware interrupt cannot be generated immediately, and the main Although it does not write to memory, it sends a data transfer request, drains all write data in the register file, generates a firmware interrupt, and executes a service code sequence.

0004

[Problems to be Solved by the Invention] As mentioned above, when a conventional channel control device detects an overrun in input transfer, communication with the peripheral control device is stopped, but data is not written to the register file within the channel control device. is stored, so it is not possible to immediately generate a firmware interrupt and execute the service code sequence, requesting data transfer from the input/output control unit without writing to main memory, and updating the data in the register file. Since a firmware interrupt is generated after all write data has been ejected, the input/output control device is forced to perform unnecessary operations, resulting in an increased transfer load.

An object of the present invention is to generate a firmware interrupt to interrupt firmware processing when an overrun is detected during input transfer, instead of discharging the write data stored in the register file by data transfer. By initializing with An object of the present invention is to provide a channel control device that can prevent such problems.

[0006]

[Means for Solving the Problems] A channel control device of the present invention includes a register file for matching between a peripheral control device and an input/output control device, and a channel control device for managing the register file and communicating with the peripheral control device. The circuit has an interrupt generation circuit that controls communication with the input/output control device, and an overrun detection circuit that detects an overrun.When an overrun is detected by the overrun detection circuit during input transfer, the register file is Even if input data is stored in the memory, the interrupt generation circuit generates a firmware interrupt, initializes the register file during firmware processing, and executes service code processing.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a system in which channel control devices according to an embodiment of the present invention are connected.

In FIG. 1, the system to which the channel control device of this embodiment is connected is composed of an input/output control device 1, a channel control device 2, and a peripheral control device 3. It is composed of an interrupt generation circuit 4, a channel control circuit 5, a register file 6, and an overrun generation circuit 7.

Next, the operation of the channel control device of this embodiment will be explained.

Data is transferred from the peripheral control device 3 to the main memory control device via the input/output control device 1.

When the channel control device 2 sends an instruction to start input transfer of a control signal from the channel control circuit 5 that controls interlock communication with the peripheral control device 3 via the peripheral control interface 18, the peripheral control The write data sent from the device 3 is sent to the register file 6 via a 1-byte wide data path (1-byte wide) 9, and a register file write instruction 16 indicating the timing to write to the register file 6 is sent as determined by the channel control circuit 5. When the channel control circuit 5 determines that 4 bytes or more of the write data has been stored in the register file 6, it sends the data transfer cause signal 15 to the interrupt generation circuit 4. The sending and interrupt generating circuit 4 sends a data transfer request signal 10 to the input/output control device 1, and when the data transfer request is accepted, an acceptance signal 12 is sent back to the channel that controls communication with the input/output control device 2. When the control circuit 5 responds with information for transferring the control signal via the input/output control interface 17, 4-byte write data is read from the register file 6, and the 4-byte wide data path 8 is read out.
Transfer data is sent using .

However, when the acceptance signal 12 cannot be returned for a long time and the write data sent from the peripheral control device 3 continues to be written to the register file 6 at any time, exceeding the capacity of the register file. , the overrun detection circuit 7 outputs the register file usage rate instruction signal 14.
Overrun is detected based on the information. Further, when an overrun is detected, an overrun instruction signal 13 is sent to the interrupt generation circuit 4 to indicate an overrun. When the interrupt generation circuit 4 receives the overrun instruction signal 13, it cancels the data transfer request signal 10 that it has been sending out, immediately sends out a firmware interrupt request 11, and starts executing the service code sequence.

As described above, conventionally, in this case, if data remained in the register file, a firmware interrupt request could not be sent, so writing to the main memory control unit was prevented and writing in the register file Data transfer is executed until all data is ejected, but in this embodiment, when an overrun is detected, the data transfer request is canceled, a firmware interrupt is generated even if write data is stored in the register file, and firmware processing is performed. Since the register file is initialized within the program, there is no need to perform data transfer after an overrun.

[0015]

[Effects of the Invention] As explained above, the channel control device of the present invention, when an overrun is detected in input transfer,
Rather than discharging the write data stored in the register file by data transfer, by generating a firmware interrupt and initializing it during firmware processing, unnecessary data transfer is no longer executed and data transfer is faster. This has the effect that it is possible to reduce the load on other channel control devices, and to prevent the occurrence of overruns in other channel control devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system connected to a channel control device according to an embodiment of the present invention.

[Explanation of symbols]

1 Input/output control device 2 Channel control device 3 Peripheral control device 4 Interrupt generation circuit 5 Channel control circuit 6 Register file 7 Overrun generation circuit 8 Data path (4-byte width) 9 Data path (1-byte width) 10 Data transfer request signal 11 Firmware interrupt request 12 Acceptance signal 13 Overrun instruction signal 14 Register file usage rate instruction 15
Data transfer factor signal

Claims (1)

[Claims] 1. A register file for matching between a peripheral control device and an input/output control device, a channel control circuit for managing the register file and communicating with the peripheral control device, and a channel control circuit for controlling the input/output control device. It has an interrupt generation circuit that controls communication and an overrun detection circuit that detects an overrun, and when an overrun is detected by the overrun detection circuit during input transfer, the input data is stored in the registration file. The channel control device is characterized in that the interrupt generating circuit generates a firmware interrupt even when the firmware is being processed, initializes the register file during firmware processing, and executes service code processing.