JPS5990066A - Testing device for logical circuit - Google Patents

Abstract

PURPOSE:To prevent the conflict between an output data of a logical circuit to be tested and an input data to the logical circuit of a testing device by providing a logical means which turns off the gate of the testing device when the output enable signal of the logical circuit to be tested has a logical level ''1''. CONSTITUTION:When the output enable signal is set to logic ''0'', the output terminal of an inverter 7 is at the logical level ''1'', so an AND gate 8 turns on when the contents of a driver enable register 2 show logic ''1'' to turn on a gate 6. When the output enable signal is set to logic ''1'', namely, when the input/output buffer 1 of the logical circuit is controlled to an output state, the output terminal of the inverter 7 is at the logical level ''0'', so the AND gate 8 turns off, so that the gate 6 is never turned on. Consequently, this simple circuit constitution prevents the conflict between the outputs of the testing device and logical circuit each other.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a testing device for a logic circuit having input/output terminals. The present invention relates to a logic circuit testing device in which the output gate of the logic circuit is turned off.

[Prior art and problems]

Figure 1 shows a conventional example of logic circuit testing equipment. Figure 2 shows an example of a test pattern? FIG. In Figure 1, 1
2 is an input/output buffer of the logic circuit, 2 is a driver enable register, 3 is an input/output data register, 4 is a comparison circuit, 5 is a waveform generation circuit, and 6 is a gate.

Conventionally, when testing a complete logic circuit, a test device as shown in FIG. 1 is used. In FIG. 1, the human output buffer 1 of the logic circuit which is the device under test is connected to the gate 6 of the test device.
It is bidirectional, connected to the comparison circuit 4 of the test device, receives all the test data from the gate 6 and supplies it to the logic circuit K, and sends the output data from the logic circuit to the comparison circuit 4 of the test device.

Input/output data can be 8 bits or 16 bits depending on the logic circuit configuration.
Usually, it consists of multiple bits such as bits. The output enable signal is set to logic "1" when output data is output from the input/output buffer 1 to the test device. The driver enable register 2 is a control register that outputs logic "1" to turn on the gate 6 when the input/output data is for output.

The input/output data register 3 stores an input/output cover pattern consisting of input data, that is, test data sent to the logic circuit, and output data, that is, expected value data sent from the logic circuit. 5 is NRZ, RZ by the input/output cover turn and clock of input/output data register 3.

It generates waveforms such as The comparison circuit 4 compares the output data from the logic circuit and the input/output cover pattern from the input/output data register 3, and outputs a full error signal if the two do not match.

An example of the test pattern is shown in Figure 32, where the input/output data register 3 is given the input/output data register 3, and the D
RE (driver enable) is applied to driver enable register 2, and CPE (comparator enable) is applied to comparison circuit 4. The test pattern shown in FIG. 2 is for one bit, and a similar test pattern is created for each bit. In the test pattern shown in Figure 2, DRE is set to 1'' so that the input/output turns from tl to 14 are sent to the gfil logic circuit as input data, and the logic circuit from t to 14 is input/output turn as all output data. CPE is set to 1'' to compare with the output data from the circuit. The output from the logic circuit and the input/output cover pattern of the input/output data register 3 are compared by the comparator circuit 4 to determine pass or fail. As is clear from FIG. 2, both DRE(!:CPE) are not set to '1'', but DRE is set to 1'', and the input/output cover pattern of input/output data register 3 is changed to waveform generation circuit 5. : When the output data is output from the gate 6 through the logic circuit Ω, the logic circuit Ω output enable signal is also set to logic “1”, and a case may occur where it collides with the output data from the crowd buffer 1.

Collisions between input data from the test equipment to the logic circuit and output data from the logic circuit to the test equipment can occur due to mistakes in the test pattern creation stage or defects in the logic circuit, but conventionally In such cases, it was discovered by looking at the displayed output waveform, and the only way to deal with it was to complete the entire test. However, if such collisions are repeated, the test equipment or logic circuit driver may deteriorate or be destroyed. In particular, if the test equipment deteriorates or is destroyed, it is impossible to guarantee all normal test results (and the reliability of the test equipment decreases).

[Purpose of the invention]

The present invention solves all of the above problems, and provides a logic circuit testing device that can completely prevent collisions between the output data of a logic circuit, which is a device under test, and the input data to the logic circuit of the test device. The purpose is to provide

[Structure of the invention]

For this reason, the logic circuit testing device of the present invention is fully equipped with gate means for sending input data to the device under test, and comparison means for comparing the data output from the device under test with expected value data. , data Z is passed through a bidirectional input/output buffer whose input/output is controlled by a control signal; all logic circuits to be input/output are the device under test, and a gate-on signal and test data are given to the gate means. A logic circuit that tests a logic circuit by sending all data to the input/output buffer, giving expected value data to the comparison means, and comparing all data output from the human output buffer with the expected value data. The test apparatus is provided with output collision prevention means for completely preventing collision between the output of the logic circuit and the output of the gate means, and the output collision prevention means is configured such that the control signal controls the output of the output buffer to a full output state. The gate-on signal is supplied to the gate means under all conditions, and the control signal controls the input/output buffer to the output state. It is characterized by being configured so that it cant.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to all drawings.

FIG. 3 is a diagram showing one embodiment of the present invention of a logic circuit testing device. In FIG. 3, 7 represents an inverter, 8 represents an AND gate, and 6 to 6 correspond to those shown in FIG.

The present invention provides a gold-plated logic means that turns off all gates of the test device when the output enable signal of the logic circuit that is the device under test is logic "1."

The logic means has an AND gate 8 and an inverter 7 as shown in FIG. 3, one input terminal of the AND gate 8 is connected to the driver enable register 2, and the other input terminal is connected to the inverter connected to the output terminal of

The output enable signal of the logic circuit is supplied to the input terminal of the inverter 7, and the output terminal of the AND gate 8 is connected to the control terminal of the gate 6. Therefore, when the output enable signal is set to logic "0", the output terminal of inverter 7 becomes logic "1", so the driver
When the contents of the enable register 2 become logic "1", the AND condition of the AND gate 8 is satisfied and the gate 6 is controlled to be turned on. However, the output enable signal is logic “1”.
”, that is, input/output buffer 1 of the logic circuit
When the inverter 7 is controlled to be in the output state, the output terminal of the inverter 7 becomes logic "0", so the AND condition of the AND gate 8 is not satisfied and the gate 6 is not controlled to be turned on. For example, when using the test pattern shown in Figure 2, even though the input/output cover is input to the logic circuit from tl to t4, there may be a mistake in creating the test pattern, a defective logic circuit, or other factors. When the output enable signal is set to logic "1" and the input/output buffer 1 is restricted to the output state, even if the content of the driver enable register 2, that is, DRE, is logic "1", the AND・The other input terminal of gate 8 is logic “0”
”, so the output of AND Gerd 8 becomes logical “0
” and gate 6 is turned off. In this way, in the test equipment, the test pattern is designed to send input data to the logic circuit, and when the logic circuit goes into the output state with gate 6 turned on, gate 6 is forced to turn on. ili controlled off.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the data output gate of the test device is controlled to be turned off by the output enable signal of the logic circuit, so that the test device and the logic circuit can be connected to each other with a simple circuit configuration. It is possible to prevent mutual outputs from colliding.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example of a logic circuit testing device, FIG. 2 is a diagram showing an example of a test pattern, and FIG. 3 is a diagram showing an embodiment of the logic circuit testing device of the present invention. DESCRIPTION OF SYMBOLS 1... Logic circuit input/output buffer, 2... Dryno(-enable register, 3... Input/output data register, 4... Comparison circuit, 5... Waveform generation circuit, 6)
...gate, 7゛...inverter, 8...and gate.

Claims (1)

[Claims] Bidirectional, with gate means for transmitting all input data to the device under test, and comparison means for comparing the data output from the device under test with expected value data, and input/output is controlled by control signals. The device under test is a logic circuit into which data is input/output through a covered sofa, and a gate-on signal and test data are given to the gate means to send the data to the input/output buffer, and the data is sent to the comparison means. In a logic circuit testing device which has come to perform all logic circuit tests by giving expected value data and comparing the data output from the human output buffer with the expected value data, the output of the logic circuit and the gate means are Output collision prevention means for preventing collision with the output is provided, and the output collision prevention means controls all of the above gate-on signals on the condition that the control signal does not control the input/output buffer to the output state. Logic characterized in that the gate-on signal is supplied to a gate means and is configured to completely cut off the gate-on signal on the condition that the control signal controls the input/output buffer 7 to be in an output state. Circuit testing equipment.