JPH01184550A - Test circuit for intermediate controller - Google Patents

Abstract

PURPOSE:To test an internal circuit entirely by converting the internal loop back test function of a self-diagnosing function in an intermediate controller to the control function of an external interface. CONSTITUTION:In a loop back test circuit, first and second selection circuits 13 and 14 which select a signal with respect to the control function of the external interface are added. And on a write register 102' being used for an external test similarly as a loop back test, the control signal of operating sequence for an external device is set as a test pattern via the external interface 101. Then, its response pattern is set at a read register 103' being used for the external test, and an MPU 11 reads it, then, executes the check of the action.

Description

[Detailed Description of the Invention] [(Already required)] Regarding a test circuit for an intermediate control device that is located between a host computer and a terminal device and has an interface control function, it has a test circuit that acts as an external device, and has a test circuit that acts on behalf of an external device, The purpose of the intermediate control device is to provide a test circuit for an intermediate control device that can be tested for the above-mentioned intermediate control device, which has at least a control circuit that controls whether or not data can be transmitted and received between an external device and an external device via an external interface. i1
A write register for a loop test and an external test that temporarily holds a test pattern for a loop test applied to the J control circuit and a test pattern for an external test applied to an external device via the external interface, and a write register for the loop test for the test pattern for the loop test. According to the selection of the return test and external test read register that temporarily holds the response pattern from the control circuit and the response pattern from the external device input via the external interface, and the online mode for normal use and the return test mode for testing. a selection circuit that selects an input signal from an external device inputted through the external interface and a test pattern for the loopback test from the write register and supplies it to the control circuit; and an online mode for normal use and an external test for testing. According to the mode selection, a first selection circuit selects a control signal from the control circuit and a test pattern for external testing from the write register and supplies it to an external device via the external interface; and a return test mode for testing. a second selection circuit that selects a response pattern from the control circuit and a response pattern from an external device input via an external interface according to a selection of an external test mode, and supplies the selected circuit to the read register; and a test pattern for testing to the write register. The response pattern set in the read register is read out and is compared with an expected pattern.

[Industrial application field]

The present invention relates to a test circuit for an intermediate control device that is located between a host computer and a terminal device and has an interface control function.

Generally, as shown in FIG. In order to send or send data from one of the input terminal devices 3 to the host computer, it controls transmission and reception with the data multiplexer.

That is, as shown in FIG. 3(b), the intermediate control device l has an MPU II inside, and transmits and receives data between the host computer 2 and the [10 controller 12] via the channel controller IO. It controls whether or not
It has at least a control circuit for sending a request signal to an external device and receiving a response signal to the request, and a control circuit for receiving a request signal from the external device and sending a response signal to the request to the external device.

In order to improve the reliability of the entire system, it is necessary to check whether this intermediate control device operates correctly, and it is extremely important that the test be performed quickly and accurately when required.

[Conventional technology]

Conventionally, testing of intermediate control devices has been carried out using a self-diagnosis method that includes a test circuit that applies a test pattern to a control circuit within the device and outputs a response pattern, and compares the response pattern with an expected value pattern using an MPU within the device. was being used.

FIG. 4 is a configuration diagram of a test circuit in a conventional intermediate control device. In the figure, the whole is a part of the channel controller 10 in the intermediary wholesaler 1, 100 is a control circuit that controls whether or not data can be sent and received, and 101 is an external host computer or! 10 is an external interface connected to the controller and has a driver/receiver inside; 102 is a return test write register that temporarily holds a return test test pattern to be applied to the control circuit;
Reference numeral 103 indicates a return test read register that temporarily holds a response pattern from the control circuit 100 for the test pattern, and reference numerals 104, 105, and 106 indicate the return test read register for temporarily holding the response pattern from the control circuit 100 for the test pattern. This is a selection circuit that switches the input route of a signal.

When online, the online mode designation signal 1040 is "1" and the return test mode designation signal 1060 is "θ".
Therefore, a control signal 1041 from an external device is input to the control circuit 100 via the AND gate 104 and the OR gate 105 via the external interface 101, and a response signal from the control circuit 100 is input to the external interface 101.
is sent to an external device for normal use. On the other hand, in the test mode, the online mode designation signal 1040 is "θ" and the return test mode designation signal 1060 is "1".
Therefore, the control signal 1041 from the external device is not gated to the output of the AND gate 104, and the control signal 1041 for testing the test pattern from the write register 102 is gated.
61 is input to the control circuit 100 via the (Ant-game) 106 and (Or-Game) 105. This test pattern is
The data is read from the internal memory and set in the write register 102 under the control of the MPU II in the intermediate control device.

A response pattern for the given test pattern is output from the control circuit 100, and an output control signal 1030 of the response pattern is set in the read register 103.

The set response pattern is input to the MPU II, where it is compared with the expected pattern to test the operation of the control circuit 100.

[Problem to be solved by the invention]

In this way, conventionally, the control circuit in the intermediate control device used only a test circuit for self-diagnosis.
A problem has arisen in that it is not possible to test the entire device, and in particular, to check the normality of the external interface 101, it is necessary to connect the host computer and the terminal device.

There is also an idea of configuring the test circuit to include a pseudo host circuit or a pseudo terminal circuit within the intermediate control device, but this poses a problem in that the redundant circuit becomes large and the device becomes expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test circuit for an intermediate control device that has a test circuit that acts as an external device and can test all internal circuits.

[Means to solve the problem]

FIG. 1(a) is a block diagram of the present invention. The present invention provides an intermediate control device that includes at least a control circuit 100 that controls whether or not data can be transmitted and received, and an external interface 101 that connects to an external device.
A return test and external test write register 102' temporarily holds a test pattern for external testing given to an external device via 01, and a response pattern from the control circuit 100 to the return test pattern is input via the external interface 101. A return test and external test read register 103' that temporarily holds the response pattern from an external device, and an external 'A'll that is input via the external interface 101 according to the selection of the online mode for normal use and the return test mode for testing. The selection circuit 15 selects the input signal from the input signal from the write register 102' and the test pattern for the loopback test and supplies it to the control circuit 100. A first selection circuit 13 selects a test pattern for an external test from a control signal and a write register 102' and supplies it to an external device via an external interface 101, and according to the selection of a return test mode for testing and an external test mode. A second selection circuit 14 selects a response pattern from the control circuit 100 and a response pattern from an external device inputted via the external interface 101 and supplies it to the read register 103', and a test pattern for testing is sent to the write register 102'. A check means 11 is provided for comparing the response pattern set in the read register 103' with the read expected pattern.

[For production]

In the present invention, by converting the internal return test function of the self-diagnosis function in the intermediate control device into the control function of the external interface, it is possible to test the external connection part including the external interface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(b) is an embodiment diagram showing the configuration of a test circuit in an intermediate control device of the present invention. In this figure, the same parts as in FIGS. 1(a) and 4 are indicated by the same symbols.

The whole is a part of the channel controller 10 in the intermediate control device (1 in Figure 3), 100 is a control circuit that controls whether data can be sent and received, and 101 is an external interface that connects to an external host computer or I10 controller. 102' has a driver/receiver inside; 102' is used for loopback tests and external tests that temporarily holds test patterns for loopback tests given to the control circuit 100 and test patterns for external tests given to external devices via the external interface 101; A write register 103' is a read register for loopback tests and external tests that temporarily holds response patterns from the control circuit 100 and response patterns from external devices via the external interface 101 for the loopback test patterns, 104, 105.10
6 is a selection circuit for switching the input route for the input signal to the control circuit 100 according to the selection of the online mode for normal use and the loopback test mode for testing; 13 is the selection circuit for switching the input route for the input signal to the control circuit 100 according to the selection of the online mode for normal use and the external test mode for testing A first selection circuit 14 switches the input route for the input signal to the interface 101, and a second selection circuit 14 switches the input route for the input signal to the read register 103' according to the selection of the loop test mode for testing and the external test mode. It is.

When online, online mode designation signal 1040
is “1” and both the return test mode designation signal 1060 and the external test mode designation signal 131O are “0”. Therefore, the control signal 1041 input from the external device through the external interface 101 is inputted through the AND gate 104 and the OR gate 105. is input to the control circuit 100, and the control 11
The response signal from the circuit 100 is sent to the external interface 101.
is sent to an external device for normal use.

On the other hand, in the test mode, the online mode designation signal 1040 is "0", and either the return test mode designation signal 1060 or the external test mode designation signal 1310 is "1".

Therefore, the control signal 1041 from the external device is not gated to the output of the AND gate 104.

However, in the present invention, the control signal 1041 is input to the AND gate 141 in the second selection circuit 14, and if the external test mode signal 131.O is "L", the control signal 1041 is input to the read register 103' via the OR gate 142. The signal state can be set to . In addition, external test mode signal 13
10 is "L", the output signal 1061 from the write register 102' gates the AND gate 131 in the first selection circuit 13 and is input to the external interface 101 via the OR gate 132, so that the write It becomes possible to provide the test pattern in the register 102' to an external device via the external interface 101. Therefore, the MPU II in the intermediate control device gives a test pattern to the external device via the write register 102', and observes the response pattern input from the external device via the external interface 101 via the read register 103'. By comparing with the expected pattern, it is possible to check the normality of at least the driver and receiver in the external ink face 101.

Furthermore, in the present invention, if the return test mode designation signal 1060 is 1'' in the test mode, the test pattern test control signal 1 from the write register 102' is
061 is input to the control circuit 100 via the AND gate 106 and the OR gate 105. This test pattern is read out from the internal memory and set in the write register 102' under the control of the MPU 11 in the intermediate control device, and a response back from the control circuit lOO to the test pattern is output as a control signal 1030. 2
is input to the AND gate 140 of the selection circuit. Since the return test mode designation signal 1060 is "1", the logic state of the control signal 1030 is set in the read register 103' via the AND gate 140 and the OR gate 142.

The set response pattern is input to the MPU II, where it is compared with the expected pattern, making it possible to check the normality of the operation of the control circuit 100.

In this way, in the present invention, by setting the external test mode designation signal to "1", the write register 102'
It is possible to apply a test pattern from the external device to an external device and input the response pattern to the read register 103'.

FIG. 2 is a configuration diagram showing an interface between an intermediate control device and an external device in an external test mode of the present invention. In this figure, the same parts as in FIG. 1 tb) are indicated by the same symbols. When giving the test pattern from the write register 102' to an external device, by setting the external test mode designation signal 1310 to "1", the test pattern signal passes through the AND gate 131 and the OR gate 132 and is sent to the external interface 101. It is input to the external interface 20 of the external device 2'. In the external device, if the online mode designation signal 24 is set to "1", the device is used normally, and the input signal is given to the control circuit 23 via the computer 21. The response signal from the control circuit 23 is gated to the AND gate 22, is given to the external interface 101 on the intermediate control device side via the external interface 20, and is further sent to the read register 103' via the AND gate 141 and the OR gate 142. The data is read and checked by the MPIll in the device. Therefore, in the present invention, it is possible to check the normality of the route that is input from the output of the external interface 101 to the external interface 101 via the external device by specifying the external test mode.

The present invention also has an internal feedback test function as a normal self-diagnosis function, sets a control signal as a test pattern in the write register 102' in the same operation sequence as the external interface, operates the control circuit 100,
The response pattern can be read into the read register 103' and its operation can be checked using the MPU II.

In the present invention, first and second selection circuits 13 and 14 for selecting signals related to the control function of the external interface are added to this loopback test circuit. Then, the control signal of the operation sequence to the external device is set as a test pattern via the external ink face 101 in the write register 102', which is also used for external testing as in the loopback test, and the response pattern is used for external testing. It is set in the read register 103' which is also used as
II reads it and performs operational checks.

〔Effect of the invention〕

Therefore, even if there is no host computer or terminal device, the internal circuit of the intermediate control device can act for them, and the entire control device, including the external connection part, can be tested with a simple circuit and at high speed. What can be done becomes possible.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of the present invention, FIG. 1 (inside) is a block diagram of a test circuit in the intermediate control device of the present invention, and FIG. 3 is a configuration diagram of a computer system, and FIG. 4 is a configuration diagram of a test circuit in a conventional intermediate control device. 11... Check means, 13... First selection circuit, 14... Second selection circuit, 15... Selection circuit, 100... Control circuit, 101... External interface, 102' ...Write register, 103'...Read register.

Claims (1)

[Claims] 1) An external test function characterized in that an externally connected control device is tested by converting an internal test function of a self-diagnosis function within the control device into a control function of an external interface. control device. 2) A control circuit (10) that controls whether or not data can be transmitted and received with an external device via an external interface (101).
0), a loopback test that temporarily holds a loopback test test pattern given to the control circuit (100) and an external test test pattern given to the external device via the external interface (101). and an external test write register (102'), which temporarily holds a response pattern from the control circuit (100) to the test pattern for the return test and a response pattern from an external device input via the external interface (101). a lead register (103') for loopback testing and external testing; and the external interface (101) according to the selection of online mode for normal use and loopback test mode for testing.
a selection circuit (15) which selects an input signal from an external device inputted via the write register (102') and a test pattern for the loopback test and supplies it to the control circuit (100); According to the selection of mode and external test mode for testing, the control circuit (
Control signals from (100) and write register (102')
a first selection circuit (13) which selects a test pattern for an external test from the computer and supplies it to an external device via the external interface (101); The response pattern from the read register (100) and the response pattern from the external device inputted via the external interface (101) are selected and the read register (100) is selected.
03'), sets a test pattern for testing in the write register (102'), reads out the response pattern set in the read register (103'), and compares it with the expected pattern. A test circuit for an intermediate control device, characterized in that it has a checking means (11).