JPH0319055A - Data transfer device - Google Patents

Abstract

PURPOSE:To reduce the test cost by securing such a constitution where a test mode control circuit blocks up a lower rank device with reception of a test mode instruction signal, reads out a test command to give an instruction after reception of a data transfer instruction signal and carries out a data transfer test based on the test command. CONSTITUTION:A test mode control circuit 54 receives a test mode instruction signal and sendsa block-up signal to a lower rank device 7 to block it up. At the same time, the circuit 54 receives a data transfer instruction signal and reads out a test command to give an instruction. Then the circuit 54 performs a data transfer test based on the test command. Thus it is possible to carry out the data transfer test without using the device 7, i.e., an input/output device, etc. As a result, the cost and the space can be reduced for execution of the data transfer test.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer device, and particularly to a data transfer device that can test the data transfer device without connecting a lower-level device to the data transfer device. .

[Prior Art] Conventionally, when testing a data transfer device in an information processing system, the test is performed by connecting the data transfer device to a lower-order device, that is, an input/output device or a tester having a data transfer function. In addition, there are rare cases in which a data transfer function is provided within the data transfer device to test the data bus.

[Problem to be Solved by the Invention 1] However, as the scale of an information processing system increases, a large number of data transfer devices and input/output devices for testing these devices are installed below the input/output dedicated processor connected to the main storage device. The tester is connected.

When testing such a large-scale information processing system during manufacturing, preparing input/output devices and test equipment for all data transfer devices requires a large amount of space in the test site. There was a problem in that it was both time-consuming and expensive.

In addition, when testing is performed by connecting input/output devices, etc., when a fault is detected, it is not easy to isolate whether the fault is on the data transfer device side or the input/output device side. For this reason, there was the complicated problem of having to stop the information processing system, turn off the power, change the cable connections, and then replace it with another input/output device and perform the test.

In addition, in a loopback test of a data bus provided in a data transfer device, there was also the troublesome problem that the input/output processor, which is a host device, had to be reconfigured for testing before the test was performed.

[Means for Solving the Problems] In order to solve such problems, the data transfer device according to the present invention has a main storage device in which test commands for testing the data transfer device are stored, and a main storage device that stores test commands for testing the data transfer device, and Based on the test mode designation signal, a blockage signal is sent to the lower device, and a data transfer instruction signal from the host device is used to instruct the readout of test commands, and the test commands read out sequentially by this readout instruction are received and tested. A test mode control circuit that controls execution of the test command, a test command read control circuit that reads test commands to the host device based on a test command read instruction, and a test command read control circuit that reads test commands from the host device based on the test command read instruction. and a command receiving circuit that sends the command to the test mode control circuit.

[Operation] When the test mode control circuit receives the test mode instruction signal, it sends a blocking signal to the lower device to block the lower device, receives the data transfer instruction signal, issues a test command reading instruction, and Executes a data transfer test based on the issued test command.

[Example] Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data transfer device according to the present invention. In the figure, system buses 8 each include main processors 1. Main storage device 2. Input/output processor 3
(Host device) 1 diagnostic processor 4 is connected. Furthermore, a plurality of data transfer devices 5, which are devices under test, are connected to the input/output processor 3 via a data bus 10 and a control signal path 11, respectively, and each data transfer device 5 is connected to a data bus 12 . An input/output control device 6 (low-order device) is connected via a control signal path 13, and an input/output device 7 is further connected to this input/output control device 6. Furthermore, a test command group 21 for testing the data transfer device 5 is stored in the main storage device 2 .

The data transfer device 5 is configured as follows. That is, the data transfer device 5 is connected to the channel control circuit 5.
0, a transmission buffer 51 that stores one transmission data from the input/output processor 3, a selector 52 connected to the transmission buffer 51, and a transmission register 53 connected to the selector 52 and stores one byte of data. , a driver DR that has a storage capacity of 1 byte of data and sends the contents of the transmission register 53 to the input/output control device 6 via the data bus 12; A test mode control circuit 54 that is connected in parallel with the channel control circuit 50 and controls the execution of the test, and a test command group 21 to the input/output processor 3 in response to a test command reading instruction.
A diagnostic command reading control circuit 55 that reads out the
(test command read control circuit), a selector 56 that is controlled by the test mode control circuit 54 to select data from the receiver RE or a read control signal from the diagnostic command read control circuit 55, and a receiving register 57 that has a storage capacity and receives data from the receiver RE or data from the diagnostic command read control circuit 55 via the selector 56;
A receive buffer 58 stores the data for one transmission to the processor 3, and a transmit buffer 5
1 and a command receiving circuit 59 connected in parallel.

Note that the channel control circuit 50 is connected to the input/output processor 3.
Two control signals, a test mode designation signal a and a test mode release signal (not shown) sent from the control signal path 11 are ignored, but all other control signals to be described later are received. , even if you are in test mode.

The test mode control circuit 54 also controls the input/output processor 3.
By receiving two signals, the test mode designation signal a and the test mode release signal, during this time, that is, when the test mode is in progress, a blockage signal (to be described later) is sent to the input/output control device 6. to block the input/output control device, and instead of the input/output control device 6, transmits/receives other control signals to/from the channel control circuit 50, which will be described later. That is, the test mode control circuit 54 processes data transfer control signals (test command read instruction signals) that should originally be transmitted from the input/output control device 6 to the input/output processor in place of the input/output control device 6. and instructs the transmission of this control signal. Based on this instruction, the diagnostic command readout control circuit 55 selects the selector 56. The designated control signal is sent to the input/output processor 3 via the reception register 57 and reception buffer 58. As a result, the input/output processor 3 reads out a test command corresponding to this control command from the test command group 21 in the main memory bag W2 based on this control signal, and transmits it to the command receiving circuit 59. The test mode control circuit 54 inputs the read test command from the command receiving circuit 59 and controls the execution of the data transfer test based on this test command.

Next, FIG. 2 is a sequence diagram showing the data transfer operation of the data transfer device 5. In the same figure, parts equivalent to those of the data transfer device in FIG. 1 are given the same reference numerals, and their explanation will be omitted. In FIG. 2, a to n and d' to n° are control signals for data transfer and testing of this data transfer. The dotted line portion in the figure indicates data transfer operations that are not performed during the test mode. The operation of the data transfer device will be explained in detail based on the sequence diagram of FIG.

First, when the main processor 1 or the diagnostic processor 4 specifies the address of the data transfer device 5, and then specifies the test mode, the input/output processor 3 receives this information and selects the data transfer device at the specified address. A test mode designation a is sent to the test mode 5 via the control signal path 11. The test mode control circuit 54 receives this and sends a blocking signal to the input/output control device 6 to block the connection path to the input/output control device 6, that is, the data bus 12 and the control signal path 13.

Next, the main processor 1 or the diagnostic processor 4 sends a data transfer instruction signal to the input/output processor 3. Upon receiving this, the input/output processor 3 sends an activation signal d to the data transfer device 5 at the designated address. This activation signal d, together with the activation signal d°, would originally be sent to the input/output control device 6 via the channel control circuit 50, and the input/output control device 6 would read out control information as a response signal to this signal. The command signal e' will be transmitted, but the activation signal d'' cannot be received because the connection path is blocked. Therefore, the test mode control circuit 54, instead of the input/output control device 6, transmits this activation signal. Receive signal d.

That is, when the test mode control circuit 54 receives the activation signal d, it instructs the diagnostic command readout control circuit 55 to send out the control information readout command signal e, and controls the selector 56. Based on this instruction, the diagnostic command reading control circuit 55 operates the selector 56, receiving register 57, . Receive buffer 58
This control information read command signal e is sent as an interrupt signal to the input/output processor via the input/output processor.

Upon receiving this, the input/output processor 3 transmits the data control word signal f in the test command group stored in the main memory 2 to the command receiving circuit 59 via the data bus 10. The command receiving circuit 59 which received this data control word signal f,
This is sent to the test mode control circuit 54. This data control word signal f is originally sent to the input/output control device 6 as a data control word signal f°,
The data transfer request command signal g' is sent from the device, but since the connection path is blocked, these signals cannot be transmitted.

Therefore, the test mode control circuit receives this signal instead of the input/output control device 6. The test mode control circuit 54 that has received the data control word signal f again instructs the diagnostic command readout control circuit 55 to send the data transfer request command signal g, and also controls the selector 56. Based on this instruction, the diagnostic command reading control circuit 55 selects the controlled selector 56. This data transfer request command g is sent as an interrupt signal to the turnout processor via the reception register 57 and reception buffer 58. After receiving this, the turnout processor 3 executes the test command group 21 in the main memory 2.
The data h stored in the designated address is transferred to the transmission buffer 51 via the data bus 10.

Note that at this time, the test mode control circuit 54 transmits other control signals (
This transfer data h is stored in the transmission buffer 51 while transmitting and receiving data (not shown). This stored transfer data h is transmitted to the transmission driver DR via the selector 52 and the transmission register 53 and discarded. This data h is originally sent to the input/output control device 6 as data h', and after the data transfer is completed, it is sent from the same device 6 as an end status request command signal j°, but the connection path is blocked. Therefore, these signals cannot be transmitted. Therefore, the test mode control circuit takes over the input/output control device 6. Therefore, after the predetermined data is transferred, the test mode control circuit 54 sends the diagnostic command readout control circuit 55 to the diagnostic command readout control circuit 55. It instructs the end status request command signal j to be sent, and causes the end status request command signal j to be sent as an interrupt signal in the same manner as described above. As a result,
The input/output processor 3 receives this command signal j, reads out the confirmation signal k from the test command group, and sends it out via the control signal path 11. This confirmation signal is received by the channel control circuit 50, and originally sent from this channel control circuit 50 to the input/output control device 6, and as a result,
The device 6 will transmit a termination status transfer signal m° and a subsequent termination command signal n°. However, since the connection path is blocked as described above, the input/output control device 6 cannot do this.

Therefore, the test command reading circuit 54 acting on this behalf
receives this confirmation signal k, instructs the diagnostic command readout control circuit 55 to send out the termination status transfer signal m and the subsequent termination command signal n, and transmits the instructed termination status transfer signal m and termination command signal. n is sent as an interrupt signal. As a result, the input/output processor 3 sends out a test mode release signal (not shown) via the control signal path 11 based on the end status transfer signal m and the end command signal n. Then, the test mode control circuit 54 that has received this test mode release signal performs termination control of a series of data transfer tests, and ends the test.

In addition, in the above data transfer, a transfer test of data transferred from the input/output processor 3 to the input/output control device 6 was explained, but the data transfer test from the input/output control device 6 to the input/output processor 3
For a transfer test of data transferred to the transmission buffer 51 ., specific data i is stored in the main storage device 2 in advance, and this specific data i is transferred to the transmission buffer 51 . Selector 52. Transmission register 53. Through the driver DR, this data i
The receiver RE, selector 56 . Receive register 57.
The data control word signal f may be transferred to the input/output processor 3 via the reception buffer 58.Furthermore, the data control word signal f may include return information, and the received data h may not be discarded by control based on this return information. , further transmits this data h to the receiver RE, selector 56,
Receive register 57. It may also be transferred to the input/output processor 3 via the reception buffer 58.

Further, in this embodiment, the commands sent and received between the input/output processor 3 and the data transfer device are configured to be sent and received via the data bus 10, but all commands are sent and received via the control signal path 11. In this case, both the command reception circuit 59 and the diagnostic command readout control circuit 55 are connected to the control signal path 11 in parallel.

[Effects of the Invention] As explained above, according to the data transfer device of the present invention,
When the test mode control circuit receives the test mode instruction signal, it sends a block signal to the lower device to block the lower device, receives the data transfer instruction signal, instructs to read the test command, and reads the read test. Now that we have configured it to run a data transfer test based on the command:
Data transfer tests can be performed without using lower-order devices, ie, input/output devices, etc., and the cost and space associated with data transfer tests can be reduced. Furthermore, when performing a data transfer test, there is no need to newly set the input/output processor for the test, which has the effect of eliminating the complexity associated with the data transfer test.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the data transfer device of the present invention, and FIG. 2 is a sequence diagram for explaining the operation. 1...Main processor, 2...Main storage device, 3...
... input/output processor, 4... diagnostic processor,
5... Data transfer device, 6... Input/output control device, 7... Input/output device, 21... Test command group, 50... Channel control circuit, 51-...・Transmission buffer, 52.56...Selector, 53...
Transmission register, 54...Test mode control circuit, 55
...Diagnostic command reading control circuit, 57...
Receive register, 58...Receive buffer, 59...
・Command receiving circuit.

Claims (1)

[Scope of Claims] A data transfer device that is located between a higher-level device and a lower-level device of an information processing system and transfers data between these devices, in which a test command for testing the data transfer device is stored. a main storage device that is to be stored, and a blockage signal is sent to the lower-order device based on a test mode designation signal from the higher-order device, and an instruction to read the test command is given by a data transfer instruction signal from the higher-order device; a test mode control circuit that receives test commands sequentially read out according to instructions and controls test execution; and a test command reading circuit that causes the host device to read out the test commands based on the test command read instructions. A data transfer device comprising: a start control circuit; and a command reception circuit that receives the test command read by the host device and sends it to the test mode control circuit.