JPH04227131A - Transmission/reception test circuit - Google Patents

Abstract

PURPOSE:To suppress the increment of software in a central arithmetic processing part as far as possible and to accelerate the self-diagnosis of a transmission/reception test in a transmission/reception test circuit for an LSI or device which performs the transmission/reception of serial data, etc. CONSTITUTION:In the transmission/reception test circuit which performs a test for the transmission/reception operation of data on another device by one device equipped with a transmission part 2 and a reception part 3 under the control of the central arithmetic processing part 1, a mode switching part 4 is provided which forms a test looping back circuit 5 by connecting the transmission part 2 to the reception part 3 when the modes of the transmission part 2 and the reception part 3 are switched to test modes, and also, instructs the transmission/reception operation of the data for test by outputting a control signal to the transmission part 2 and the reception part 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting/receiving testing circuit for an LSI or device that transmits and receives serial data, and more particularly to a transmitting/receiving testing circuit that can autonomously test transmitting and receiving functions. In recent years, some elements or devices such as LSIs configure systems by transmitting and receiving serial data to and from other elements and devices. In order to check whether the function of this serial data transmitting/receiving section operates normally, it is necessary to actually perform a data transmitting operation and check whether the expected data is being transmitted from the transmitting serial port. It is necessary to input received data to the receive serial port and check whether the expected data can be read from the receiver.

0002

[Prior Art] Conventionally, this type of transmitting/receiving test circuit is shown in FIGS.
This will be explained based on FIG. In the figure, the conventional transmitting/receiving test circuit has a transmitting section 2 and a receiving section 3 transmitting and receiving serial data to and from other devices under the control of a CPU 1.
In the test mode, the CPU 1 controls the mode switching section 4 to form a test loopback circuit 5, and transmits test data as serial data from the transmitting section 2 to the receiving section 3 via the test loopback circuit 5. This received test data is inspected by the CPU 1 to determine whether transmission/reception is appropriate.

Next, the operation of the conventional device based on the above configuration will be explained. First, when the system power is turned on, the CPU 1 resets the entire system for initialization, and the transmission data register (TDR) 222 is set as shown in FIG.
) is set. The CPU 1 writes (01)H to the mode register (MR) 41 of the mode switching section 4, thereby setting the bit of the loopback instruction LPB to "1" (step 10).

[0004] The CPU 1 has a reception control register (RCR).
) 310 receive enable REN is set to “1”.
” (step 11) and transmit data register (T
(DR) 222 (--)H of arbitrary data is written (step 12). Further, the CPU 1 has a transmission control register (
Write (01)H to the transmission enable TEN of the transmission control register (TCR) 210 (step 13);
A transmission sequence is started in the transmission unit 2 by writing to the transmission data register (TDR) 210 and the transmission data register (TDR) 222.

[0005] This transmission sequence is controlled by the transmission control register (
The TCR) 210 makes a request to send the start flag FLAG of the frame part to the transmission control unit 220, and sends a request to the send data register (TDR) 222 to send the send data, send the FCS, and send the end flag FLAG. The flags, data, etc. sent out are sequentially formed into a transmission frame as shown in FIG. 9(B) in the frame assembling unit 221 and transmitted (step 14). In order to determine whether or not this transmission has been completed, the CPU 1 reads the transmission completion status T from the transmission status register (TSR) 211.
CP is read (step 15), and it is determined whether the read transmission completion status TCP is (01)H, indicating completion (step 16).

[0006] When the CPU 1 determines that the transmission is complete, a test loopback circuit 5 is formed via a multiplexer (MUX) 42, and the receiving section 3 starts a receiving operation (step 17). This receiving section 3 separates data in a frame detecting section 320 and registers it in a received data register (RDR).
) 312. CPU1 receives data register (R
DR) 312 (step 18), and it is determined whether the read data matches the data transmitted from the transmitter 2 (step 19). If it is determined that the data match in this judgment, the reception status register (R
Read the reception completion status RCP from SR) 311 (
Step 20), determine whether this reception completion status RCP is (01)H, indicating completion (Step 21)
. If the CPU 1 determines that the reception is complete, it determines that the transmission and reception operation is normal (step 22).

[0007] Also, the steps 16, 19,
If the CPU 1 determines (01)H or does not match in step 21, it determines that the transmission/reception operation is abnormal (step 23).

[0008]

[Problem to be Solved by the Invention] Since the conventional transmitting/receiving test circuit is configured as described above, it is necessary to realize a self-diagnosis function using a simple loopback circuit using hardware and complicated software on the CPU side. Not,
This poses a problem in that the burden of software for test operations on the CPU increases, resulting in an enormous amount of software. In particular, the need to transfer large amounts of data necessitates faster communication processing, but there has been a problem in that high-speed self-diagnosis of transmission and reception tests is not possible because the test processing is performed using complex software.

The present invention has been made to solve the above-mentioned problems, and is a transmitting/receiving test that can suppress the increase in software in the central processing unit (CPU) as much as possible, and can perform self-diagnosis of the transmitting/receiving test at high speed. The purpose is to propose circuits.

0010

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention. In the figure, the transmission/reception test circuit according to the present invention performs a test from one device including a transmitting section (2) and a receiving section (3) to another device based on the control of the central processing section 1.
In a transmission/reception test circuit that tests data transmission/reception operations, when the transmission/reception (2) and reception section (3) are switched to test mode, the transmission section (2) and reception section (3) are connected. A test loopback circuit 5 is formed with a mode switching section (4) that outputs a control signal to the transmitting section (2) and the receiving section (3) to instruct the transmitting/receiving operation of test data. It is.

[0011]

[Operation] In the present invention, the mode switching section 4 shifts to the test mode based on the control of the central processing section 1, and the mode switching section 4 controls the transmitting section 2 and the receiving section 3 to execute the test mode. As a result, the software of the central processing unit 1 only sets the test mode, and there is no need to execute the transmitting/receiving routine of the test mode by software, reducing the amount of software for testing and shortening the testing time.

0012

Embodiments (a) An embodiment of the present invention An embodiment of the present invention will be described below with reference to FIGS. 2 to 4. FIG. 2 is a block diagram of the configuration of the apparatus of this embodiment, FIG. 3 is a diagram of the signal format configuration of each register, and FIG. 4 is a flowchart of the test operation of this embodiment.

In each of the above figures, the transmission/reception test circuit according to this embodiment has a CPU 1, a
A transmitting section 2, a receiving section 3, a mode switching section 4, and a test loopback circuit 5 are commonly provided, and in addition to this configuration, a testing section 33 for testing received data is provided in the receiving section 3, and a mode switching Mode register (MR) 41 of section 4
This configuration is configured to send a transmission/reception set signal to the transmission control register 210 of the transmitter 2 and the reception control register 310 of the receiver 3 to control them.

The inspection section 33 includes a frame detection section 320
The receive data and transmit data register (T
DR) 212 to detect a match or mismatch with the expected value of the transmission data, and write a self-diagnosis status CPL to the reception status register (RSR) 311 based on the detection result. Next, the operation of this embodiment based on the above configuration will be explained. First, as a premise, the transmission data register (T
DR) 212 is set to an initial value as shown in FIG. 9(A). This initial value is ignored during normal operation, and the data stored in the transmit data register (TDR) 212 is assumed to be empty. Furthermore, the mode register (M
R) Write "1" to the bit in the test instruction TST for the test command to 41 (step 1).

The mode register (MR) 41 is set to the multiplexer (M
UX) 42 and the inspection unit 33, and also outputs each enable TE for transmission and reception of the transmission control register (TCR) 210 and reception control register (RCR) 310.
Set the bits of N and REN to “1” (Step 2
). A multiplexer (MUX) to which the control signal is input
) 42 to select terminal 2 and test loopback circuit 5.
is formed, and an HDLC transmission frame as shown in FIG. 9(B) is transmitted from the transmitter 2 to the receiver 3 via the test loopback circuit 5 (step 2). This HDLC transmission frame is transmitted from the transmission control unit 220 to the frame unit by a transmission request for a start flag FLAG and a transmission data register (TDR) according to the transmission sequence of the transmission unit 2.
It is formed by sequentially outputting a request for transmitting data 212, a request for sending FCS, and a request for sending end flag FLAG.

Here, the CPU 1 checks the transmission completion status TCP in the transmission status register (TSR) 211.
The read transmission status TCP is (01
)H or not (step 4). Said step 4
If the transmission status TCP is determined to be (01)H, the reception unit 3 sets the reception enable REN bit in the reception control register (RCR) 310 to “1” under control from the mode register (MR) 41. and becomes ready for reception, and receives the transmission data of the HDLC frame sent out via the test loopback circuit 5 (
Step 5). This received data is sent to the frame detection unit 320.
The start and end flags FLAG and FCS are detected, inspected, and deleted, and the data is stored in the receive data register (RDR).
312 (step 5). Further, the received data output from the frame detection section 320 is input to the inspection section 33, and the transmission data register (TDR) 2
Compare with the expected value which is the transmission data input from 12,
If all the received data match the expected values, a set signal is output that sets the self-diagnosis status CPL bit in the reception status register (RSR) 311 to "1" (step 5). Therefore, only when there is no abnormality in the received data in the inspection unit 33, the reception completion status R of the reception status register (RSR) 311 is set at the time of reception completion.
Both bits of CP and self-diagnosis status CPL are set to “1”.
” (Step 5).

Further, the CPU 1 reads the reception completion status RCP and self-diagnosis status CPL from the reception status register (RSR) (step 6), and determines whether or not the reception status register (RSR) is (03)H. Step 7). Based on this judgment, CPU1
is determined to be normal or abnormal depending on whether the reception status register (RSR) is (03)H or another value (steps 8 and 9). Also, if the transmission status register (TSR) 211 is not (01)H in step 4, the CPU
1 is determined to be an abnormal transmission operation (step 9).
).

In this manner, the CPU 1 simply issues the test instruction TST to the mode switching unit 4, and the transmitting/receiving units 2 and 3 execute data transmission/reception, and the testing unit 33 of the receiving unit 3 Since the suitability of the received data is judged by the CPU 1, the amount of software processing in the CPU 1 is minimized, the increase in software can be suppressed, and the speed of the test operation can be increased.

(b) Another embodiment of the present invention FIG. 5 shows a schematic configuration diagram of another embodiment. In the other embodiment device in the same figure, the transmission data from the transmitter 2A is transmitted to another device B via the transmission line 7, and is transmitted via the transmission line 7 by the test loopback circuit 5B of this other device B. It is configured to be received and inspected by the inspection section 4A. By transmitting and receiving test data via the transmission line 7 in this manner, it becomes possible to inspect and test the transmission line 7 for abnormalities.

Furthermore, in each of the above embodiments, the inspection section 33 is provided in the receiving section 3, but the inspection section 3
It is also possible to have a configuration in which the function No. 3 is executed by the CPU 1. Further, in each of the above embodiments, the test transmission data is sent from the transmission data register (TDR) 212 via the frame assembly section 221 and also sent to the inspection section 33. It is also possible to have a configuration in which test transmission data is held in advance and this held data is compared as an expected value.

[0021]

[Effects of the Invention] As explained above, in the present invention,
The mode switching section shifts to the test mode based on the control of the central processing section, and the mode switching section controls the transmitting section and the receiving section to execute the test mode. Only the settings are performed, and there is no need to execute the transmission/reception routine in the test mode using software, which has the effect of reducing the amount of software for testing and shortening the testing time.

[Brief explanation of the drawing]

FIG. 1 is a principle explanatory diagram for explaining the principle configuration of a transmitting/receiving test circuit according to the present invention.

FIG. 2 is a configuration block diagram for explaining one embodiment of the present invention.

FIG. 3 is a signal format configuration diagram of each register in the embodiment shown in FIG. 2;

FIG. 4 is a test operation flowchart for explaining the operation of the embodiment shown in FIG. 2;

FIG. 5 is a schematic block diagram of another embodiment of the present invention.

FIG. 6 is a configuration block diagram of a conventional transmission/reception test circuit.

FIG. 7 is a diagram illustrating a signal format configuration of each register in a conventional circuit.

FIG. 8 is a test operation flowchart of a conventional transmission/reception test circuit.

FIG. 9 shows the initial value of a transmission data register and the configuration of an HDLC transmission frame in a general transmission/reception test circuit.

[Explanation of symbols]

1...CPU (Central Processing Unit) 2...Transmission unit 3...Reception unit 4...Mode switching unit 5...Test loopback circuit 6...Transmission/reception port 7...Transmission line 21...Transmission buffer 22...Transmission control unit 31...Reception buffer 32 ...Reception control section 33...Testing section 41...Mode register (mode control section) 42...Multiplexer (switching section)

Claims (4)

[Claims] 1. A transmission/reception test in which data transmission/reception operations are tested from one device comprising a transmitting section (2) and a receiving section (3) to another device under the control of a central processing section 1. In the circuit, when the transmitting/receiving section (2) and the receiving section (3) are switched to a test mode, the transmitting section (2) and the receiving section (3) are connected to form a test loopback circuit 5. , transmitter (2) and receiver (3)
1. A transmission/reception test circuit comprising a mode switching section (4) that outputs a control signal to instruct a transmission/reception operation of test data. 2. In the transmitting/receiving test circuit according to claim 1, based on the control of the mode switching section 4, test reception data received by the receiving section (3) is converted into test data transmitted from the transmitting section 2. 1. A transmission/reception test circuit comprising: a test section 33 that compares data for use as an expected value and tests received data based on the comparison result. 3. In the transmitting/receiving test circuit according to claim 1 or 2, the test data transmitted from the transmitter (2) does not pass through the test loopback circuit 5, and is transmitted to the other device normally. A transmitting/receiving test circuit characterized in that the signal is transmitted to a receiving section (3) via a transmitting circuit used during transmitting and receiving. 4. In the transmitting/receiving test circuit according to any one of claims 1 to 3, when the transmitting section (2) and the receiving section (3) are switched to a test mode, when the transmitting section (2) is initialized and reset; A transmission/reception test circuit characterized in that a specific value of a test mode is set in a transmission buffer (21) of a transmission section (2).