JP3292307B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC testing apparatus for testing an IC such as a memory.

[0002]

2. Description of the Related Art FIG. 4 shows an outline of a logical comparator used in a conventional IC test apparatus. In the figure, reference numeral 1 denotes an IC under test. This IC under test 1 is supplied with a test pattern signal from the pattern generator 2. The IC under test 1 temporarily stores the test pattern signal, performs a read operation in response to a read command, and inputs the read output to the logical comparator 3 through the analog comparator 4.

In the analog comparing section 4, a reference voltage H of H logic is used.
An analog comparator 4H to which REF is applied and an analog comparator 4L to which L · REF is applied
And determines whether or not the logic level of the logic signal read from the IC under test has the normal H logic level and L logic level. This determination result is punched out by the strobe pulse STRB and output.

That is, the analog comparators 4H and 4L output L logic when the IC under test 1 outputs H logic and L logic having regular levels. Logical comparator 3 is constituted by the gate G ₁ ~G ₇ and the OR gate OR ₁ ~OR _3. The gate G ₁ is the expected value pattern signal operates as a logic comparator for outputting a determination result when the H expected.
The gate G ₂ outputs the expected value pattern signal whose Z expected value (I under test I).
When C1 outputs a potential intermediate between H logic and L logic, it operates as a logic comparator that outputs a determination result.
The gate G ₃ are operated as a logical comparator for outputting a determination result when the expected value pattern signal is L expectations.

[0005] 3A is output the expected value by taking the output of gate G ₁ and G ₃ in the OR gate OR ₁ outputs a defect detection signal H · L · FAIL at H expected values or L expectation, 3B gate output the expected value from the G ₂ outputs a defect detection signal Z · FAIL when Z expectation, 3C is the state of all the expected values taking the logical sum of all of the gate G ₁ ~G ₃ OR gate OR ₂ The output terminal for outputting the failure detection signal FMF is shown.

Conventionally, an output terminal 3D is provided in addition to the output terminal 3C. The output terminal 3D gate G ₄ ~G
An output terminal of the failure detection signal FMC obtained by taking out the determination result of ₆ by the OR gate OR ₃ is shown. From the signal FMC output to the output terminal 3D, it is possible to know the contents of the logic of the output of the IC under test 1 when a failure occurs. That is, as shown in FIG. 5, when the IC under test 1 is normal (pass), the signal FMF is output.
Is L logic, and the signal FMC is undefined. In the case of a failure (fail), the signal FMC is at H logic, and the signal FMC is shown in FIG.
Is defined as In FIG. 6, when the expected value pattern signals EXPH and EXPL are both “0” and “0”,
(In this case, the expected value is called don't care.) Output signal FM
The output of C and the IC under test 1 is undefined.

The expected value is L, that is, the expected value pattern signal E
XPH is "0", EXPL is "1". Output signal FMC is 0.
At this time, the output of the IC under test 1 becomes H logic. Output signal F
If MC is “1”, the output of the IC under test 1 is in the high impedance state Z (an intermediate value between H logic and L logic). When the expected value is H logic, that is, when the expected value pattern signal EXPH is “1” and EXPL is “0”, if the output signal FMC is “0”, the output of the IC under test 1 is L logic and FMC is “1”. In this case, the output of the IC under test 1 has a high impedance Z.

The expected value is Z, that is, the expected value pattern signal E
When XPH is “1” and EXPL is “1”, the output signal F
If MC is “0”, the output of IC under test 1 is H, FMC
Is “1”, the output of the IC under test 1 becomes L.

[0009]

As described above, conventionally, it is determined whether the IC under test 1 is pass or fail based on whether the output signal FMF is 0 or 1, and the output of the IC under test 1 is further determined based on the logical value of the output signal FMC. Although the state can be determined, in order to determine the output state of the IC under test 1, conventionally, the output state of the IC under test 1 must be collated with the expected value pattern signals EXPH and EXPL, that is, whether the output of the IC under test 1 has failed due to H logic. It was not possible to determine whether or not the logic failed.

An object of the present invention is to provide an IC test apparatus capable of knowing the output state of an IC under test when a failure occurs without collating an expected value pattern signal.

[0011]

According to the present invention, an IC under test is provided.
An analog comparator which determines whether the output of the IC has the normal H logic level and L logic level, compares the output of the analog comparator with an expected value pattern signal, detects a mismatch, and fails the IC under test. In a IC test apparatus comprising a logical comparator for detecting a logical comparator, a pair of gates that are controlled to open and close according to the determination result of the logical comparator is provided, and a comparison output of the analog comparator is given to the pair of gates. An IC test apparatus capable of determining the occurrence of a failure and the logic state of the IC under test at the time of the occurrence of the failure by the outputs of the pair of gates is provided.

According to the present invention, the logic comparator is an IC under test.
Is compared with an expected value, and each time a mismatch is detected, a pair of gates is controlled to open. The outputs of the pair of analog comparators are separately provided to the other input terminals of the pair of gates. Therefore, when a failure occurs, the state of the output of the analog comparator is taken out through a pair of gates. Therefore, it is possible to know the occurrence of a failure and the logic state of the output of the IC under test by the signals output from the pair of gates.

[0013]

FIG. 1 shows an embodiment of the present invention. Figure 4 in the figure
The parts corresponding to are denoted by the same reference numerals. In the IC testing device constituted by including an analog comparator unit 4 and the logical comparator 3 in the present invention, a logic comparator 3 three gates _{G 1, G 2, G 3} , 2 pieces of OR gates OR ₁ , OR
Together constituted by _two, it provides an output signal FMF of the OR gate OR ₂ taking out logically OR logical comparison pair of gates 5A, in 5B. In this example, the output signal FMF becomes H logic when a failure occurs. Therefore, by using an AND gate as the pair of gates 5A and 5B,
Each time a failure occurs in the logical determination result, the pair of gates 5A and 5B is controlled to be open by the signal FMF.

On the other hand, the comparison result of the analog comparison section 4 is input to the other input terminals of the gates 5A and 5B. That is, the analog comparator 4 for H logic is connected to the other input terminal of the gate 5A.
Give the output of A. The output of the analog comparator 4B is given to the other input terminal of the gate 5B. The analog comparator 4A has a comparison voltage HR that defines a normal H logic level.
EF is given. When the output signal D _OUT (FIG. 2A) of the IC under test 1 is in a voltage range lower than the comparison voltage H.REF, the output signal SH of the analog comparator 4A is
As shown in B, H logic is output, and when D _OUT becomes higher than H · REF, the output signal SH is inverted to L logic.

The analog comparator 4B has a regular L logic level.
And a comparison voltage L.REF that defines the Test
Output signal D of IC1_OUTIs lower than this comparison voltage
Is the output signal SL of the analog comparator 4B as shown in FIG. 2C.
Maintain the L logic _OUTIs the comparison voltage L · REF
When the voltage rises to a higher voltage, the output signal of the analog comparator 4B
SL is inverted to H logic.

Accordingly, when H logic is output from one of the pair of gates 5A and 5B, it can be understood that a failure has occurred in the logic comparison. Of course, the output signal D of the IC under test 1
_OUT logic can be determined. That is, the gate 5A
When H logic is output from the IC, a failure occurs while the analog comparator 4A is outputting H logic, so that the IC under test 1 generates a failure while outputting L logic. I understand.

When the logic "H" is output from the gate 5B, a failure has occurred while the analog comparator 4B is outputting the logic "H". Therefore, the IC 1 under test outputs the logic "H". In this state, it can be determined that a failure has occurred. On the other hand, both gates 5A and 5B
When the logic is output, it is understood that a failure has occurred while both of the analog comparators 4A and 4B are outputting the H logic. That is, as shown in FIG. 2A, it can be understood that a failure has occurred while the output signal D _{OUT of the} IC under test crosses the area Z (high impedance) between the H logic and the L logic.

FIG. 3 shows the outputs H.RES of the gates 5A and 5B.
The relationship between the logic of ULT and L · RESULT and the logic of the output signal D _OUT of the IC under test 1 is shown. H ・ RESULT and L
When both RESULTs are “0” logic, it means pass (normal).

[0019]

As described above, according to the present invention, the occurrence of a failure and the logic state of the IC under test 1 can be determined based on the 2-bit data of the gates 5A and 5B. Therefore, by storing the 2-bit data in the memory, it is convenient to analyze the cause of the occurrence of the failure, and the advantage that the cause of the occurrence of the failure can be determined in a short time is obtained.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the analog comparator.

FIG. 3 is a diagram for explaining the operation of the present invention.

FIG. 4 is a connection diagram for explaining a conventional technique.

FIG. 5 is a diagram for explaining the operation of the conventional technique.

FIG. 6 is a view similar to FIG. 5;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 IC under test 2 Pattern generator 3 Logical comparator 4A, 4B Analog comparator 5A, 5B Gate

Claims (1)

(57) [Claims] An analog comparator for determining whether a signal output from an IC under test has a regular H logic level and a regular L logic level, and a comparison output of the analog comparator. A logical comparator for logically comparing an expected value pattern and detecting a mismatch to determine a failure.
In C the test apparatus, a pair of gates the logical comparator is braking <br/> control to the open state for each determined as fail provided that the pair of gate
Gives a comparison output of the analog comparator, respectively, and occurrence of fail by the output of the pair of gate, IC testing device configured to be able determine the logical value of the output of the IC at the time of failure occurrence.