JP3223924B2 - Logic comparator for IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test logical comparator used for testing an IC such as a memory.

[0002]

2. Description of the Related Art In an IC test apparatus, a test pattern signal is supplied to an IC under test, and a response output signal is supplied to a logical comparator. The logical comparator compares the response output signal with an expected value pattern signal. Each time it is detected, data of, for example, H logic indicating a failure is written in the failure analysis memory and stored as failure analysis data.

Conventionally, there are a normal comparator system and a double speed comparator system for logical comparators. The normal comparator system has a circuit structure for performing one logical comparison operation in one test cycle, and the double speed comparator system has a circuit structure for performing two logical comparison operations in one test cycle. By adopting the double-speed comparator method, two logical comparisons can be performed within one test cycle, so that a multipoint logical comparison result can be obtained in a short time and the time required for the test can be shortened. The possible benefits are obtained.

FIG. 6 shows a circuit structure of a conventional logic comparator employing a double speed comparator system. In the figure, reference numeral 1 denotes an IC under test. A test pattern signal is supplied from the pattern generator 2 to the IC under test 1, and a response output signal thereof is taken into the logical comparator 3. The expected value pattern signals EXPH1 and EXPH are output from the pattern generator 2 to the logical comparator 3 through the decoder.
XPL1 and EXPH2, EXPL2 are applied to perform logical comparison.

The logical comparator 3 is composed of blocks 3A and 3B. Each of the blocks 3A and 3B independently operates as a logical comparator operating in a normal comparator system, and the two blocks 3A and 3B cooperate to execute a logical comparison operation in a double speed comparator system. Analog comparators 4H and 4L are provided before the blocks 3A and 3B. This analog comparator 4
H and 4L are provided to compare and determine whether the H logic level and the L logic level of the logic signal output from the IC under test 1 fall within a normal voltage range. That is, the comparison voltage HREF is given to the analog comparator 4H,
When the voltage of the logic signal D _OUT output from the IC under test 1 shown in FIG. 7A reaches the comparison voltage HREF or more, the logic L is output. The comparison voltage L is applied to the analog comparator 4L.
When REF is supplied and the voltage of the logic signal output from the IC under test 1 falls below the comparison voltage HREF, the logic L is output. Eventually, these analog comparators 4H and 4L output L logic when the IC under test 1 outputs a logic signal having a regular level. Therefore, the analog comparator 4H is referred to as an H logic analog comparator and the analog comparator 4L is referred to as an L logic analog comparator.

The H logic analog comparators 4H and 4H
The comparison output of the logic analog comparator 4L is input to the blocks 3A and 3B. Since the blocks 3A and 3B have the same structure, only the structure of the block 3A will be described here. The outputs of the H logic and L logic analog comparators 4H and 4L are supplied to the strobe circuits 5H and 5L, sampled by the strobe pulse STRB1, and taken into the first latch circuit 6H and the second latch circuit 6L. These first and second latch circuits 6H, 6L is constituted by D-type flip-flop, and outputs a logic value sampled in strobe 5H and 5L in the positive phase output terminal Q _1.

[0007] The logic data of the IC under test 1 taken into the first and second latch circuits 6H and 6L is applied to one input terminal of each of the gates H and L. The other input terminals of the gates H and L are connected to expected value signals EXPH1, EXPL shown in FIG.
1, EXPH2, EXPL2. Expected value signals EXPH1-EXPL2 are provided as signals for controlling the opening and closing of gates H and L. That is, the strobe pulse STR
When B1 is given at a timing that should be L logic, the expected value is L, so that the gate L is controlled to open. When the strobe pulse STRB1 is given at the timing when it should be at the H logic level, the gate H is controlled to be open. When these gates H and L are controlled to open, the first
It is determined that L logic is given from the second latch circuit 6H or 6L. On the other hand, the gates H and L
And second the H logic from the latch circuits 6H and 6L are input gate H or L outputs logic H, which is judged as defective by being output through the OR gate OR _1, is recorded in the failure analysis memory 7A .

On the other hand taken out phase output signal outputted to the latch circuit 6H and the inverted output terminal Q ₂ of 6L OR gate OR _3, provides an output of the OR gate OR ₃ in gate Z. The expected value signal to be given to the gate Z is obtained by applying a strobe pulse STRB1 at a timing when the signal D _OUT output from the IC under test crosses the middle of the H logic and the L logic, sampling by the strobe pulse STRB1, latching the logic, The value is taken at gate Z.

In block 3A, the strobe pulse STR
The comparison operation is performed only in B1, and only one point can be compared in one test cycle.
For this reason, conventionally, a block 3B having the same structure is additionally provided, and a strobe pulse STRB2 is applied to the block 3B side.
D, the strobe pulses STRB1 and STRB
2 during one test cycle.
For example, it is determined whether the logic of the first half and the second half of _OUT matches the expected value.

[0010]

The logical comparator employing the conventional double speed comparator system requires the block 3B in addition to the block 3A, and has a disadvantage that the circuit scale becomes large.
In particular, in the IC test apparatus, the logical comparators 3 must be prepared by the number of terminals of the IC 1 under test. The number of terminals of the IC under test 1 is as large as several hundreds of pins. For this reason, the IC test apparatus must be made so as to be able to test the multi-pin IC. Therefore, it is necessary to prepare a large number of logical comparators 3 having a large circuit scale. Needless to say, with the increase in the number of parts, the occurrence rate of failures increases, and the reliability decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC testing apparatus which employs a double-speed comparator system, has a small circuit scale, can suppress an increase in cost, and has a small number of parts, so that a failure rate can be reduced. It is intended to provide a logical comparator.

[0012]

In the present invention, the outputs of the analog comparator for H logic and the analog comparator for L logic are separately latched by two latch circuits through a strobe circuit. The two latch circuits output a positive-phase latch output and a negative-phase latch output, and each of the positive-phase latch output and the negative-phase latch output is separately compared with an expected value signal by gate means. When all the outputs of the respective gate means are OR gated and taken out, they can be operated in the normal mode. Further, by providing switching means for separately taking out the result of comparing each positive-phase latch output and the negative-phase latch output with the expected value by the gate means, it is possible to operate in a double-speed comparator system.

Therefore, according to the present invention, it is possible to provide a logic comparator for an IC test apparatus which can operate in a normal mode and a double-speed comparator system with a conventional circuit scale of one block.

[0014]

FIG. 1 shows the configuration of a logical comparator for an IC test apparatus according to the present invention. Parts corresponding to those in FIG. 6 are denoted by the same reference numerals. The structure in which the strobe circuits 5H and 5L are provided at the subsequent stage of the analog comparators 4H and 4L is the same as that described in the prior art, but in the present invention, the strobe circuits 5H and 5L are separately provided with the strobe pulse ST.
Give RB1 and STRB2. Samples sampled by the strobe pulses STRB1 and STRB2 are taken into the first and second latch circuits 6H and 6L, respectively.

Each of the first and second latch circuits 6H and 6L can be constituted by a D-type flip-flop. D-type flip-flop of the positive-phase output terminal Q _1, the negative-phase output terminal Q ₂ respectively and the first gate group 9H consisting AND gate and a second gate group 9L respectively connected. Expectation value pattern signals EXPH, EXPH1 and EXPH are connected to the other input terminals of each of the gate groups 9H and the second gate group 9L.
L, EXPLI.

The output of the first gate group 9H is connected to an OR gate O
R₁And ORed out. The output of the second gate group 9L
OR gate OR_TwoOR circuit O
R₁And OR_TwoThe signal output from the switch is further discussed by the switching means 8.
Operate in normal mode by taking out logically
be able to. In the switching means 8, the gate 8A is
Logic by controlling closed and controlling gate 8B open
Sum gate OR₁And OR _TwoFailure analysis memo for the signal extracted by
7A and 7B can be stored separately,
It can be operated in a rate manner.

That is, in the normal mode, as shown in FIG. 2, the strobe pulses STRB1 and STRB2 are adjusted to the same timing position and applied to the strobe circuits 5H and 5L. In the example of FIG. 2, the strobe pulse STRB1 is located at the position of the high impedance region Z existing between the H logic and the L logic.
And STRB2 are set. The H logic analog comparator 4H outputs H logic in the Z region.
The L logic analog comparator 4L also outputs H logic in the Z region. Accordingly, the two first and second latch circuits 6H and 6L both take H logic.

Here, the expected value pattern in the normal mode is such that the gates / H and / L are opened and the output is L as shown in FIG.
When the logic is output, it is determined to be normal. Thus because crowded preparative H logic of the two first and second latch circuits 6H and 6L, as described above, the reverse phase output terminal Q ₂ L logic is output. As a result a first gate group 9H gate circuit / H of both the second gate group 9 L / L and a gate circuit / H be opened by the expected value pattern signal / L is first
Further, since L logic is given from the second latch circuits 6H and 6L, L logic is given to the failure analysis memory 7A and it is stored that the circuit is normal.

In FIG. 2, the strobe pulse STRB1 is
And STRB2 are set in the first half of the Z area (the area where the signal D _OUT is at L logic).
In this case, the gate circuit H is opened as shown in FIG. At this time, since the latch circuit 6H carries the H logic from the H logic analog comparator 4H, the gate circuit H outputs the H logic. In other words, this case indicates that the expected value and the output of the IC under test 1 do not match.

When the strobe pulses STRB1 and STRB2 are moved to the latter half of the Z region (the region where the signal D _OUT is at the H logic) while the expected value pattern signal remains at H,
The latch circuit 6H reads the L logic as is apparent from FIG. 2B. As a result, the gate circuit H outputs L logic, indicating that the response output signal of the IC under test 1 matches the expected value pattern signal.

The expected value pattern X is don't care. In this case, none of the gate circuits H, / H, L, / L are opened. Therefore, the strobe pulses STRB1 and STRB1
RB2 always outputs L logic and does not transmit a fault signal.
FIG. 4 shows the operation of the double speed comparator system. In this example, the function of determining the state of high impedance Z is omitted, and only the signal D _OUT is determined to be H logic or L logic. In the case of the double speed comparator system, the strobe pulses STRB1 and STRB2 are set at different timing positions. In the illustrated example, the strobe pulse STRB1
In the first half and the strobe pulse STRB2 in the second half.

The switching means 8 controls the gate 8A to close and the gate 8B to open. When LH is given as the expected value pattern shown in FIG. 5 in the relationship between the signal D _{OUT in} FIG. 4 and the strobe pulse timing position, the gate circuits / H and / L are controlled to be open, and the first and second latch circuits 6 are controlled.
And outputs the negative-phase output logic of the terminal Q ₂ of H and 6L. At this time, the negative-phase output terminal Q ₂ is connected to the first and second latch circuits 6H and 6H.
Since both L outputs L logic, L logic is given to the failure analysis memories 7A and 7B, and it is stored that they are normal.

The logic of the first half and the second half of the expected value pattern is LH
In other cases, for example, in the case of HX , only the gate circuit H is opened as is clear from FIG. Since H logic punched by strobe pulses STRB1 to the gate circuit H is applied from the positive phase output terminal to Q ₁ latch circuits 6H, the failure analysis memory 7A given logical H, the signal D _OUT expectation H logic indicating that the pattern does not match is stored. When the expected value pattern is other than LH, H logic is output from _{one of the} OR gates OR _{1 and} OR ₂ and it is determined that they do not match.

[0024]

As described above, according to the present invention, it is possible to configure a logical comparator which operates in a double speed comparator system with a circuit size about half that of the prior art. As a result, IC
Advantages can be obtained in that the circuit scale of the test apparatus can be reduced and cost reduction can be expected.

[Brief description of the drawings]

FIG. 1 is a connection diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the logical comparator according to the present invention in a normal mode.

FIG. 3 is a diagram for explaining a relationship between an expected value pattern and a gate control signal in a normal mode;

FIG. 4 is a waveform chart for explaining the operation of the logical comparator according to the present invention in the double speed comparator system.

FIG. 5 is a diagram for explaining the relationship between an expected value pattern and a gate control signal for opening and closing in the case of a double-speed comparator system.

FIG. 6 is a connection diagram for explaining a conventional technique.

FIG. 7 is a waveform chart for explaining the operation of the related art.

FIG. 8 is a diagram for explaining a relationship between an expected value pattern and an expected value pattern signal in the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 IC under test 2 Pattern generator 3 Logic comparator 4H, 4L Analog comparator 5H, 5L Strobe circuit 6H First latch circuit 6L Second latch circuit 7A, 7B Failure analysis memory 8 Switching means 9H First gate group 9L Second gate group

Claims (1)

(57) [Claims] 1. A. First Embodiment B. an H-logic analog comparator and an L-logic analog comparator that determine whether the H logic level and the L logic level of the logic signal output from the IC under test are the prescribed voltage values; A first latch circuit that latches each comparison result output from the H logic analog comparator and the L logic analog comparator at a desired timing, and outputs a comparison result of the H logic level and a logic opposite to the comparison result, and a first latch circuit L B. a second latch circuit that outputs a comparison result of the logic level and a logic opposite to the comparison result; D. a first gate group in which a latch output of the first latch circuit is applied to one input terminal and an expected value corresponding to H logic is applied to the other input terminal; B. a second gate group in which a latch output of the second latch circuit is applied to one input terminal and an expected value corresponding to L logic is applied to the other input terminal; A state in which all the gate outputs of the first gate group and the second gate group are ORed to output a logical comparison result in the normal mode, and a double speed in which the outputs of the first gate group and the second gate group are separately output. A logic circuit for an IC test apparatus, comprising: a switching circuit configured to switch to a mode for outputting a logical comparison result of a mode.