JP3472972B2 - IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
Test the operation of ICs (semiconductor integrated circuit devices) such as
Related to an IC test apparatus. [0002] 2. Description of the Related Art FIG. 2 shows a schematic configuration of an IC test apparatus.
You. In the figure, reference numeral 1 denotes a pattern generator. This pattern occurs
The unit 1 outputs a test pattern signal and an expected value. 2 is
Test IC, 3 indicates logical comparator, 4 indicates failure analysis memory
You. The test pattern is supplied from the pattern generator 1 to the IC under test 2.
And the response output signal is sent to the logical comparator 3.
input. In the logical comparator 3, the output from the IC under test 2 is
Response output signal and expectation output from pattern generator 1
Logically compares the response output signal with the expected value.
Monitor whether or not. If the IC under test 2 is, for example, a memory,
The test pattern signal given to the IC under test 2 includes an address signal.
The IC under test 2 is added according to the address signal.
To the test pattern at the accessed address.
Write the readout signal and use the readout output as the response output signal.
It is given to the logical comparator 3 and compared with the expected value. Therefore
A mismatch occurs between the response output signal of the test IC and the expected value
Each time the address at which the mismatch occurred
And write, for example, H logic to this defective address.
Is stored as an address at which a defect has occurred. Trial
After the end of the test, the storage of the failure analysis memory 4 is read out,
It is used to analyze the cause. FIG. 3 shows an internal configuration of the logical comparator 3. Argument
The logical comparator 3 performs a level comparison circuit for each terminal of the IC under test 2.
It is configured to include a path 3A and a logical comparison circuit 3B.
The level comparison circuit 3A is connected to the H logic and
And whether the level of L logic has reached a predetermined level
judge. Time when output of IC under test 2 should be H logic
(T shown in FIG. 4_ThreeThe area of the output signal is set in
If the output voltage is lower than the output voltage HV,
It is determined that the logic level does not reach the H logic level.
A fail signal indicating a logic failure is output. [0005] Also, the output signal of the IC under test 2 or L logic
The point in time (T shown in FIG. 4)₀Or T_FiveOutput)
Outputs a voltage whose signal level is higher than the set voltage LV.
Output a normal L logic level voltage
It is determined that there is not, and also in this case, a fail signal of H logic is output.
Power. This fail signal is input to the logical comparison circuit 3B.
It is. In the logic comparison circuit 3B, the level comparison circuit 3A
Output from the pattern generator 1
Logical comparison with the output expected value En is performed. Logical comparison result
As a result, when it is detected that the value does not match the expected value En,
The logical comparison circuit 3B outputs the H logic fail signals F1, F2, F
3. Fn is output and written to the failure analysis memory 4. Each argument
The logical comparison circuit 3B stores the mode set in the comparison mode register 6.
The comparison mode is determined by the mode setting state. Toes
In the comparison mode, the response output signal of the IC under test 2 is
Output normal logic value and voltage on H logic side and L logic side
Logical comparison mode for testing whether or not the IC under test 2
Output terminals are controlled to a high impedance state.
(Hereinafter referred to as Hiz detection mode).
Is called). FIG. 5 shows a level comparison circuit 3A and a logic comparison circuit.
3B shows a specific circuit configuration. The level comparison circuit 3A
The H logic of the response output signal of the IC under test 2 is a normal H logic level.
Voltage comparator CO for determining whether or not the voltage exceeds the bell HV
M1 and the L logic of the response output signal of the IC under test 2 are normal
Determine whether the voltage is lower than the L logic level LV
And a voltage comparator COM2. These two voltage comparators COM1 and COM
2 is the timing area T shown in FIG. ₀Or T_ThreeAt
The strobe pulse ST from the timing generator 5 (FIG. 3)
Is given by the strobe pulse ST.
Whether the output of IC2 is L logic or H logic
Take in. At this time, the logic L of the output of the IC under test 2 becomes
A voltage lower than the normal L logic voltage VL, or
It is determined whether the voltage exceeds the standard H logic voltage HV.
If the logical value is satisfied, L logic is output. On the other hand, the logical comparison circuit 3B has a NAND gate N
AD1 and NAD2 are level comparators COM1 and COM2
Output to the input terminal JI
A logical comparison operation with the expected value En is performed. The expected value En is
If H logic, comparison operation of NAND gate NAD1 is valid
And if the expected value En is L logic, the NAND gate NA
The comparison operation of D2 is treated as valid. [0010] The NAND gate NAD3 is in the Hiz detection mode.
Shows a gate operating with. In other words, in the Hiz mode,
The output voltage of the test IC 2 is a normal H logic voltage HV,
A state existing in the middle of the logical voltage LV is detected. Test
The voltage at the output terminal of IC2 is H logic voltage HV and L logic voltage
When the voltage is an intermediate voltage of the LV (the timing shown in FIG. 4)
Test T₁Or T_FourState) with a strobe pulse ST
Then, both the voltage comparators COM1 and COM2 have H logic.
Output. These two H logic signals are connected to a NAND gate NAD
3 to obtain an L logic signal at its output.
The state of the output terminal of the IC under test 2 becomes the Hiz mode state
If not, the NAND gate NAD3 outputs H logic. NOR gates NOR1 and NOR2 and an AND gate
The gate AND1 is controlled by the control set in the comparison mode register 6.
Switching of the comparison mode is performed by opening and closing control by the control data.
Now. That is, L logic is set in the comparison mode register 6.
Then, the AND gate AND1 is controlled to the closed state,
The gates NOR1 and NOR2 are controlled to be open.
Therefore, in this case, the NAND gates NAD1 and NAD2
The logical comparison result is output to the OR gate OR. H logic is set in the comparison mode register 6.
And the outputs of NOR gates NOR1 and NOR2 are fixed to L logic.
And NOR gates NOR1 and NOR2 are substantially closed.
State controlled. On the other hand, AND gate AND1
Hid detection result of NAND gate NAD3 controlled to open
Through the OR gate OR. Comparison mode is logical comparison
Mode or Hiz detection mode,
Output from the OR logic signal to the H logic signal,
The signal is written to the failure analysis memory 4 as a fail signal.
You. [0013] FIG. 3 shows a conventional configuration.
As described above, arguments provided corresponding to the number of terminals of the IC under test 2 are provided.
One comparison mode register 6 for the logical comparison circuit 3B
It was only provided. Therefore, the IC under test 2
Performs logical comparison of response output signals output from each output terminal.
No test and Hi test to see if you are in Hiz mode
The test in the z detection mode must be performed as a separate test.
I didn't. For this reason, both tests shall be performed
And the time required for testing becomes longer, and a large number of ICs are tested.
If you are in trouble. An object of the present invention is to provide a logical comparison test and a Hiz
Detection mode test can be performed independently for each terminal pin
In the logical comparison test and the Hiz detection mode test.
Reduce testing time when doing both
To provide IC test equipment that can
You. [0015] According to the present invention, a comparison mode is provided.
It has a register and the setting set in the comparison mode register
Set the comparison mode of the logical comparator according to the data.
In the IC test equipment, each terminal of the IC under test
Each logic comparison circuit has its own comparison mode
In this configuration, a register is provided. According to the structure of the present invention, each terminal is provided.
Whether a comparison mode register is provided for the logical comparison circuit
Thus, the comparison mode can be set for each terminal. Obedience
Logic test and Hiz mode test in one test
Can be executed for each terminal. Therefore, discussion in a short time
It is possible to obtain the logical comparison result and the result of the Hiz detection mode.
Benefits that can improve test efficiency.
You. [0017] FIG. 1 shows an embodiment of the present invention.
You. The reference numerals shown in FIG. 1 denote parts corresponding to FIGS.
Are denoted by the same reference numerals. In this invention, logical comparison
Each logical comparison circuit 3B constituting the circuit 3 is provided with a comparison mode register.
It is characterized by a configuration in which a star 6 is provided. Each comparison model
Mode register 6 can be set to any comparison mode.
Control line 7 is connected as follows. Therefore, the logic for each terminal
Comparison mode and Hiz detection mode can be set
You. Also, during the test, the comparison mode is set for each terminal.
Switch from mode to Hiz detection mode and vice versa
Can be performed. Therefore, logical comparison mode can be performed in one test.
Mode and test in Hiz detection mode
Test results in the logical comparison mode and Hi
Test results in the z detection mode can be obtained. [0018] As described above, according to the present invention,
Logical comparison mode and Hiz detection for each terminal of IC under test 2
Mode tests can be mixed and executed at the same time.
You. Therefore, ICs that need to perform both tests can be
The advantage of being able to test a large number of ICs.
The effect is very great when testing.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram illustrating an outline of an IC test apparatus. FIG. 3 is a block diagram for explaining an internal configuration of a logical comparator used in the IC test apparatus shown in FIG. 2; FIG. 4 is a waveform diagram for explaining a timing area in a logic comparison mode and a timing area in a Hiz detection mode in the IC test apparatus. FIG. 5 is a connection diagram for explaining a specific configuration and operation of a conventional logic comparison circuit. [Description of Signs] 1 Pattern generator 2 IC under test 3 Logic comparator 3A Level comparison circuit 3B Logic comparison circuit 4 Failure analysis memory 5 Timing generator 6 Comparison mode register

Claims (1)

(57) [Claims 1] A test pattern signal is given to an IC under test,
In the IC test apparatus configured to logically compare the response output signal and the expected value with a logical comparator and detect a mismatch between the expected value and the defective portion, the comparison mode of the logical comparator is set to the expected value. A comparison mode register is provided for each logic comparison circuit to switch between a logic comparison mode for executing the logic comparison of (1) and a high impedance detection mode for detecting that the output terminal of the IC under test is in a high impedance state. IC test equipment.