JP4664535B2 - Semiconductor device test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device testing apparatus for testing a semiconductor device such as a non-volatile memory called a flash memory or a general-purpose memory such as a DRAM, and in particular, retests focusing on a defective address. Therefore, an object of the present invention is to provide a semiconductor device testing apparatus that can perform failure analysis of a flash memory in a short time.
[0002]
[Prior art]
FIG. 3 shows the configuration of a general memory test apparatus. In the figure, 11 is a timing generator, 12 is a pattern generator, 13 is a waveform shaper, DUT is a semiconductor device under test, 14 is a logical comparator, 15 is a failure analysis memory, and 16 is a tester for controlling the operation of these parts. Indicates a controller.
The pattern generator 12 generates test pattern data according to various timing signals output from the timing generator 11. The test pattern data includes an address signal applied to the memory under test DUT, data to be written into the semiconductor device under test DUT, a control signal for controlling the operation of the semiconductor device under test DUT, and the like.
[0003]
The test pattern data generated by the pattern generator 12 is composed of a digital signal. The test pattern data composed of this digital signal is converted into a test pattern signal having an actual waveform (logic waveform of 1 and 0) by the waveform shaper 13, and the test pattern signal is applied to the semiconductor device DUT under test.
In the semiconductor device under test DUT, the applied test pattern is stored at the address in accordance with the address signal included in the test pattern signal. At the same time, data is read from each address of the semiconductor device under test DUT, and the read data is compared with the expected value output from the pattern generator 12 by the logical comparator 14. If a mismatch occurs as a result of the comparison, fail data representing the mismatch is applied to the failure analysis memory 15. At this time, the address signal applied to the semiconductor device under test DUT is also supplied to the failure analysis memory 15, and fail data indicating that it is a fail address is stored at the address where the mismatch occurred.
[0004]
The fail data fetched into the defect analysis memory 15 is generally used for defect repair processing, but in some cases, it is also used as mask data for subsequent retests. In other words, by storing the address where the failure occurred in the initial test in the failure analysis memory 15, the address where the failure occurred is determined in the next test (semiconductor device test is executed a plurality of times while changing the test conditions). Tests are conducted only on addresses that have been excluded from the test. In such a case, the fail data stored in the failure analysis memory 15 is read out, and at the address from which the “1” logic fail data is read, the “1” logic fail data is used as mask data. 14 is prohibited, and an address determined to be defective in the initial test is excluded from the test target.
[0005]
There are a method of generating mask data from the defect analysis memory 15 and a method of generating from the pattern generator 12. The semiconductor device test apparatus shown in FIG. 3 shows a case where mask data is generated from the defect analysis memory 15. FIG. 4 shows a part of the internal configuration of a failure analysis memory having a mask data generation function.
The defect analysis memory 15 shown here shows a case where a mask data generation unit 15-2 is added to the fail information storage unit 15-1. Both the fail information storage unit 15-1 and the mask data generation unit 15-2 are configured by an address selection unit 15A, a memory control unit 15B, and a memory unit 15C. An address signal identical to the address signal applied from the pattern generator 12 to the semiconductor device under test DUT (see FIG. 3) is input to the address selector 15A. The address selection unit 15A separates the upper bit address signal and the lower bit address signal in the input address signal, the upper bit address signal is applied to the memory control unit 15B, and the lower bit address signal is stored in the memory. Applied to the part 15C.
[0006]
Fail data output from the logical comparator 14 is input to the memory control unit 15B constituting the fail information storage unit 15-1. Fail data is input to the memory unit 15C-1 constituting the fail information storage unit 15-1 through the memory control unit 15B, and the fail data is stored in the memory unit 15C-1.
At the same time, fail data is transferred from the memory unit 15C-1 through the data bus DBUS to the memory unit 15C-2 constituting the mask data storage unit, and the same fail data as the memory unit 15C-1 is transferred to the memory unit 15C-2. Written.
[0007]
When the test condition is changed and the next test is started, the memory unit 15C-1 is set to the write mode, the memory unit 15C-2 is set to the read mode, and the fail read from the memory unit 15C-2 during the test. Data is output as mask data to the logical comparator 14, masking the address where the failure occurred in the initial test, and prohibiting the comparison operation.
FIG. 5 shows an example of the configuration of the pattern generator 12 when mask data is generated by the pattern generator 12. The pattern generator 12 includes a sequence controller 12A, a data generator 12B, a control signal generator 12C, an address generator 12D, and a mask signal generator 12E.
[0008]
Fail data generated by the logical comparator 14 at the time of the initial test or after the completion of the initial test is transferred to the pattern generator 12 through the data bus DBUS, and this fail data is input to the mask signal generator 12E and applied to the semiconductor device DUT to be tested. The fail data is stored at the same address as the address being read.
In the next test after changing the test conditions, fail data is read from the mask signal generator 12E, and this fail data is applied to the logic comparator 14 as a mask pattern.
[0009]
[Problems to be solved by the invention]
For example, in a nonvolatile memory such as a flash memory, there is a phenomenon in which a memory cell that is defective at the beginning of a test gradually transitions to a good cell while writing and reading are repeated for the test. Due to the existence of such a phenomenon, conventionally, a storage area (for example, a page) where a defective address (address where a defective cell exists) has occurred for a predetermined number of times for all addresses of the page. Writing and reading are repeated, and after the writing and reading operations are executed a predetermined number of times, a pass / fail judgment test is performed again.
[0010]
As another example, in order to specify the failure occurrence condition in the non-volatile memory, only with respect to the defective address, for example, the write and read operations are repeated while changing the application condition of the test pattern. In some cases, it may be specified. For this reason, the test of the nonvolatile memory has a drawback that takes time.
For this reason, it is possible to mask the address passed using the mask function described above, write and read only the defective address, repeat the test, and execute the pass / fail judgment test again after a predetermined number of times. It can be shortened.
[0011]
However, as described above, the conventional configuration is such that a mask can be applied only to an address where a failure has occurred. Therefore, the passed address cannot be masked and the passed address cannot be excluded from the read operation. There are inconveniences.
To execute this operation, when writing the fail data to the memory storing the mask data, if the data is “0”, it is converted to “1”, and if the data is “1”, it is converted to “0”. Then, the mask data may be written. However, the conversion of this data must be performed by, for example, the tester controller 16, and the tester controller 16 operates by software, so that the operation is slow, and the memory unit 15C-2 for storing the mask data or the generation of the mask signal Since it must be executed for all the address areas of the unit 12E, there is a disadvantage that time is spent in this respect and the time required for the test becomes longer and longer.
[0012]
An object of the present invention is a semiconductor device that can freely select whether to re-test by masking an address determined to be defective in the initial test, or to perform re-test by masking an address determined to be good. We are going to propose a test device.
[0013]
[Means for Solving the Problems]
According to the first aspect of the present invention, a test pattern signal is applied to a semiconductor device under test, the response output signal is compared with an expected value by a logical comparator, and the occurrence of a mismatch is detected to detect a defective address where a defective cell exists. Information is acquired, the failure address information is stored in the failure analysis memory, and the failure address information stored in the failure analysis memory is applied to the logical comparator as mask data in a subsequent test to mask the failure address. In a semiconductor device testing apparatus having a mask function capable of performing masking, a mask data inversion control unit is provided in a mask data supply path for applying mask data to a logical comparator, and a good address is set by setting the mask data inversion control unit. Whether to mask and test only bad addresses or mask bad addresses and test only good addresses Suggest semiconductor device testing apparatus where the structure can be freely selected.
[0014]
Action <br/> either inverts the polarity of the mask data in the mask data inversion control unit according to the semiconductor device testing apparatus according to the present invention, or a from optionally can be selected and set to passes through the mask data, Whether the fail data stored in the defective address is supplied to the logical comparator as mask data or the pass data indicating the good address stored in the good address is supplied to the logical comparator as mask data Can also be set.
[0015]
As a result, if the fail address information is acquired in the failure analysis memory in the initial test, only the defective address can be tested by masking the good address using the fail address information. The test can also be performed under the reverse condition.
Therefore, for example, there is an advantage that a test for specifying a defect occurrence condition of a defective address can be completed in a short time, for example, writing to a defective address of a nonvolatile memory, repetition of a read operation, or specifying a defect occurrence condition of the defective address.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of a semiconductor device test apparatus according to the present invention. The embodiment shown in FIG. 1 shows an embodiment in which the present invention is applied to a semiconductor device test apparatus configured to generate mask data from the defect analysis memory 15. Parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and redundant description thereof is omitted.
The present invention is characterized in that a mask data inversion control unit 21 is provided in a mask data supply path for applying mask data to the logical comparator 14. In this embodiment, the mask data supply path 20 is shown as a signal supply path for applying mask data from the memory unit 15C-2 storing the mask data to the logical comparator. A mask data inversion control unit 21 is provided in the mask data supply path 20.
[0017]
The mask data inversion control unit 21 can be configured by, for example, an exclusive OR circuit EXOR. Mask data A read from the memory unit 15C-2 is input to one input terminal of the exclusive OR circuit EXOR. An inversion selection signal is applied to the other input terminal of the exclusive OR circuit EXOR to select whether to invert the logic of the mask data A or to pass through the non-inverted state. This inversion selection signal is set in the memory control unit 15B and is given as a logical value of “1” or “0”. When the inversion selection signal is set to logic “0”, the mask data A is set to pass through as it is. When the logic is set to “1”, the mask data A is inverted and output.
[0018]
Therefore, when it is desired to retest only the fail address, the inversion selection signal may be set to “1” logic. By setting the inversion selection signal to “1” logic, when the mask data A read from each address is “0” logic representing a good address, the mask data B output from the mask data inversion control unit 21 is “ 1 "is converted to a signal which is inverted and masked and applied to the logic comparator 14. Therefore, in this case, in the initial test, the address determined to be good is masked, and only the data read from the address having the defective cell is compared by the logical comparator 14 to determine whether it is good or bad.
[0019]
FIG. 2 shows an embodiment in which a mask signal generator 12E is provided on the pattern generator 12 side. This case also shows a case where the mask data inversion control unit 21 is provided in the mask data supply path 20 from the mask signal generation unit 12E to the logical comparator 14. Reference numeral 22 denotes a register for setting an inversion selection signal. By setting an inversion selection signal of “1” or “0” logic in this register 22, it is possible to select whether the mask data A is passed as it is or whether the logic is inverted and output.
That is, as in the embodiment shown in FIG. 1, when “0” logic is set in the register 22, the mask data is passed as it is, and when “1” logic is set, the mask data logic is passed. Invert and output. Therefore, when “1” logic is set in the register 22, the mask signal generator 12E outputs “1” logic as mask data at an address determined to be defective in the initial test, but the mask data of the “1” logic. Is inverted to “0” logic by the exclusive OR circuit EXOR and applied to the logic comparator 14. Therefore, the logical comparison operation is masked for the address determined to be good in the initial test, and the logical comparison operation is executed for the address determined to be defective to determine whether it is good or bad.
[0020]
【The invention's effect】
As described above, according to the present invention, the mask data that communicates with the logical comparator 14 regardless of whether the mask data generator is arranged on the defect analysis memory 15 side or the pattern generator 12 side. A mask data inversion control unit 21 is provided in the supply path 20, and the mask data inversion control unit 21 inverts the mask data from “1” logic to “0” logic, and conversely, “0” logic is inverted to “1” logic. Thus, the address determined as good in the initial test is masked, and the address determined as defective can be tested without masking. Therefore, since only the defective address can be concentrated and tested, the effect is great when applied to a case where a defective address is subjected to a plurality of write and read operations or when a failure occurrence condition is detected. .
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an embodiment of a main part of the present invention.
FIG. 2 is a view for explaining another embodiment of the main part of the present invention.
FIG. 3 is a block diagram for explaining the configuration of a general semiconductor device test apparatus.
4 is a block diagram for explaining a configuration of a failure analysis memory used in the semiconductor device testing apparatus shown in FIG. 3;
FIG. 5 is a block diagram showing an embodiment in which the present invention is applied to a semiconductor device testing apparatus having a configuration in which a mask data generation unit is provided in a pattern generator.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Timing generator 12 Pattern generator 13 Waveform shaper 14 Logical comparator 15 Defect analysis memory 15-1 Fail information storage part 15-2 Mask data generation part 16 Tester controller 20 Mask data supply path 21 Mask data inversion control part EXOR Exclusive OR circuit

Claims (1)

A test pattern signal is applied to the semiconductor device under test, the response output signal is compared with the expected value by a logical comparator, the occurrence of a mismatch is detected, and defective address information in which a defective cell exists is acquired, and the defective address A mask function that stores information in a defect analysis memory and masks the defective address by applying the defect address information stored in the defect analysis memory as mask data to the logical comparator in a later test. In a semiconductor device testing apparatus comprising:
A mask data inversion control unit is provided in a mask data supply path for applying mask data to the logical comparator, and an inversion selection signal set for selecting whether to invert the mask data is supplied to the mask data inversion control unit . the semiconductor device testing apparatus, characterized in that the or a freely selectable arrangement for testing only yo address by masking or defective address to test only the defective address by masking the good address by applying to.

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