JP3406652B2 - Flash memory test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory test apparatus, and more particularly, to a flash memory test apparatus for shortening a test time in an erase test of a flash memory. FIG. 2 is a diagram showing a basic configuration of a general semiconductor memory test apparatus. The semiconductor memory test apparatus includes a timing generator 1, a test pattern generator 2, a waveform shaper 3,
The memory MUT includes a logical comparator 4 and a failure analysis memory 5, and tests the memory under test MUT. The test pattern generator 2 operates in accordance with a reference clock CK generated by the timing generator 1,
It outputs an address signal ADRS, test pattern data TPD, and a control signal CS to be supplied to the UT. These signals are applied to a waveform shaper 3 where they are shaped into a waveform necessary for a test and then applied to a memory under test MUT. The memory MUT under test has a control signal C
S controls writing and reading of the test pattern data TPD. The read data RD read from the memory under test MUT is given to the logical comparator 4, where the expected value data ED output from the pattern generator 2 and the read data RD are compared,
Based on the mismatch, pass / fail judgment of the memory under test MUT is performed. In the case of a mismatch, the failure data FD is supplied from the logic comparator 4 to the failure analysis memory 5, and the memory cell in the failure analysis memory 5 specified by the address signal ADRS generated by the test pattern generator 2 has its failure data. FD
Is stored. After the test, the contents stored in the failure analysis memory 5 are analyzed. FIG. 3 shows the internal structure of the test pattern generator 2. The test pattern generator 2 is an address generator 2
1, test pattern data generator 22, control signal generator 2
3. Address converter 24 and sequence controller 25
Consisting of The sequence controller 25 includes the address generator 2
1, test pattern data generator 22, control signal generator 2
3 is controlled. The sequence controller 25 includes an instruction memory 251 for storing a series of instructions for generating test pattern data, a program counter 252 for specifying an address of the memory 251, and a counter 252.
And a program counter controller 253 for controlling based on the command stored in the program counter 1. The memory area of each address of the instruction memory 251 includes a sequence control instruction area, an address operation instruction area, a data operation instruction area, and a control signal generation instruction area. The instruction memory 251 is accessed by the address output from the program counter 252, and the contents of the accessed location are stored in the program counter controller 253, address generator 21, test pattern data generator 22, or control signal generator 23. Supplied to all. Program counter controller 253
Performs sequence generation by decoding the read sequence control instruction and incrementing and holding the program counter 252, or by loading the read address and generating a new address. Here, the flash memory will be described. Due to its structure, flash memory does not always succeed in writing data by one write operation, so it is usually necessary to perform write operations a plurality of times. The number of times until the writing is successful differs depending on the type of the memory under test MUT, and differs even for the same type of memory under test MUT for each address. In the data write test of the flash memory, if the data can be written to all the memory cells to which the data is to be written within a specified number of times, the memory is determined to be good. The same applies to the data erasure test. If the data can be erased for all the memory cells whose data is to be erased within the specified number of times, the memory is determined to be non-defective. Here, the data erasing test of the flash memory includes a test for erasing the entire memory at once and a test for erasing the memory for each block. An example in which a plurality of flash memories are erase-tested simultaneously and in parallel will be described with reference to the flowchart of FIG. After performing the erasing operation for the entire flash memory MUT to be erased simultaneously or in parallel or for each block, an address is designated to the first address in the range targeted for the erasing operation. , The pass / fail judgment signal output from the logical comparator 4 is recognized. If this is a pass, the next address is specified and the process proceeds to the pass / fail judgment. If the pass / fail judgment is a pass, a third address is further designated to proceed to the pass / fail judgment. This pass / fail determination is repeatedly performed as long as the determination is a pass, until the address reaches the final address within the range targeted for the erase operation. If the final address is determined to be a pass, the entire flash memory MUT or block is determined to be a pass. If the address is designated for the first address and the judgment is not a pass but a fail, the operation proceeds to an erase operation. If the determination after the erase operation has been performed again is pass, the next address is specified as described above and the process proceeds to the pass / fail determination. If it is failed, the erase operation is further performed and the fail continues. The erase operation is performed as many times as the specified number of times. When the pass / fail judgment is “fail” and the number of erase operations reaches the specified number, the entire flash memory MUT or block is determined to be “fail” here. The same applies to the case where the pass / fail judgment is failed at an address in the middle of not reaching the final address. Note that X
Step by one for each erase operation. As described above, when the pass / fail judgment is a pass, the next address is designated, and when the pass / fail judgment is a fail, the operation proceeds to the erase operation. In other words, the memory M to be erase-tested based on the determination result for the address
The pattern given to the UT is determined. That is, the address of the memory MUT to be tested is specified, and the acceptability of the address is determined. The result of the determination is input to the test pattern generator 2, and a pattern is determined based on the input and prepared. Therefore, the waiting time to reach this becomes long. If the pass / fail judgment of an address in the middle of the test target address is failed, pass / fail judgment after the further erase operation is performed again from the first address for the addresses passed by the previous erase operation. Therefore, the test time becomes longer. It is not necessary to judge the pass / fail of the address once passed. The present invention is to provide a flash memory test apparatus which has solved the above-mentioned problems. A logical relationship between read data RD read from a plurality of flash memories MUT to be erase-tested simultaneously in parallel and expected value data ED output from test pattern generator 2 is provided. The comparison is made in the comparator 4,
In a flash memory test apparatus in which a read signal is output from the logical comparator 4 to the test pattern generator 2 when the read data RD and the expected value data ED do not match, a fail signal is output, and when the read data RD and the expected value data ED match, a pass signal is output. A flash memory test apparatus is configured to control a sequence of pattern generation using a signal AFAIL in which all the flash memories MUT to be erased are failed and a signal OFAIL in which one of the memory MUTs is failed. An embodiment of the present invention will be described with particular reference to the flowchart of FIG. In summary, in addition to the pass / fail judgment result in the above-described conventional example, all the flash memories MU to be erase-tested are output from the logical comparator 4.
By controlling the sequence of pattern generation using the signal AFAIL in which T is failed and the signal OFAIL in which one of the memory MUTs is failed after the erase operation, the total erase test time can be reduced. Hereinafter, embodiments of the present invention will be described in detail. First, an erasing operation is performed for the entire flash memory MUT to be erased simultaneously and in parallel or for each block, and then the first address in the range targeted for the erasing operation is added to the flash memory MUT. The address is designated, and a determination is made based on a pass / fail signal output from the logical comparator 4. Up to this point, it is the same as the conventional example described with reference to FIG. According to the present invention, when this address is specified, the test pattern generator 2 generates a pattern for determining an address subsequent to that address, and subsequently performs pass / fail determination. Then, the generated address and the value of the loop counter used for generating the address are held until the determination result is returned from the logical comparator 4. O when any of the memory MUTs has failed
When FAIL is first output from the logical comparator 4, the test pattern generator 2 stores the held address and the value of the loop counter described above. If the result of the pass / fail judgment output from the logical comparator 4 is AFAIL in which all the memory MUTs are failed, the test pattern generator 2 generates a pattern for an erase operation, and the memory MUT
Give to. After the erasing operation is completed, the value of the loop counter stored by OFAIL is loaded into the loop counter, and the pass / fail judgment is performed by specifying an address from the stored first failed address. Here, the address is specified only for the address after the previous failure and the address stored in the test pattern generator 2.
Addresses that have already passed are not addressed . As described above, in the conventional example of the flash memory test apparatus, a pattern to be given next is prepared based on the judgment result from the logical comparator 4. On the other hand, the flash memory test apparatus of the present invention performs pass / fail judgment of the subsequent addresses without waiting for the judgment result of the judgment target address, and sets the FAIL time pattern, that is, the erase operation pattern only when the judgment result is AFAIL. Since this occurs, a standby time required for preparing a pattern for each determination is not required, and the erasing test time is shortened accordingly. Since the pass / fail judgment of the second and subsequent erasing operations is not performed for the addresses that have already passed, the erasing test time is shortened from this point as well.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart illustrating an embodiment of the present invention. FIG. 2 is a block diagram of a flash memory test apparatus. FIG. 3 is a diagram showing a test pattern generator. FIG. 4 is a flowchart illustrating a conventional example. [Explanation of Signs] 2 Test pattern generator 4 Logical comparator MUT Flash memory RD Read data ED Expected value data AFAIL Signal that all memory MUTs have failed OFAIL Signal that any of memory MUTs has failed

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (1)

(57) [Claim 1] A logical comparator compares read data read from a plurality of flash memories to be erased and tested in parallel with expected value data output from a test pattern generator. performs quality determination by comparing the path signal when the coincidence with the fail signal when the expected value data and is not consistent with the data read with respect to the logical comparator or we test pattern generator produce an output Means for outputting a signal AFAIL when all the flash memories to be erased are failed, and outputting a signal OFAIL when any of the memories is failed.
And the address when the signal OFAIL was first output.
The means for storing and continuing the pass / fail judgment and the erasing operation immediately when the signal is AFAIL are performed.
Starts the pass / fail judgment from the stored address.
Means and the erasure test repetition first detect the above-mentioned signal OFAIL
Means for starting pass / fail judgment from the address at the time of
Flash memory testing apparatus, characterized by Bei.