JPH07130199A - Test device for semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate needless access for an address of a memory to be tested and to shorten a test time. CONSTITUTION:Two fail analyzing memory 5A, 5B are provided, test data is given to a memory MUT to be tested with an address specified by a pattern generator 2, also a write enable signal WE is given to the memory to be tested through a prohibiting gate 44, test data is written, the write-in result is read out and compared with an expected value. When uncoincidence is detected, the coincidence signal is written in one side of fail memories. In write-in operation of test data for the memory to be tested, When a test result for the same address as the above which is read out from the other fail analyzing memory is passed, the prohibiting gate 44 is closed and the write enable signal WE is prohibited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test apparatus, and more particularly to a semiconductor memory for controlling the sequence generation of a memory test pattern according to the contents stored in a fail analysis memory in which the fail address of a memory under test is stored. Regarding test equipment.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG. Figure 5
FIG. 6 is a diagram showing a conventional basic configuration of a semiconductor memory test device. The semiconductor memory test apparatus is composed of a timing generator 1, a pattern generator 2, a waveform shaper 3, a logical comparator 4, and a fail analysis memory 5, and tests the memory under test M.

The pattern generator 2 has an address signal ADRS and a test data signal TPD which are supplied to the memory under test M in accordance with a reference clock CK generated by the timing generator 1.
The control signal CS is output. These signals are applied to the waveform shaper 3, where they are shaped into the waveform required for the test and then applied to the memory under test M. For the memory under test M, the control signal CS controls the writing and reading of the test data signal TPD. The signal of the test result read from the memory under test M is given to the logical comparator 4, where the expected value data ED output from the pattern generator 2 and the read test result are compared, and their coincidence, Whether or not the memory under test M is defective (pass or fail) is determined based on the mismatch.

When the test result and the expected value data ED do not match, a fail signal is output from the logical comparator 4 to the fail analysis memory 5 and a fail specified by the address signal ADRS generated from the pattern generator 2 is performed. This fail information is stored in the cell in the analysis memory 5. After the test is completed, the fail address of the memory under test M can be analyzed by examining the contents of the fail analysis memory 5.

Now, the pattern generator will be described with reference to FIG. The pattern generator 2 includes an X address generator 21.
_X , Y address generator 21 _Y , test data generator 22,
It is composed of a control signal generator 23, a sequence controller 24 for controlling these, and an address descrambler 25. Sequence control unit 24, based on instruction memory 24 ₁ a series of instructions stored for the pattern generation, the program counter 24 ₂ to specify the address, the program counter 24 ₂ in the instruction from the memory 24 ₁ It is composed of a program counter controller 24 _{3 for} controlling. The memory area of each address of the instruction memory 24 ₁ includes a sequence control instruction area, an address operation instruction area, a data operation instruction area, and a control signal generation instruction area.

The instruction memory 24 ₁ is accessed by the address output from the program counter 24 ₂ , and the contents are respectively stored in the program counter
It is given to the controller 24 ₃ , the address generator 21, the test data generator 22, and the control signal generator 23. The program counter controller 24 ₃ performs sequence generation by decoding the read sequence control instruction and incrementing or holding the program counter, or loading the read address and generating a new address.

The address generator 21 has an X address calculator and a Y address calculator, and generates an X address signal and a Y address signal in accordance with an address generation instruction of the instruction memory 24 ₁ . The data generator 22 and the control signal generator 23 similarly generate the data signal TPD and the control signal CS. The address descrambler 25 performs address conversion of the address output from the address generator 21 according to a conversion table stored in advance in an internal memory and outputs the address.

FIG. 7 is a diagram for explaining the sequence control section 24 of the pattern generator in more detail. Portions not directly related to the present invention are omitted. As described above, the sequence control unit 24 uses the instruction memory 24 ₁ ,
Program counter 24 ₂ , program counter
It is composed of the controller 24 ₃ . In FIG. 7, the program counter controller 24 ₃ is shown in a more detailed exploded view as compared with FIG.

When the execution of the pattern generation program stored in the instruction memory 24 ₁ is started, the start address register 24SR storing the start address is selected by the multiplexer 24M and the start address is stored in the program counter 24 _2. Is loaded. The sequence control instruction of the instruction memory 24 ₁ designated by this start address is decoded, and the program counter 2
The next operation of 4 ₂ is determined. Program counter 2
4 ₂ will eventually hold (NOP), to perform any of the increment (INC), the load (LOAD).
When loading, the load data can be an operand in the instruction memory by a sequence control instruction,
Either the start address register 24SR or the branch address register BR is selected by the multiplexer 24M.

By the way, one of the instructions of the pattern program is a match flag sense instruction. This is an instruction for controlling the generation of the sequence according to the logical comparison result of the output of the memory under test MUT. When this instruction is executed,
When the output of the specified pin of the memory under test MUT matches the expected value data ED, it is said that a match is found, and the logical comparator 4 outputs the match flag signal MF to the pattern generator 2. This flag signal MF causes the program counter 24 ₂ to advance by +1. When a match can not be taken, the operand multiplexer 24M in the program counter 24 ₂ from the instruction memory 24 ₁
Loaded via. The pattern program is usually made to form a loop that waits for the flag signal MF until a match is found. If no match is found after executing the loop a specified number of times or more, the branch address register 24
Branch to the address specified by BR. In addition to this, there is a flag sense instruction that performs another operation, but the description thereof will be omitted.

The flash memory will be described below. Flash memory is a large-capacity, non-volatile memory that can be rewritten many times. Data read mode, write mode (program mode),
A program verify mode (program verify mode), an erase mode, and a series of other operation modes are provided. These operations are controlled by externally writing a specific command to the controller inside the memory by a write enable signal. The flash memory does not have a dedicated terminal as a terminal for inputting this command but shares it with the data terminal, and switching between the data and the command is performed by, for example, changing the voltage of a specific power supply terminal.

FIG. 8 is a diagram for explaining the procedure of the flash memory write test. In the first test, first, an address is applied to the memory under test, and a program setup mode command is written from the data terminal to set the program mode. In program mode, write data from the data pin. Next, when the program verify mode is performed while holding the write data, the controller inside the memory reads the data and compares it with the write data. If they do not match, program from the memory under test
Since the fail signal is output, it is determined that writing has failed (fail) at this address. While storing the fail address in the fail analysis memory, this series of operations is repeatedly executed for all the addresses to be tested.

In the write test of the flash memory, normally, only one write test does not always pass all the addresses. Therefore, even in the second and subsequent tests, the same address sequence is used for a plurality of tests. To do. By the way, the flash memory is specified not to be rewritten at an address where data has already been written successfully. Therefore, refer to the fail analysis memory that stores the test results up to the last time,
The write enable signal to the memory under test is prohibited for the addresses that have already passed. In this way, when data can be written in all the memory cells in which data is to be written within the specified number of times (for example, within 20 times), it is determined as a non-defective product.

[0014]

By the way, when the write test of the flash memory is repeated by repeating the write test once for all addresses by the semiconductor memory test apparatus shown in FIG. 5, the number of write times usually increases. Although the number of addresses that have not passed the test decreases as the test progresses, the test time is the same every time in the above-mentioned test because all addresses are generated for each write count. That is, for the addresses that pass the test, the write enable WE is masked by the pattern generation program for each test, but this is substantially equivalent to the execution of the test in the operation cycle. However, there is a problem in that the number of tests itself does not decrease and therefore the test time does not decrease.

An object of the present invention is to provide a semiconductor memory test apparatus which solves the above problems and shortens the test time.

[0016]

A semiconductor memory test apparatus according to the present invention repeatedly generates a series of addresses from an initial value to a final value in a desired sequence, and at the same time, test data to be written in the memory under test, and Expected value data to be compared with the data read from the memory under test, and a control signal including an operating state control signal for controlling the operating state of the memory under test are generated, and the series of the series of data is stored in the memory under test. The data read from the memory under test and the expected value data are compared with each other by comparing the pattern generation means for giving an address, the test data, and the control signal to perform writing and reading, and whether they match or do not match. The logical comparison means for outputting a determination result indicating whether or not and the above-mentioned series of addresses are sequentially given, and the read mode is repeated for each repetition of the above-mentioned series of addresses. And the write mode are alternately switched to each other, and the previous determination result read from the fail analysis memory in the read mode is given to each address of the series of addresses, and the previous determination is performed. If the results match, the operation state control signal supplied to the memory under test is prohibited to inhibit writing to the memory under test, and if they do not match, the operation state control signal is applied to the memory under test. Inhibiting gate means for performing write / read to the memory under test, and writing the comparison result by the logical comparison means for the data read from the memory under test to the fail analysis memory in the write mode. Has been done.

[0017]

FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, in this embodiment, the write enable signal WE from the waveform shaper 3 is applied to the write enable terminal WE of the memory under test MUT via the inhibit gate 44. Furthermore, in this embodiment, two fail analysis memories 5 are used.
A and 5B are provided, and these two fail analysis memories are controlled by the read / write control signals RWA and RWB so that one is in the read mode and the other is in the write mode. Also, the match flag MF from the logical comparison unit 4 and the fail analysis memories 5A and 5A similar to those described above are used.
Any one of the fail information FAIL read from B is selected by the multiplexer 6 and given to the pattern generator 2 as a match flag MF ′. Fail analysis memory 5A
The read output of the fail analysis memory 5A or 5B is also applied to one input terminal of the inhibit gate 44.
When the previous test result read from is fail, the inhibit gate 44 is opened to allow the write enable signal WE to pass, and when the previous test result is pass, the inhibit gate 44 is closed to inhibit the write enable signal.

In this embodiment, as will be described in detail later, FAIL information obtained by the previous write test is written in one fail analysis memory, for example, 5B, and the memory under test of the memory under test MUT is written in this write test. For each address, if FAIL = 1 is written in the corresponding address of the fail analysis memory 5B as the previous test result, a write test is performed by executing program setup, program (write), and program verify, and the result is FAIL. If so, it is written to the corresponding address of the fail memory 5A, and if FAIL = 1 is not written to the fail analysis memory 5B (that is, if it is a pass), these operation cycles are omitted and the operation immediately proceeds to the next address. Is configured. Therefore, as the number of addresses that have become paths increases as the write test progresses, the time spent for those addresses can be shortened, and a write test for many memories can be executed in a short time. At the start of the next writing test,
The contents of the fail analysis memory 5B are erased, the same test is then performed while referring to the FIAL information of the fail analysis memory 5A, and the fail information of the test result is written in the fail analysis memory 5B.

FIG. 2 is a diagram for explaining the procedure of the second and subsequent write tests of the flash memory according to the embodiment of FIG. In the first write test, the multiplexer 6 selects the output of the logical comparison unit 4, and the write test result is not yet written in the fail memory. The write test is sequentially performed for each address without referring to the above, and the obtained FAIL information is written to the corresponding address of one fail memory, for example, 5A. When the first write test is completed, the write count RETRY is set to 2 in step S1, and the other fail memory 5B is erased in step S2. Next, in step S3, the initial address ADD = 0 is generated, and in step S4, the previous FAIL information of the corresponding address in the fail memory 5A is read out, and it is checked whether writing (programming) has already been completed. If writing has not been completed, an address is applied to the memory under test in step S5, a command for the program setup mode is written from the data terminal, and the program mode is set in step S6. In the program mode, write data from the data terminal.

Next, in step S7, the program verify mode is executed while holding the write data.
The controller inside the memory reads the data and compares it with the written data. If they do not match, the memory under test outputs the program fail signal FAIL, so it is determined that the writing has failed (fail) at this address, and FAIL is written at the corresponding address of the fail memory 5B. In step S8, it is checked whether the address ADD has reached the maximum address MAX. If not, the address ADD is incremented in step S9, the same write test is performed again in step S4, and the FAIL comparison result is used as the fail analysis memory 5A.
While storing in, the series of operations are repeatedly executed for all the addresses to be tested. If the address ADD reaches the maximum address in step S8, step S1
Check 0 to see if all addresses are PASS.

In this embodiment, if the previous write test result read from the corresponding address of the fail analysis memories 5A and 5B is pass (programmed) in step S4, three steps S5, S6,
By not executing the write test of S7 and jumping to step S8, it is possible to considerably reduce the time as a whole memory test. Instruction memory 2
An instruction program for executing such steps S4 to S9 described in 4 ₁ can be represented as shown in FIG. 3, for example.

In FIG. 3, the sequence generation command area A
The code NOP shown in R1 represents an operation code for simply incrementing the instruction address by the program counter 24 ₂ . The conditional jump code JIP provided at the address ST0 of the instruction memory jumps to the address ST1 of the instruction memory if the previous pass was a pass, and otherwise executes the NOP operations of the following three addresses. Instructions for generating control signals for program setup, program, and program verify are written in the instruction control signal generation areas AR4 of these three addresses, respectively.
The jump code JMX is written in the address ST1 of the instruction memory, and the test address AD
D is incremented and counter address ST0
Jump to. Therefore, by executing the instruction sequence shown in FIG. 3, step S4 in FIG.
~ S9 can be repeatedly executed.

FIG. 4 shows an example of a timing chart for executing the instruction sequence of FIG. At the test address A for the MUT, the previous test result information M read from the fail analysis memory 5A or 5B.
The case where F ′ is FAIL is shown, and therefore, the write test of this time is executed in three cycles of program setup (data application), program (write), and program setup (read). At the next two test addresses A + 1 and A + 2, the previous test result information MF ′ read from the fail analysis memory is PASS.
In the case of these test addresses, the above 3
Skip one cycle and immediately go to the next test address A +
Go to 2, A + 3. Therefore, the test time of the MUT is shortened accordingly.

In the flash memory write test, normally, only one write test does not always pass all addresses. Therefore, it is confirmed in step S11 that the write count RETRY has not reached the specified count MAX, and then step S12 is performed. The write count RETRY is incremented in step S13, the fail memory 5A used for reading the previous FAIL information is erased in step S13, and step S13 is executed.
Return to 3. Also in the third and subsequent write tests, the test is repeated with the same address sequence. As described above, the flash memory is specified not to be rewritten at an address where data has already been written successfully. Therefore, the fail analysis memory storing the test results up to the previous time is referred to, and the write enable signal to the memory under test is prohibited by the prohibition gate 44 for the addresses that have already passed. In this way, when data can be written in all the memory cells in which data is to be written within the specified number of times (for example, within 20 times), it is determined as a non-defective product.

[0025]

As described above, according to the present invention, for an address whose test result up to the previous time is pass, the number of test times is increased by generating a sequence of advancing to the next address without writing and testing. Can be reduced, and the test time can be shortened accordingly.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention.

FIG. 2 is a flowchart of an embodiment of the present invention.

FIG. 3 is a part of a micro instruction sequence for generating a test pattern.

4 is a time chart of a test pattern generating operation according to the instruction sequence of FIG.

FIG. 5 is a diagram showing a basic configuration of a conventional semiconductor memory test device.

FIG. 6 is a diagram illustrating a pattern generator in the apparatus of FIG.

7 is a diagram illustrating a sequence control unit of the pattern generator in FIG.

FIG. 8 is a diagram illustrating a procedure of a flash memory write test, in which (a) is a timing chart and (b) is a timing chart.
Is a flow chart.

[Explanation of symbols]

 1 Timing Generator 2 Pattern Generator 3 Waveform Shaper 4 Logical Comparator 5 Fail Analysis Memory 6 Multiplexer MUT Semiconductor Memory Under Test

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 16/06 G11C 17/00 309 E

Claims (2)

[Claims] 1. A series of addresses from an initial value to a final value are repeatedly generated in a desired sequence, and the test data to be written in the memory under test and the data read from the memory under test should be compared. Generates expected value data and a control signal including an operation state control signal for controlling the operation state of the memory under test, and writes the series of addresses, the test data and the control signal to the memory under test and writes them. A pattern generating means for performing reading, a logical comparison means for comparing the data read from the memory under test and the expected value data, and outputting a determination result indicating whether they match or do not match, The above-mentioned series of addresses are sequentially given, and two modes are alternately switched between the read mode and the write mode each time the series of addresses are repeated. At each address of the failure analysis memory and the series of addresses, the previous determination result read from the fail analysis memory in the read mode is given, and if the previous determination result is the same, the memory under test is The supplied operating state control signal is prohibited to prohibit writing to the memory under test, and if they do not match, the operating state control signal is given to the memory under test to perform writing and reading to the memory under test. And a prohibition gate means for writing the comparison result of the logic comparison means with respect to the data read from the memory under test to the fail analysis memory in the write mode. 2. The semiconductor memory test apparatus according to claim 1, wherein the pattern generation means is given the previous comparison result read from the fail analysis memory, and if the comparison result is a match, the device under test is tested. It includes means for skipping a test data application cycle, a write cycle, and a read cycle for the memory, and immediately updating the generated address.