JPH05223891A - Logical comparator for ic testing device - Google Patents

Abstract

PURPOSE:To provide a logic comparator for use in an IC testing device which logically compares the output signal from each IC to be tested with an expectation value pattern signal, wherein the configuration of the logic comparator to operate in the double speed comparing system is simplified to lessen the circuit size of this testing device. CONSTITUTION:The outputs of a pair of analog comparators 4H, 41, are sampled by stroke circuits 5H, 5L which are given respective stroke pulses, and the sampling outputs are taken in two latch circuits 6H, 6L. The positive phase output and counter-phase output of each of the latch circuits 6H, 6L are taken out by gate means H,/H and L,/L, whose opening and closing are controlled in accordance with the expectation value pattern, and thereupon judging about identical or not identical is conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test logic comparator used when testing an IC such as a memory.

[0002]

2. Description of the Related Art In an IC tester, a test pattern signal is applied to an IC under test, and its response output signal is applied to a logical comparator, and the logical comparator compares the response output signal with an expected value pattern signal. Each time it is detected, for example, H logic data representing a defect is written in the defect analysis memory and stored as defect analysis data.

Conventionally, there are a normal comparator system and a double speed comparator system as logical comparators. The normal compare method has a circuit structure that performs a logical comparison operation once within one test cycle, and the double speed comparator method has a circuit structure that performs a logical comparison operation twice within one test cycle. By adopting the double speed compare method, the logical comparison can be performed twice within one test cycle, so that it is possible to obtain the logical comparison result of multiple points in a short time, and to shorten the time required for the test. The advantage that can be obtained is obtained.

FIG. 6 shows a circuit structure of a conventional logical comparator which adopts a double speed comparator system. In the figure, 1 indicates an IC to be tested. A test pattern signal is applied from the pattern generator 2 to the IC under test 1, and the response output signal thereof is taken into the logic comparator 3. The expected value pattern signals EXPH1, EPH1, E
XPL1 and EXPH2 and EXPL2 are applied to perform a logical comparison.

The logical comparator 3 is composed of blocks 3A and 3B. The blocks 3A and 3B each independently operate as a logical comparator that operates in the normal compare method, and the two blocks 3A and 3B cooperate to execute the logical comparison operation in the double speed comparator method. Analog comparators 4H and 4L are provided in front of the blocks 3A and 3B. This analog comparator 4
H and 4L are provided to compare and determine whether the H logic level and the L logic level of the logic signal output from the IC under test 1 are within the normal voltage range. That is, the comparison voltage HREF is given to the analog comparator 4H,
When the voltage of the logic signal D _OUT output from the IC under test 1 shown in FIG. 7A reaches or exceeds the comparison voltage HREF, the L logic is output. Further, the comparison voltage L is applied to the analog comparator 4L.
When REF is applied and the voltage of the logic signal output from the IC under test 1 drops below the comparison voltage HREF, L logic is output. After all, these analog comparators 4H and 4L output L logic when the IC under test 1 outputs a logic signal having a normal level. Therefore, the analog comparator 4H will be referred to as an H logic analog comparator, and the L will be referred to as an L logic analog comparator.

H logic analog comparators 4H and L
The comparison output of the logic analog comparator 4L is input to the blocks 3A and 3B. Since the blocks 3A and 3B have the same structure, only the structure of the block 3A will be described here. The outputs of the H logic and L logic analog comparators 4H and 4L are given to the strobe circuits 5H and 5L, sampled by the strobe pulse STRB1, and taken into the first latch circuit 6H and the second latch circuit 6L. Each of the first and second latch circuits 6H and 6L is composed of a D-type flip-flop and outputs a logical value sampled by the strobe circuits 5H and 5L to the positive phase output terminal Q ₁ .

The logic data of the IC under test 1 fetched by the first and second latch circuits 6H and 6L is given to one input terminal of each of the gates H and L. At the other input terminals of the gates H and L, expected value signals EXPH1 and EXPL shown in FIG. 8 are provided.
1, EXPH2, EXPL2 are provided. Expected value signals EXPH1 to EXPL2 are provided as signals for controlling opening / closing of gates H and L. That is, strobe pulse STR
If B1 is given at a timing that should be L logic, the expected value is L, so the gate L is controlled to open. Further, when the strobe pulse STRB1 is given at the timing which should be the H logic level, the gate H is controlled to be open. When these gates H and L are controlled to open, the first
And it is determined that the L logic is given from the second latch circuit 6H or 6L to be normal. On the other hand, the gates H and L have the first
When the H logic is input from the second latch circuits 6H and 6L, the gate H or L outputs the H logic, which is output through the OR gate OR ₁ and is determined to be defective and recorded in the defect analysis memory 7A. ..

On the other hand taken out phase output signal outputted to the latch circuit 6H and the inverted output terminal Q ₂ of 6L OR gate OR _3, provides an output of the OR gate OR ₃ in gate Z. The expected value signal given to the gate Z is given a strobe pulse STRB1 at a timing when the signal D _OUT outputted from the IC under test 1 crosses the middle of the H logic and the L logic, and is sampled by the strobe pulse STRB1 and latched for logic. Take the value at gate Z.

In block 3A, strobe pulse STR
The comparison operation is performed only in B1, and the logical comparison operation can be performed for only one point in one test cycle.
Therefore, conventionally, a block 3B having the same structure is additionally provided, and a strobe pulse STRB2 is applied to the block 3B side, as shown in FIG.
As shown in D, strobe pulses STRB1 and STRB
Output signal D output by 2 in one test cycle
For example, it is determined whether the logic of the first half and the second half of _OUT matches the expected value.

[0010]

The conventional logical comparator employing the double speed comparator system requires the block 3B in addition to the block 3A, and has a drawback that the circuit scale becomes large.
Particularly, in the IC test apparatus, the logical comparators 3 must be prepared for the number of terminals of the IC under test 1. The IC 1 under test has a large number of terminals, some of which have several hundreds of pins. For this reason, the IC tester must be constructed so that it can test the multi-pin IC. Therefore, it is necessary to prepare a large number of logic comparators 3 having a large circuit scale, which increases costs and obstructs miniaturization. As a matter of course, as the number of parts increases, the failure rate increases and the reliability decreases.

It is an object of the present invention to use an IC test apparatus in which the circuit scale is small while adopting the double speed comparator system, so that the increase in cost can be suppressed and the number of parts is small so that the failure rate can be reduced. It is intended to provide a logical comparator.

[0012]

According to the present invention, the outputs of the H logic analog comparator and the L logic analog comparator are separately latched by two latch circuits through strobe circuits. The two latch circuits output a positive-phase latch output and a negative-phase latch output, and the positive-phase latch output and the negative-phase latch output are separately compared with the expected value signal by the gate means. It is possible to operate in the normal mode when all the outputs of each gate means are taken out by OR gate. Further, by providing switching means for separately taking out the result of comparing each positive-phase latch output and negative-phase latch output with the expected value by the gate means, it is possible to operate in the double speed comparator system.

Therefore, according to the present invention, it is possible to provide a conventional logic comparator for an IC test device which can operate in the normal mode and the double speed comparator system with the circuit scale of one block.

[0014]

1 shows the structure of a logic comparator for an IC test apparatus according to the present invention. The parts corresponding to those in Fig. 6 are given the same symbols. The structure in which the strobe circuits 5H and 5L are provided after the analog comparators 4H and 4L is the same as that described in the prior art, but in the present invention, the strobe pulse ST is separately provided to the strobe circuits 5H and 5L.
Give RB1 and STRB2. The samples sampled by these strobe pulses STRB1 and STRB2 are taken into the first and second latch circuits 6H and 6L, respectively.

Each of the first and second latch circuits 6H and 6L can be composed of a D-type flip-flop. A first gate group 9H and a second gate group 9L, which are AND gates, are respectively connected to the positive phase output terminal Q ₁ and the negative phase output terminal Q ₂ of the D-type flip-flop. Expected value pattern signals EXPH, EXPHI and EXP are applied to the other input terminals of each gate group 9H and second gate group 9L.
L, EXPLI is given.

The output of the first gate group 9H is connected to the OR gate O
R₁And take the logical OR. The output of the second gate group 9L
OR gate OR₂Logical sum circuit O
R₁And OR₂The signal output from the switching means 8 will be further discussed.
Operate in normal mode by taking it out
be able to. Also, in the switching means 8, the gate 8A
Control by closing and gate 8B by opening
Sum gate OR₁And OR ₂Failure analysis memo for the signal extracted in
7A and 7B can be stored separately,
It can be operated in a rate system.

That is, in the normal mode, as shown in FIG. 2, strobe pulses STRB1 and STRB2 are aligned at the same timing position and applied to strobe circuits 5H and 5L. In the example of FIG. 2, the strobe pulse STRB1 is placed at the position of the high impedance region Z existing between the H logic and the L logic.
And STRB2 are set. The H logic analog comparator 4H outputs H logic in the Z region.
The L logic analog comparator 4L also outputs H logic in the Z region. Therefore, both the first and second latch circuits 6H and 6L take in the H logic.

Here, the expected value pattern in the normal mode is to output L by opening gates / H and / L as shown in FIG.
When the logic is output, it is determined to be normal. Therefore, as described above, since the H logic is incorporated in the two first and second latch circuits 6H and 6L, the L logic is output to the opposite phase output terminal Q ₂ . As a result, even if the gate circuits 1H and 1L of both the first gate group 9H and the second gate group 9L are opened by the expected value pattern signal, the gate circuits / H and / L are set to the first
Also, since the L logic is given from the second latch circuits 6H and 6L, the failure analysis memory 7A is given the L logic and it is stored that it is normal.

In FIG. 2, the strobe pulse STRB1
And STRB2 are set in the first half of the Z area (area where signal D _OUT is L logic), and at this time the expected value pattern signal is set to H
In that case, the gate circuit H is opened as shown in FIG. At this time, the latch circuit 6H receives the H logic from the H logic analog comparator 4H, so that the gate circuit H outputs the H logic. In other words, in this case, the expected value and the output of the IC under test 1 do not match.

When the strobe pulses STRB1 and STRB2 are moved from the Z region to the latter half of the Z region (region where the signal D _OUT is H logic) with the expected value pattern signal kept at H,
The latch circuit 6H will read the L logic as is apparent from FIG. 2B. As a result, the gate circuit H outputs the L logic, indicating that the response output signal of the IC under test 1 matches the expected value pattern signal.

The expected value pattern X is don't care. In this case, none of the gate circuits H, / H, L and / L is opened. Therefore, strobe pulses STRB1 and ST
RB2 always outputs L logic and does not emit a defective signal.
FIG. 4 shows the operation of the double speed comparator system. In this example, the function of judging the state of the high impedance Z is omitted, and it is arranged to judge only whether the signal D _OUT is H logic or L logic. In the case of the double speed comparator system, the strobe pulses STRB1 and STRB2 are set at different timing positions. In the illustrated example, the strobe pulse STRB1
In the first half and strobe pulse STRB2 in the second half.

The switching circuit Z controls the gate 8A to be closed and the gate 8B to be open. When LH is given as the expected value pattern shown in FIG. 5 in the relationship between the signal D _OUT and the strobe pulse timing position shown in the figure, the gate circuits / H and / L are controlled to open and the first and second latch circuits 6
The logic of the opposite phase output terminal Q ₂ of H and 6L is output. At this time, the negative-phase output terminal Q ₂ is connected to the first and second latch circuits 6H and 6H.
Since both L outputs L logic, defect analysis memories 7A and 7B are given L logic and stored as normal.

The logic of the first half and the second half of the expected value pattern is LH
In other cases, for example, in the case of HL, only the gate circuit H is opened as is clear from FIG. Since the H logic punched out by the strobe pulse STRB1 is given to the gate circuit H from the positive phase output terminal Q _{1 of the} latch circuit 6H, the H logic is given to the failure analysis memory 7A, and the signal D _OUT and the expected value are output. The H logic indicating that the pattern does not match is stored. When the expected value pattern is other than LH, H logic is output from either one of the OR gates OR _{1 and} OR ₂ and it is determined that they do not match.

[0024]

As described above, according to the present invention, it is possible to construct a logical comparator that operates in a double speed comparator system with a circuit scale about half that of the conventional one. As a result IC
The circuit scale of the test apparatus can be reduced and the cost can be expected to be reduced.

[Brief description of drawings]

FIG. 1 is a connection diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the logical comparator according to the present invention in the normal mode.

FIG. 3 is a diagram for explaining a relationship between an expected value pattern and a gate means opening / closing control signal in a normal mode.

FIG. 4 is a waveform diagram for explaining the operation of the double speed comparator system of the logical comparator according to the present invention.

FIG. 5 is a diagram for explaining a relationship between an expected value pattern and a gate means opening / closing control signal in the case of a double speed comparator system.

FIG. 6 is a connection diagram for explaining a conventional technique.

FIG. 7 is a waveform diagram for explaining the operation of the conventional technique.

FIG. 8 is a diagram for explaining a relationship between an expected value pattern and an expected value pattern signal in the conventional technique.

[Explanation of symbols]

 1 IC under test 2 Pattern generator 3 Logical comparator 4H, 4L Analog comparator 5H, 5L Strobe circuit 6H First latch circuit 6L Second latch circuit 7A, 7B Failure analysis memory 8 Switching means 9H First gate group 9L Second gate group

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[Procedure amendment]

[Submission date] December 16, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

Here, the expected value pattern in the normal mode is to output L by opening gates / H and / L as shown in FIG.
When the logic is output, it is determined to be normal. Therefore, as described above, since the H logic is incorporated in the two first and second latch circuits 6H and 6L, the L logic is output to the opposite phase output terminal Q ₂ . As a result a first gate group 9H gate circuit / H of both the second gate group 9 L / L and a gate circuit / H be opened by the expected value pattern signal / L is first
Also, since the L logic is given from the second latch circuits 6H and 6L, the failure analysis memory 7A is given the L logic and it is stored that it is normal.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

The switching means 8 controls the gate 8A to be closed and the gate 8B to be open. When LH is given as the expected value pattern shown in FIG. 5 in the relationship between the signal D _OUT and the strobe pulse timing position of FIG. 4 , the gate circuits / H and / L are controlled to open and the first and second latch circuits 6
The logic of the opposite phase output terminal Q ₂ of H and 6L is output. At this time, the negative-phase output terminal Q ₂ is connected to the first and second latch circuits 6H and 6H.
Since both L outputs L logic, defect analysis memories 7A and 7B are given L logic and stored as normal.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

The logic of the first half and the second half of the expected value pattern is LH
In other cases, for example, in the case of HX , only the gate circuit H is opened as is apparent from FIG. Since the H logic punched out by the strobe pulse STRB1 is given to the gate circuit H from the positive phase output terminal Q _{1 of the} latch circuit 6H, the H logic is given to the failure analysis memory 7A, and the signal D _OUT and the expected value are output. The H logic indicating that the pattern does not match is stored. When the expected value pattern is other than LH, H logic is output from either one of the OR gates OR _{1 and} OR ₂ and it is determined that they do not match.

Claims (1)

[Claims] 1. A. An H logic analog comparator and an L logic analog comparator that determine whether the H logic level and the L logic level of the logic signal output from the IC under test have a prescribed voltage value; A first latch circuit for latching the comparison results output from the H logic analog comparator and the L logic analog comparator at a desired timing, and outputting the comparison result of the H logic level and the reverse logic of the comparison result, and L A second latch circuit for outputting a comparison result of logic levels and a logic opposite to the comparison result; A first gate group in which a latch output of the first latch circuit is applied to one input terminal and an expected value corresponding to H logic is applied to the other input terminal; A second gate group in which the latch output of the second latch circuit is applied to one input terminal and an expected value corresponding to the L logic is applied to the other input terminal; A state in which all the gate outputs of the first gate group and the second gate group are logically ORed to output the logical comparison result in the normal mode, and a double speed in which the outputs of the first gate group and the second gate group are separately output A switching circuit that switches to a state of outputting a mode logical comparison result, and a logical comparator for an IC test apparatus.