JPH0269687A - Testing device for logic integrated circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of a shortage in capacity in a defect analyzing memory by providing an address detecting means, defective pattern detecting means, and write inhibit means. CONSTITUTION:At an address detecting means 60, a D type FF latches address signals given to a pattern memory 12 at every test cycle and an AND gate 62 performs coincidence detection by comparing the latched address signals in the preceding and succeeding test cycles. In a defective pattern detecting means 70, a D type FF 71 and AND gate 72 similarly detect the coincidence of defect occurring patterns in the preceding and succeeding cycles when an input is made from a logic comparison circuit 40. In a write inhibit means 80, outputs the detecting means 60 and 70 and the circuit 40 are supplied through an OR gate 53 and writing is selectively inhibited. When such constitution is used, data writing is inhibited when address signals supplied to the memory 12 are the same and, at the same time, defect occurring patterns are also the same in the preceding and succeeding cycles and, when a defect occurs due to the repeated impression of the same test pattern, writing in a defect analyzing memory 50 is performed one time only. Therefore, a shortage in capacity hardly occurs in the memory 50.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a logic integrated circuit testing device for testing logic integrated circuit elements such as integrated circuit memories.

"Prior Art" Figure 3 shows an overview of a conventional logic integrated circuit testing device. In the figure, numeral 10 indicates a pattern generator. This pattern generator 10 is a sequence memo I711,! :, pattern memory 12, sequence memory pointer 13, pattern memory pointer 14, and repetition counter 15
This includes a zero detection device 16, etc., which detects when the count value of the counter 15 becomes zero.

All pattern signals to be used are written in the pattern memory 12, and these pattern signals are accessed by a pattern memory pointer 14 to read out the pattern signals. The sequence memory 11 stores the pattern generation order. In other words, the same pattern is stored in the pattern memory 12 without duplication. When the same pattern is repeatedly output, the same address is repeatedly output from the sequence memory 11, and the pattern written at this address is repeatedly read out, thus generating the same address a desired number of times.

Further, a certain portion of the pattern memory is repeatedly read out by the sequence memory and outputted as a test pattern signal. In this way, the pattern signals actually written to the pattern memory are -
The pattern is compressed to several tenths of the original size and stored in the pattern memory.

The test pattern signal output from the pattern generator 10 is applied to the device under test 30 through the waveform shaping circuit 20.

The response output of the device under test 30 is compared with the expected value pattern output from the pattern generator 10 in the logic comparison circuit 40, and if a mismatch is detected, the address where the mismatch occurred and the device under test 30 are stored in the failure analysis memory 50. The defect occurrence pattern is memorized.

The failure analysis memory 50 includes a memory main body 51, a memory pointer 52 that provides an address signal to the memory main body 51,
Each time a defect occurs, the memory pointer 52 moves the address by +1, and the OR gate 53 gives a write command signal to the memory main body 51, and detects the defect in order from the first address of the memory main body 51. Store generated data.

"Problem to be Solved by the Invention" The pattern generator 10 repeatedly accesses the pattern memory 12 and outputs a test pattern signal. In other words,
The test pattern is compressed and stored in the pattern memory 12. Therefore, the capacity of the pattern memory 12 only needs to be sufficient for the number of types of pattern data.

On the other hand, since the capacity of the memory main body 51 of the failure analysis memory 50 must be sufficient for the number of failure occurrences, a large capacity is required corresponding to the number of failure occurrences of the device under test.

An object of the present invention is to provide a logic circuit testing device that can reduce the memory capacity of the failure analysis memory 5o.

"Means for Solving the Problem" The present invention provides an address for detecting whether or not address signals given to a pattern memory match in a previous test cycle and a next test cycle in a logic circuit testing device equipped with a failure analysis memory. a detecting means, a defective pattern detecting means for detecting whether the defective pattern of the device under test matches between the previous test cycle and the next test cycle, and a detecting means for detecting whether the defective pattern of the device under test matches between the address detecting means and the defective pattern detecting means. The structure includes a write inhibiting means for inhibiting writing to the failure analysis memory when detected.

"Function" According to the configuration of the present invention, the same address in the pattern memory is accessed successively, and therefore the same test pattern is read out and applied to the device under test, and a defect is detected at that time. If the patterns match in the previous test cycle and the next test cycle, writing of defective data is prohibited.

Therefore, if the same pattern is successively read from the same address in the pattern memory, and the device under test generates the same defect pattern, the defect data is written to the defect analysis memory only once at the beginning, and then the same pattern is read from the same address in the pattern memory. Writing of the same defective data is prohibited.

As a result, the number of defective data written to the defect analysis memory can be reduced, and the memory capacity can be reduced.

Note that if the same test pattern is given continuously and the device under test fails at that time, the failure data after the first time is meaningless data, and even if it is removed, there will be no problem in failure analysis. .

In other words, when the same test pattern is continuously applied, the internal state of the device under test does not change.
This is because if a defect occurs in the first test, it can be assumed that the defect will continue to occur.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In Figure 1, 1
0 is a pattern generator, 2o is a waveform shaping circuit, 30 is an element under test, 40 is a logic comparison circuit, and 50 is a failure analysis memory, which is the same as the conventional device explained in FIG.

In this invention, the address detection means 60 detects whether the address signal given to the pattern memory 12 is the same in the previous test cycle and the next test cycle, and the address detection means 60 detects whether the failure occurrence pattern is the same in the previous test cycle and the next test cycle. A defective pattern detecting means 70 detecting whether or not the address detecting means 60 and the defective pattern detecting means match, and a write inhibiting means 80 which prohibits writing to the defect analysis memory 50 when both the address detecting means 60 and the defective pattern detecting means detect a match are provided.

The address detection means 60 can be composed of, for example, a group of D-type flip-flops 61 and, for example, a group of AND gates 62 for detecting coincidence. In other words, pattern memory 1
Each pit data of the address signal given to D-type flip-flop group 61 is input to the data input terminal of each D-type flip-flop, and the address signal is latched every test cycle. This latch output is applied to one input terminal of each AND gate of the matching detection AND gate group 62. An address signal to be applied to the pattern memory 12 is directly supplied to the other input terminal of the AND gate.

With this configuration, the AND gate group 62 uses the address signal given to the pattern memory 12 in the previous test cycle and the pattern memory 1 in the next test cycle.
It is possible to compare the address signals given to 2, and if a match is detected, it outputs a logic "1".

The defective pattern detection means 70 also includes the D-type flip-flop group 7.
1 and an AND gate group 72. The defective pattern data output from the logic comparison circuit 40 is input to the data input terminal of each D-type flip-flop constituting the D-type flip-flop group 71, and the defective pattern data is latched for each test cycle. This latch output is applied to one input terminal of each AND gate of the AND gate group 72. The logic comparison output of the logic comparison circuit 40 is directly input to the other input terminal of the AND gate.

With this configuration, the AND gate group 72 compares the failure occurrence pattern of the previous test cycle with the failure occurrence pattern of the next test cycle, and outputs a logic "1" when a match is detected.

The write inhibiting means 80 can be composed of a Nant gate 81 and an AND gate 82, for example. The detection output of the address detection means 60 and the detection output of the defective pattern detection means 70 are applied to the input terminal of the Nant gate 810.

Therefore, the Nant gate 81 normally outputs a logic "1", but when the address detection means 60 and the defective pattern detection means 70 each detect a match, it outputs a logic "0" and controls the AND gate 82 to close. . and gate 82
A defect occurrence detection signal is applied to the other input terminal of the circuit through an OR gate 53.

Therefore, while the Nant gate 81 is outputting logic "1", the failure detection signal output from the OR gate 53 gives a write command signal to the memory body 51 of the failure analysis memory 50 through the AND gate 82, but the address detection Means 60
When the and defective pattern detection means 70 both detect a match between the address in the pattern memory 12 of the previous test cycle and the address of the next test cycle and a match of the defective pattern, the AND gate 82 is closed and writing is prohibited.

FIG. 2 shows a modified embodiment of the invention. This example shows an example in which a capture mode switching circuit 90 is provided.

In other words, the AND gate 82 constituting the write inhibit means 80
A gate 91 is arranged in parallel with the AND gates 82 and 91, and the AND gates 82 and 91 are controlled to open and close in a complementary manner by a mode switching signal inputted to an input terminal 93. In other words, when a logic "1" is input as the mode switching signal, the AND gate 82 is opened and the gate 91 is opened.
is controlled to close.

In this state, all the failure detection signals inputted from the OR gate 53 through the AND gate 82 are sent to the failure analysis memory main body 5.
1 write signal terminal.

Furthermore, when the mode switching signal rOJ logic is input, the AND gate 82 is controlled to close and the gate 91 is controlled to open. At this time, when the output of the Nante gate 81 is "month logic", defective data is written, and when the output of the Nante gate 81 becomes "0" logic, writing is prohibited.

That is, when the attos of the previous test cycle and the next test cycle match the defective pattern, it operates in a mode in which writing is prohibited.

"Effects of the Invention" As explained above, according to the present invention, the address signal given to the pattern memory 12 is the same in the previous test cycle and the next test cycle, and the failure occurrence pattern is different in the previous test cycle and the next test cycle. If they are the same, writing of defective data is prohibited, so if the same test pattern is repeatedly applied and a defect occurs, only the first defective data is written into the defect analysis memory 50.

Therefore, since unnecessary data is not written to the failure analysis memory 50, the capacity of the failure analysis memory 50 can be saved, making it difficult to run out of capacity.

Furthermore, the capacity of the failure analysis memory 50 can be reduced, and cost reduction can also be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a modified embodiment of the invention, and FIG. 3 is a block diagram for explaining a conventional technique. 10: Pattern generator, 12: Pattern memory, 20
: Waveform shaping circuit, 30: Device under test, 40: Logic comparison circuit, 50: Failure analysis memory, 60 Near address detection means,
70. Defective pattern detection means, 80; write prohibition means.

Claims (1)

[Claims] (1) A. Read the test pattern signal from the pattern memory and apply it to the device under test, compare the response output signal of the device under test with the expected value pattern signal, and if a mismatch is detected, write the failure occurrence address in the failure analysis memory. B. Address detection for detecting whether the read address given to the pattern memory matches the previous test cycle and the next test cycle. means; C. defective pattern detection means for detecting whether or not the defect occurrence patterns match in the previous test cycle and the next test cycle; and D. defective analysis when the address detection means and the defective pattern detection means detect a match. A logic integrated circuit testing device comprising: means for inhibiting writing to memory;