JPS5984571A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form the high-speed COMS of low threshold value by a method wherein a gate oxide film is thinly formed and ion implantation of boron is performed twice. CONSTITUTION:An N type well 2 and a field SiO2 film 3 for element isolation are formed on one main surface side of a P type silicon substrate 1. After a mask 4 and an underlayer of SiO2 film 5 have been removed by performing an etching, whole surface is oxidized by heat, and a gate oxide film 6 of 750Angstrom and another relatively thick gate oxide film 6 are grown on the whole element region. Then, p type impurity such as an ion beam of boron is irradiated, boron is ion-implanted through the gate oxide film 6, and a boron-implanted region 8 is formed directly below the above boron-implanted part. Then, an etching is performed on an SiO2 using polysilicon 9 and 10 and a field SiO2 film 3, the gate oxide film 6 located on element regions C and D is completely removed, and the whole surface is oxidized by heat. As a result, a gate oxide film 11 of 500Angstrom in thickness and another relatively thick gate oxide film 11 are grown on the element regions C and D. P type impurities such as boron, for example, are ion-implanted on the substrate side through a thin SiO2 film 11 using an ion beam 13. As a result, boron 14 is double-implanted superposing on the boron implanted region 8 located on the element regions C and D.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device T (hereinafter referred to as TE C).
and its manufacturing method.

In recent years, OM OB (Complementary M
etalOXide Sem1aonductor
) type](fPROM-(Electrically
Programmable Read Only Mθm
ory) is being developed. CMOB of this building
As a type EPROM, the gate electrode t of each M08FEfT
The first layer is made of polysilicon, and the gate oxide film has two types: 5ooX and 1000A.The former is proposed for use in high-speed FIIIT, and the latter is used in high-voltage FETs. It's awned. However, in this structure, when converting to 0MO8, the gate oxide film thickness is 1ooo
A mask for the first ion implantation that controls the FIT threshold voltage of X to be low? n must be added, which increases the number of manufacturing steps. On the other hand, the gate voltage mk
The gate oxide film fur of the FIT formed with the first polysilicon layer is approximately 800"A, and the gate oxide film fur of the gate electrode is approximately 1200"A. In this case, in order to lower the threshold voltage of the FET with a thick gate oxide film, it is necessary to add a mask, which makes manufacturing difficult. Moreover, increasing the voltage resistance itself is not easy.

Therefore, what is the manufacturing process for the purpose of the tree brother? A process that is simple and at the same time allows easy control of the threshold voltage and its manufacturing method? It is about providing.

Hereinafter, a detailed description will be given of the implementation drawings that are applicable to the 10MO8 type BPROM of the present invention.

The manufacturing process of the EPROM 1 according to this example will be explained.

1. As shown in FIG. 1, on the whole surface side of the P-type silicon substrate 1,
An N-type well 2 and three field 5102 films for element isolation are formed in a predetermined pattern according to a known conductor manufacturing technique. 4 in the figure is an oxidation-resistant mask (silicon nitride) used when forming the 5102 film under this field by selective oxidation technology. The field 5102 film 3 increases the pressure resistance of MI.
S FET resistor area A, memory element area B, 0
Element regions C and D for the N-channel M5FET and the P-channel M5FET constituting M08i are separated, respectively.

Next, as shown in Figure 2, mask 4 and base 8102i5
After removal by etching, all I]iIt is heated and a relatively thick gate oxide film 6 of 87.5 OA is grown in the entire lattice region.

Next, as shown in Fig. 3, an ion beam of 7i75KeV of P-type impurity, in other words boron, is applied to the entire surface, energy 2X1.
Irradiation is performed with a dose of 0"/c4, and boron t ions are implanted through the gate oxide film 6 trays to form a boron implanted region 8 directly under it. By this boron implantation, the M-type 5FET using the gate oxide film 6 trays is The threshold voltage is set to be low, about 0.5V.

Next, as shown in Figure 4, Bonsan iVc was formed using chemical vapor deposition technology.
Grown impurity-doped (low resistance) polysilicon? After patterning by etching, a gate electrode t! made of the first polysilicon layer is placed on the gate oxide film 6 in the device regions A and B.
9. Floating gates JmlOi each have a shaped bottom.

Next, as shown in FIG. 5, polysilicon 9 and 10 and field 810g group 3 are etched seven times with Sin as a mask, and gate oxide film 6 in device regions 0 and D is completely removed.

As shown in Figure 6, by thermally oxidizing the entire surface,
A relatively thin cate oxide film 11i with a VC film thickness of 500A is grown in the system columen region C and D. In the element region A, a Si film 11 with a thickness of 5(1) is formed on both sides of the gate oxide film 6.
At the same time, a 5in2 film 12 having a thickness of 100 OA is grown on the surface of each polysilicon layer 9 and 11.

Next, as shown in FIG.
Irradiate with a dose of 10"/ctA, and
Boron silicon ions are implanted into the substrate side through to2[11r. As a result, boron 14 is implanted into the element regions C and D17C overlapping the boron implanted region 8 described above (double implantation), increasing the boron concentration. With this boron double implant, M using gate oxidation milk
Step 5: The threshold voltage of PET is controlled to be as low as about 0.5V. To obtain this low threshold value, 51
Is there a phenomenon where the implanted boron is eaten away by the 02 film 11? Must be considered, 67) K, Eli0211rA11 lower 1c
i J: v Boron is implanted with high tension in the above two straight implants”ft
In order to protect you, I will fully compensate you for your loss.
It is possible to maintain the boron concentration at a certain level.

Next, as shown in FIG. 8, the 277th layer of impurity-doped low-resistance polysilicon is grown on the entire surface using chemical vapor deposition and 44J deposition techniques, and is patterned by etching to form device regions B, C! , D is the second layer polysilicon control gate ti15.0 MO8 each case) 'i pole 16.17
Strive to form. In FIG. 8, each of these gate electrodes 2
The underlayer 5i021FJ 11.12t is etched as a mask, and the floating gate 10 and 8102 film 6 under the control gate ma+5 are etched (melon cut). The boron double implantation region (8+14) shown in FIG. 7 is indicated by a cross mark 18 in the m8 diagram.

Next, as shown in FIG. 9, thermal oxidation is performed on the entire surface of the silicon and polysilicon to form s10xl1M19.20 crystals.

As shown in FIG.
Incorporate a type-unwired substance (kerie is phosphorus) and a P-type axial substance (relie is boron) into each other. This allows N to be used as a source or drain region in the steel regions A, B, and O.
Mold diffusion regions 21 and 22.23 and 24.25 and 2
6r is formed, and P+ type diffusion regions 27 and 28 are formed as source or drain regions in the element region.

Next, as shown in Fig. 1Al1, a phosphosilicate glass film 29 is deposited on the entire surface using chemical deposition technology. Aluminum wires 30, 31. are processed by photo etching between each contact hole, and aluminum wires 30.31. 32r is formed.

Through the above process, the following four types of MISFET'
(Z has (II! MO8 type EP'ROM is created.

MO8I near 50A, has a relatively thick gate oxide film 6r, and has a channel part doped with low concentration of boron δn, high breakdown voltage, low threshold voltage (o, 5V) (7) N channel M
ISFET MO8mnear 5QA and specific gate oxide film r,
Floating gate 10 and control gate 15
A low-threshold memory device with a two-layer polysilicon gate structure.

MOS2: 500A and relatively thin gate oxide film 11
The channel part is heavily doped with boron, and M
OS3 and high speed 0M0S configuration N Chao Lu MIS
FIiliT0MO83: A P-channel MISF with a relatively thin gate oxide film 11'z of 500A, a channel portion heavily doped with boron, fL, a high-speed 0M0Bf configuration with MOS2, and a low threshold voltage]flT.

As mentioned above, according to the non-implemented version, the first layer is a polysilicon gate, has a comparatively buried A gate oxide layer 2, and the channel portion is doped with a low concentration of boron. This shows a low threshold voltage 7 and also shows a withstand voltage. This time, the gate oxide film was made selectively thinner, and at the same time boron ion implantation was performed once. ability, 2
A low threshold, high-speed CMOB' is fabricated using a MOS3 layered polysilicon gate with a comparatively thin gate structure and a high concentration of boron doped in the channel part.
f can be created. This is because the gate oxide film is of course selectively expanded and the boron ion implantation is performed twice. 'In this way, MOS manufacturing for each building can be easily carried out without adding masks, and
The threshold f1u voltage can also be easily controlled by selective implantation of boron, and valley elements can be formed with high density.

In addition, in the upper 6 ha, u, 11!41 of the gate oxide film of @M08 is not limited to the above,
Various changes 6zetej: Yes. Also, the guide 1 of each of the above-mentioned beef body areas! It may change to a type R type. Furthermore, the present invention can be applied not only to the gFROM but also to a general 1/i: technology consisting of an MI EIFET having various characteristics such as cylinder dynamic pressure, low threshold voltage, and high speed.

[Brief explanation of drawings]

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 1θ, and Figure 11 are according to the implementation sequence of the present invention. EEPROM 69 Manufacturing Method 11 The cross-sectional views shown in Figure 1 are shown. In addition, in the reference numerals shown in the drawings, 6...relatively thick gate oxide film, 7 and 13... boron ion beam, 8.14 and 18... boron implantation region, 9 and 1
0...First layer polysilicon gate, 11...Relatively thin gate oxide film, 15.16 and 17...Second layer polysilicon gate, MoB2...High breakdown voltage, low threshold voltage N-channel M5FET, MO8m...2-layer polysilicon structure memory resistor, MoB2...0MO8
N channel M engineering 5PET, MO83...0MO8
P-channel M-type 5FET with low h-value voltage for use.

Claims (1)

[Claims] l. A first M-type S FET having a gate electrode made of a first polysilicon layer and a 20-M type 5FET having a gate electrode made of a second polysilicon layer are common semiconductors. [1IiT]1IiT has a relatively thick gate insulating film, and the second M
Making the FfiT a relatively thin gate insulating film t'
Semiconductor integrated circuit device with % characteristics. 2. The channel portion of the first M-type 8FET is doped with impurities at a relatively low concentration, and the channel portion of the 20M-type 5FET is doped with a relatively high concentration of impurities. A semiconductor integrated circuit device according to claim 1gl which is a threat. 3. The step of separating the whole surface of the semiconductor substrate into each element region, and the relatively thick insulation of the entire element chain. , a step of doping impurity into the entire confectionery region through this conductive gland, and a step of forming a gate electrode made of the first polysilicon layer on the relatively thick gate insulating film of the first element region. forming a relatively thin gate insulating film thereon after removing a relatively thick gate insulating film on the second element region; and a step of forming a gate electrode made of a second polysilicon layer on the relatively thick gate insulating film in the second element region.
- A method for manufacturing a semiconductor integrated circuit device having nine characteristics.