JPS598431A - Buffer circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit of high speed and low power consumption by combining bipolar and CMOS transistors(TRs) to constitute a noninverting type composite buffer circuit. CONSTITUTION:N-channel MOSTRs QM1, QM2, P-channel MOSTRs QM2, QM3 and NPN bipolar TRs QB1, QB2 are provided. When both inputs and outputs are at high potential, the TR sQM2, QM3 are turned off and the TRs QM1, QM2 are turned on. Thus, the TRQB2 turns off and a load of an output OUT is capacitive, then the TRQM1 turns off. When the output OUT goes to a low potential, since no base current is applied from the output OUT to the TRQB2, the TRQB2 turns off and no current flows to the TRQB1. As far as the input/ output remains at high or low potentials, only the leakage current flows and the power consumption is almost zero.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low power consumption, high speed buffer circuit that combines OMO8 and bipolar.

Conventionally, attempts have been made to combine 0MO8, bipolar, and transistors to construct a buffer circuit that combines the low power consumption of 0MO8 and the high speed of bipolar. FIG. 1 shows an inverter as an example of a buffer circuit. Although circuits of this type with different configurations are known, inverters are the most common.

By the way, this type of buffer circuit is, for example, CMO8.
You can configure high-speed, low-power consumption logic gates with high drive capability added to logic gate circuits, or configure light-loaded circuit parts in the LSI with only 0MO8, and use these buffer circuits only in heavily-loaded circuits. In addition, the overall design is highly integrated and fast.

It is suitable for configuring LSIs with low power consumption.

For example, Fig. 2 is an example of such a circuit configuration, in which a bipolar CMOS MOS gate (for example, the circuit in Fig. 1) is added to a CMOS gate (for example, a two-man NAND gate is shown). be. In this circuit configuration, if the load CL - the sum of each line capacitance and the input capacitance of the next stage gate to be driven is small (for example, 0.1
pF), generally 0MO8 alone is sufficiently fast, but if a buffer circuit is added, the load drive response will become slower. However, the CL is large (
For example, when it is about 1 pF], the 0M08 circuit has poor driving ability and becomes very slow, and the delay time becomes several times (for example, three times or more) that of a light load. In this case, by adding all the bipolar and 0MO8 composite buffer circuits, the delay time of the entire circuit including the additional circuit part can be shortened (for example, to about twice that of the 0M08 circuit at light load). Needless to say, if the speed is large, the effect of increasing speed by adding a buffer circuit will be even greater.

By the way, as shown in Fig. 2, the CMo5 logic gate usually has NAND and NOR as its basic circuits, and when an inverter circuit is combined with these gates, AN
D, OR, etc., are logics that do not include negation. Figure 2 shows the IflIt, NAND configured by 0MO8
A composite buffer circuit 22 of bipolar and 0MO8 as shown in FIG. 1 is connected to the output of the gate 21, and the AND
A circuit is obtained.

However, it is difficult to use many combinations of such logic circuits for purchasing or to assemble all the random logics as basic circuits. Therefore, a non-inverter type buffer circuit with high speed and low power consumption is desired as these buffer circuits.

Therefore, the object of the present invention is to combine bipolar and CMO8'(
An object of the present invention is to provide a high-speed, low-power non-inverter type composite buffer circuit that combines the following elements.

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 3 is a circuit diagram of one embodiment of the present invention. This circuit consists of n-channel MOS transistors QMI and Q, M4, p
Channel MOS transistor QI'142° and 9M3
．． npn bipolar transistor QB1. Consists of QB2. This circuit operates as follows. First, consider a state where both input and output are at high levels. At this time, QM2,9
M3 is off, and QM1 and QM4 are on. Therefore QB2 is off. Furthermore, since the load on the output OUT is capacitive, QBl is also almost off in a steady state. Under this condition, if the output OUT becomes low level for some reason (for example, leakage current from the load connected to the output), the base current is supplied to QBI via QM1e, and the output OUT is kept at a high level. It will be done. As long as OUT is at a high level, Q and Bl are almost off, and therefore almost no current flows in a steady state. Next, consider a state in which the input IN switches from high level to low level. Immediately after switching, the output OUT is still at a high level. Stay in this state Q
, M2.9M3 are on, QMI and QM4 are off.

The charge accumulated at the base of QBI is extracted by QM2 and QBI is turned off. On the other hand, QB2 has QM3'
The base current is supplied through the circuit, so it turns on. Therefore, a current hFK times its base current flows through the collector of %QB2, so that the output OUT rapidly goes to a low level. When the output OUT becomes low level, the Q
The base current to B2 is no longer supplied, and QB2 is turned off. In this state, QM2 is also on, but
Since the base charge of QBl has already been extracted, no current flows. Even if both the input and output are in a steady state at a low level, no current flows except for leakage current. Next, consider the case where the input switches from low level to high level. Immediately after the input switches, the output is still at a low level.

Therefore, QMl is on, QM2 is off, QM3 is off,
QM4 is turned on, and base current is supplied to QBI via QMl, while the base charge of QB2 is extracted by Q and M4. Therefore, QB2 turns off quickly,
The output OUT goes to a high level due to QBI. Output O
When UT becomes completely high level, the base current through QM 1 k stops flowing, and the state returns to the first described state.

As explained above, in the circuit shown in Figure 3, as long as the input/output remains at a high or low level, only the IJ current flows and the power consumption is almost zero; It just flows with time. Therefore, overall power consumption is small and can be considered to be the same as 0MO8. On the other hand, when viewed from the output, the gm of the MO8 transistor appears to be multiplied by a hole (that is, about two orders of magnitude), so even if the output load capacitance is large, the speed can be sufficiently increased. Note that in order to increase speed, it is desirable that λ in QMI (or 9M3 in some cases) be a depletion type.

FIG. 4 shows another embodiment of the invention. The difference between this embodiment and the embodiment in FIG. 3 is that the drain of QM2, which was connected to the output OUT in FIG. 3, is idQ and B2 in FIG.
The only point connected to the base of the In the circuit shown in Figure 4, when the input switches from low level to high level,
The charge extracted from the base of QB1 is supplied to QB2 as a base current, and therefore the time for QB2 to turn on is shortened by that amount. For other operations, please refer to the 4th section.
The figure and Figure 3 are the same.

By the way, in the embodiment shown in FIG. 3.4, it is desirable that the QMI be of the depletion type in order to increase the speed. If it is not depletion type, even if the input is high level,
This is because it is not possible to supply enough pace current to raise the output to a sufficiently high level. Therefore, it is difficult to maintain the output at a sufficiently high level and to increase the speed. On the other hand, Section 3.4
Since the other MOS transistor td in the figure is generally an enhancement type (of course, it is possible to use a depletion type if necessary), the third MOS transistor td is
．． In the case of the embodiment shown in FIG. 4, it is necessary to use both enhancement type and depletion type MOS transistors in order to improve the performance, which makes the process somewhat complicated. □FIG. 5 shows another embodiment of the present invention, in which the above-mentioned drawbacks are eliminated.

The circuit in Figure 5 is a p-channel MO8) transistor QNII.
, QM12 and 9M13, an n-channel MOS transistor QM14, and npn bipolar transistors QBII and QBl2.

The operation of this circuit will be briefly explained. First, input.

Consider a state in which both outputs are at a high level. At this time, QMI
I, Q, M12, 9M13 are off, and only QMI4 is on. Therefore, QBII.

Both QBl2 are off. Under this condition, the output OU
If T becomes low level due to some reason (for example, leakage current of the load connected to the output), QMI2 turns on, base current is supplied to QBII from the input terminal IN, and the output OUT is kept at a high level. It will be done. As long as OUT is at a high level, vQB11 is off, and therefore almost no current flows in the steady state. Next, consider a state in which the input IN switches from high level to low level. Immediately after switching, the output OUT is still at a high level. In this state, QMI
1, QMI 3 is on, Q, Ml 2. QM
14 is off. The charge accumulated in the base of QBII is extracted by QMII and QBII is turned off.
On the other hand, QBl2 is turned on because the base current is supplied through all of QM13. Therefore, a current hue times the base current flows through the collector of QB12, so that the output OUT rapidly goes to a low level. When the output OUT becomes a low level, the base current is no longer supplied from the output OUT to Q and B12, and QB12 is turned off. In this state, QMI 1 and QMI 2 are also on, but
Since the base charge of QBII has already been extracted, no current flows. In other words, even if both input and output are in a steady state with low levels, no current flows except for leakage current. next,
Consider the case where the input changes from low level to high level. Immediately after the input switches, the output is still at a low level. Therefore, QMI1 is off, QMI2 is on, 9M13 is off, QMI4 is on, and QMI2
While the base current is supplied to QBII through
The base charge of 2 is extracted by QMI4. Therefore, QBl2 turns off quickly and the output OUT becomes QBI
I move towards a higher level. When the output OUT becomes completely high level, QMI2 is turned off and returns to the state described at the beginning.

As explained above, even in the circuit shown in Figure 5, as long as the input and output remain at high or low levels, only leakage current flows and power consumption is almost zero, and power only flows during switching transitions. be. Therefore, the power consumption as a whole can be considered to be the same as 0MO8, similar to the embodiment shown in Fig. 3.4, and it can be considered that the gm of the CMOS gate is effectively multiplied by hFW. This is the same as in the embodiment shown in Figure 4.

FIG. 6 shows another embodiment of the invention. The difference between this embodiment and the embodiment shown in FIG. 5 is that the drain of QMII, which was connected to the output OUT in FIG. 5, is QB12 in FIG.
The only point is that it is connected to 0 pace. In the circuit shown in Figure 6, when the input switches from low level to high level,
The charge extracted from the base of QBll is supplied to QBl2 as a base current, and therefore QBl2
turns on faster. Regarding other operations, FIG. 6 and FIG. 5 are the same. In the circuit shown in FIG. 5.6, the base current of QBl must be supplied by the front-stage circuit, so the front-stage circuit requires a somewhat larger driving capability than in the case of FIG. 3.4.

FIG. 7 is a circuit diagram of yet another embodiment of the present invention. In this embodiment, QMI, QM2, or QMII, QMI2 in Figures 3, 4, or 5.6 are removed, and the bases of QB1''! and QBII are directly connected to the input terminals. In this case, QBl is in the on state except when the input is at an extremely low level, so it has the disadvantage that all the noise on the input appears on the output side.However, if the noise margin is sufficient This circuit can be used if this is secured.The operation of this circuit is clear from the explanation of the operation shown in FIGS. 3 to 6, so the explanation will be omitted.

A usage example of the circuit described above will be briefly described.

Fig. 8 shows an example in which a three-man-powered CM08 NAND gate A is combined with embodiment B of Fig. 6, and the entire three-man-powered NAND gate is
It constitutes an AND circuit. The delay time of this circuit was compared with the delay time of an ECL circuit, which is currently the most standard high-speed bipolar logic circuit, assuming that all processes are at the same level. As a result, it was found that for a load capacitance i1 pF, the delay time of the circuit shown in FIG. 8 is almost the same as that of ECL. Also, the delay time in both parts A and B is almost equal E
Each delay time was approximately half of that of CL.

Further, the power consumption at this time is extremely small, about 1/20 of ECL, assuming a switching cycle time of 50 ns. In other words, if the circuit shown in FIG. 8 is used, it is possible to construct an LSIt which is about 20 times more highly integrated than the ECL in terms of power consumption, and the total delay time of the unit gate can be basically the same as that of the ECL.

Other approaches to using the buffers of the present invention are also possible. Figure 9 shows the concept, and A
is a logic circuit network that combines multiple CMOS gates.
, B, B', etc. are buffer circuits of the present invention. In this case, the CMOS gate circuit network is grouped within a range that is considered to have a sufficiently light load on each gate, and each CMOS gate is
The MOS gate operates under light load conditions (that is, the load gate is placed nearby and the wiring capacitance is small). On the other hand, when the load is heavy, such as when all inputs are applied to gates located far away within the chip, or when there is a large fan-out, the signal is transmitted via the buffer circuit B or the like. Therefore, the increase in delay time due to load is small. A fairly simple case of such usage is shown in FIG. In this case, for example, the signal input from I2 is applied to the CMOS gates AI, A3 . A4? After that, it is buffered at B2 and goes out to output 02. In this case, A1.
A3. Since the load on A4 is light, each operates with a delay time of about 172 ECLs. Also, even if the load on output 02 is heavy,
Since this portion also operates with a delay time of approximately 1/2 of ECL, the three stages of gates operate with a delay time twice as long as ECL as a whole. This reduction in delay time becomes greater as the number of cascaded gates in the CMOS gate network increases.

However, since the load generally increases as the number of gates increases, there is an optimum point somewhere. This optimum point is determined by the process technology used, the level of circuit design technology, etc. ! In addition, in the case of the method of use shown in Fig. 9, the number of bipolar CMOS chips used is reduced, so the increase in chip area due to the use of buffers can be kept to a minimum. As a bipolar CMO8 composite buffer for the network, a combination of both non-inverter type and inverter type will be used. May be used in combination with a buffer.

In addition, in the present invention, ■τuk of the MOS) transistor
By changing the speed, power consumption, output level, etc., it is possible to change the speed, power consumption, output level, etc., but it goes without saying that this is a matter of design and is within the scope of the present invention.

Also, replace npn) transistor 1pnp) transistor with p-channel MO8I-ransistor and n-channel M
It goes without saying that the same operation can be achieved even if the OS transistors are replaced.

As described above, according to the present invention, a non-inverter type high speed, low power consumption composite buffer circuit can be obtained, and since a desired logic circuit with high driving ability can be easily constructed, its industrial value is great.

[Brief explanation of the drawing]

Fig. 1 shows a conventional inverter type buffer circuit, Fig. 2 shows how the buffer circuit is used, Fig. 3 shows one embodiment of the present invention, and Fig. 4 shows another embodiment of the present invention. Examples, FIG. 5 shows yet another embodiment of the invention, FIG. 6 shows yet another embodiment of the invention, FIG. 7 shows yet another embodiment of the invention, and FIG. 8 shows another embodiment of the invention. FIG. 9 is a conceptual diagram of another example of how to use the buffer of the present invention, and FIG. 10 is a conceptual diagram of another example of how to use the buffer of the present invention.
1 Figure 2 Figure 3 y] 4 Figure Liu 5 Figure 6 Mouth〒 7th n VJ B Figure

Claims (1)

[Claims] 1. A first np whose collector and emitter are respectively connected to the first power supply end and output end, and whose base is connected to the input end.
n (pnp) transistor, and a second transistor whose collector and emitter are connected to the output terminal and the second power supply terminal, respectively.
a p(n) channel MOS transistor connected between the collector and base of the second npn (pnpJ) transistor and having its gate connected to the input terminal; (pnp)) base of transistor,
a ncp) channel MOS transistor connected between emitters and having its gate connected to the input terminal. 2. A first npn (pnp) transistor whose collector and emitter are connected to a first power supply terminal and an output terminal, respectively, and a second npn (pnp) transistor whose collector and emitter are respectively connected to the output terminal and a second power supply terminal. a first n(p) channel MOS transistor connected between the collector and base of the first npn (pnp)) transistor, and having its gate connected to the input terminal; a second n(1)) or sub-main channel MO8) transistor connected between the base and emitter of the first flpn (Cpnp) transistor and whose gate is connected to the input terminal; 1)nl)) between the base of the transistor, , c-mitter, or the first . second np
n (1) np) I - a first 1) (n
) channel MOS transistor; and a second p(n) channel MOS transistor connected between the collector and base of the second npn (Cpnp) transistor and having its gate connected to the input terminal. 3. 3. The buffer circuit according to claim 2, wherein the Ω first n-channel transistor is of a depletion type. 4. A first npn (pnp) transistor whose collector and emitter are connected to the first power supply end and the output end, respectively; and a second npn (pnp) transistor whose collector and emitter are connected to the output end and the second power supply end, respectively. an npn (pnp) transistor; The second npn (
a first p(n) channel MO connected between the paces of the pnp) transistor and having its gate connected to the input end;
a second p(n) transistor connected between the base of the first npn (pnp) transistor and the input terminal, and having its gate connected to the emitter of the first npn (pnp) transistor; a third p(n) channel MO8) transistor connected between the collector and base of the second npn (pnp) transistor, and whose gate is connected to the input terminal; , the second npn (I)nl)) transistor.