JPH0262117A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPH0262117A
JPH0262117A JP63335698A JP33569888A JPH0262117A JP H0262117 A JPH0262117 A JP H0262117A JP 63335698 A JP63335698 A JP 63335698A JP 33569888 A JP33569888 A JP 33569888A JP H0262117 A JPH0262117 A JP H0262117A
Authority
JP
Japan
Prior art keywords
trs
input signals
low level
logic circuit
level signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63335698A
Other languages
Japanese (ja)
Inventor
Yoon-Seung Shin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH0262117A publication Critical patent/JPH0262117A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

PURPOSE: To configure a logic circuit by forming the circuit with 2n-sets of MOS transistors (TRs) and 2-sets of bipolar TRs, where (n) is the number of input signals so as to reduce the number of components.
CONSTITUTION: When PMOS TRs T1, T2 are simultaneously conductive in response to input signals A, B, a high level signal is given to bases of bipolar TRs Q1, Q2. On the other hand, when either of NMOS TRs T3, T4 is conductive in response to the input signals A, B on the other hand, a low level signal is given to the bases of bipolar the TRs Q1, Q2. When the input signals A, B are both at a low level, the TR Q.1 is conductive and the TR Q2 is nonconductive and a high level output signal P is outputted. On the other hand, at least either of the input signals A, B is at a high level, a low level signal is given to the bases of the TRs Q1, Q2 and a low level signal P is outputted. Thus, the logic circuit is configured in this way.
COPYRIGHT: (C)1990,JPO
JP63335698A 1988-08-06 1988-12-28 Logic circuit Pending JPH0262117A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880010071A KR910005612B1 (en) 1988-08-06 1988-08-06 Highly integarted bi-cmos logic circuit

Publications (1)

Publication Number Publication Date
JPH0262117A true JPH0262117A (en) 1990-03-02

Family

ID=19276782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63335698A Pending JPH0262117A (en) 1988-08-06 1988-12-28 Logic circuit

Country Status (2)

Country Link
JP (1) JPH0262117A (en)
KR (1) KR910005612B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598431A (en) * 1982-07-07 1984-01-17 Hitachi Ltd Buffer circuit
JPS61198817A (en) * 1984-12-10 1986-09-03 Hitachi Ltd Composite circuit combining bipolar transistor and field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598431A (en) * 1982-07-07 1984-01-17 Hitachi Ltd Buffer circuit
JPS61198817A (en) * 1984-12-10 1986-09-03 Hitachi Ltd Composite circuit combining bipolar transistor and field effect transistor

Also Published As

Publication number Publication date
KR910005612B1 (en) 1991-07-31
KR900004109A (en) 1990-03-27

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