JPH0440893B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low power consumption, high speed buffer circuit that combines CMOS and bipolar.

Conventionally, attempts have been made to combine CMOS, bipolar, and transistors to construct a buffer circuit that combines the low power consumption of CMOS and the high speed of bipolar. FIG. 1 shows an example of a buffer circuit and an inverter. Although circuits of this type with different configurations are known, inverters are the most common.

For technology related to the present invention, see IE Transactions on Electron Devices, Vol. ED-16, No. 11,
November 1969, pp. 945-951 (IEEE
TRANSACTIONS ON ELECTRON
DEVICES Vol.ED−16, Noll, Nov.1969,
pp.945-951). In addition, U.S. Patent No. 3609479 (especially Fig. 9) and
It is described in Publication No. 35761 (especially Fig. 9).

However, these techniques have not been able to prevent the saturation operation of bipolar transistors.

By the way, this kind of buffer circuit is, for example,
It is possible to configure high-speed, low-power consumption logic gates with high drive capacity added to CMOS logic gate circuits, or to configure lightly loaded circuit parts within an LSI using only CMOS, and use these only for heavily loaded circuits. It is suitable for adding a buffer circuit to construct a highly integrated, high-speed, low-power LSI as a whole. For example, Figure 2 shows an example of such a circuit configuration, and shows a CMOS gate (for example, 2 inputs).
Bipolar (NAND gate shown)
CMOS buffer circuit (for example, the circuit in Figure 1)
is added. In this circuit configuration, if the load CL (the sum of the wiring capacitance and the input capacitance of the next-stage gate to be driven) is small (for example, about 0.1 pF), CMOS alone is generally fast enough, and the buffer circuit If this is added, the response of the load drive will become slower. However, when CL becomes large (for example, about 1 pF), the CMOS circuit becomes extremely slow due to its poor driving ability, and the delay time becomes several times (for example, more than three times) that of a light load. In this case, by adding a bipolar and CMOS composite buffer circuit, the delay time of the entire circuit including the additional circuit portion can be shortened (for example, to about twice that of a CMOS circuit under light load). Needless to say, if the load CL is even larger, the effect of increasing speed by adding a buffer circuit will be even greater.

Note that in the circuit shown in Figure 1, the lower half of the circuit
Contains CMOS source follower circuit. Generally, CMOS source follower circuits have no voltage gain and are known to be slow. For this reason, the circuit shown in FIG. 1 still has the problem of being insufficient in terms of high-speed operation.

By the way, as shown in Figure 2, usually
CMOS logic gates have NAND and NOR as their basic circuits, and when an inverter circuit is combined with these gates, it becomes a logic that does not include negation, such as AND or OR. Figure 2 shows one example.
At the output of the NAND gate composed of CMOS,
A bipolar and CMOS composite buffer circuit 22 as shown in FIG. 1 is connected to obtain an AND circuit.

However, it is difficult to frequently use such combinations that result in positive logic circuits, or to construct random logic as a basic circuit. Therefore, a non-inverter type buffer circuit with high speed and low power consumption is desired as these buffer circuits.

Therefore, the object of the present invention is to
Our objective is to provide a high-speed, low-power, non-inverter type composite buffer circuit that combines CMOS.

In order to achieve the above object, the inventors of the present application have studied a method of configuring a buffer circuit.

FIG. 3 shows the first circuit considered by the inventors of the present application. This circuit is an n-channel MOS transistor
QM1 and QM4, p-channel MOS transistors
It consists of QM2, QM3, and npn bipolar transistors QB1 and QB2. This circuit operates as follows. First, consider a state where both input and output are at high levels. At this time, QM2 and QM3 are off, and QM1 and QM4 are on. Therefore QB2 is off. Furthermore, since the load on the output OUT is capacitive, QB1 is also mostly off in a steady state. Under this condition, if the output OUT becomes low level for some reason (for example, leakage current from the load connected to the output), then it will pass through QM1.
Base current is supplied to QB1 and the output OUT is kept at a high level. Almost as long as OUT is at a high level
QB1 is off, so little current flows in steady state. Next, consider a situation where the input IN switches from high level to low level. Immediately after switching, the output OUT is still at a high level. In this state, QM2 and QM3 are on, and QM1 and QM4 are off. The charge accumulated in the base of QB1 is extracted by QM2 and QB1 is turned off. On the other hand, QB2 is turned on because the base current is supplied through QB3. Therefore, a current that is h _FE times the base current flows through the collector of QB2, so
The output OUT quickly goes to a low level. Output OUT
When becomes a low level, the base current from the output OUT to QB2 is no longer supplied, and QB2 is turned off. In this state, QM2 is also on, but
Since the base charge of QB1 has already been extracted,
No current flows. In other words, even if both input and output are in a steady state with low levels, no current other than leak current flows. Next, consider the case where the input switches from low level to high level. Immediately after the input switches, the output is still at a low level. Therefore,
QM1 is on, QM2 is off, QM3 is off, QM4 is
It turns on, and base current is supplied to QB1 via QM1, while the base charge of QB2 is extracted by QM4. Therefore, QB2 turns off quickly and the output OUT goes to a higher level due to QB1. When the output OUT becomes completely high level, QM1
The base current no longer flows and returns to the state described at the beginning.

As explained above, in the circuit shown in Figure 3, as long as the input/output remains at a high or low level, only leakage current flows and the power consumption is almost zero, and power flows during the switching transition. Only. Therefore, overall power consumption is low and can be considered to be the same as CMOS. On the other hand, when viewed from the output, MOS
Since the gm of the transistor appears to be multiplied by h _FE (that is, about two orders of magnitude), the speed can be sufficiently increased even if the output load capacity is large. Note that in order to increase speed, it is desirable that QM1 (or QM3 as the case may be) be of a depletion type.

The circuit in Figure 3 above includes a transistor QM
1. Contains a CMOS source follower circuit consisting of QM2. Therefore, the circuit shown in FIG. 3 is still insufficient in terms of high-speed operation.

FIG. 4 shows a second circuit considered by the inventors of the present application. The difference between this circuit and the circuit in Figure 3 is that
The only difference is that the drain of QM2, which was connected to the output OUT in the figure, is connected to the base of QB2 in Figure 4. In the circuit shown in Figure 4, when the input switches from high level to low level, the charge extracted from the base of QB1 is supplied to QB2 as a base current, so QB2 turns on faster by that amount. Become. Regarding other operations, FIG. 4 and FIG. 3 are the same.

By the way, in the examined circuits of FIGS. 3 and 4, it is desirable that QM1 be of the depletion type in order to increase the speed. Unless it is a depletion type,
This is because even if the input is at a high level, it is not possible to supply enough base current to make the output at a sufficiently high level. Therefore, it is difficult to maintain the output at a sufficiently high level and to increase the speed. On the other hand, since the other MOS transistors shown in FIGS. 3 and 4 are generally enhancement type (of course, it goes without saying that they can be made into depletion type if necessary), the implementation of FIGS. In this example, in order to improve performance, it is necessary to use both enhancement type and depletion type MOS transistors, which makes the process somewhat complicated.

In the circuit shown in Figure 4, the transistor QM
1. Contains a CMOS source follower circuit consisting of QM2. Therefore, the circuit of FIG. 4 is still insufficient in terms of high-speed operation.

FIG. 5 shows the third circuit considered by the inventors of the present application. In this circuit, in Figures 3 and 4,
QM1 and QM2 are removed and the base of QB1 is directly connected to the input terminal. In this case, since QB1 is in the on state except when the input is at an extremely low level, it has the disadvantage that all the noise on the input appears on the output side. However, this circuit can be used if sufficient noise margin is ensured. Note that the operation of this circuit is clear from the explanation of the operation in FIGS. 3 and 4, so the explanation will be omitted.

Since the circuit of FIG. 5 also does not use a CMOS source follower, a high-speed buffer circuit can be obtained. Furthermore, as described later, a high-speed circuit can be obtained by connecting a CMOS inverter at the front stage.

As described above, the means of the present invention for solving the problems of the prior art described above includes a buffer circuit B including a CMOS and a bipolar transistor, and a MOS circuit A connected to the input of the buffer circuit. become bipolar
The buffer circuit B, which is a CMOS composite circuit, has an input terminal IN, an output terminal OUT, and a first terminal whose collector is connected to the first operating potential point and whose emitter is connected to the output terminal OUT.
npn transistor QB11, and a second transistor whose collector is connected to the output terminal OUT and whose emitter is connected to the second operating potential point.
an npn transistor QB12, a first p-channel MOS transistor whose gate is connected to the input terminal IN, whose drain is connected to the base of the second npn transistor QB12, and whose source is connected to the output terminal OUT.
QM13, and an n-channel MOS transistor QM1 whose gate is connected to the input terminal IN, whose drain is connected to the base of the second npn transistor QB12, and whose source is connected to the second operating potential point.
4, and a second p-channel MOS transistor whose gate is connected to the output terminal OUT, whose drain is connected to the base of the first npn transistor QB11, and whose source is connected to the input terminal IN.
QM12, and a third p-channel MOS transistor QM11 whose gate is connected to the input terminal IN and whose source is connected to the base of the first npn transistor QB11, and the MOS circuit A has an input signal at its gate. is applied, and the drain is connected to the input terminal of the buffer circuit B.
The purpose is to make it a composite circuit. (Figure 6, Figure 7,
See Figure 8. ) According to the above means, the npn transistor QB11
Connect the base of the terminal to the input terminal IN in a direct current manner. Therefore, there is no MOS transistor in the preceding stage of QB11. Therefore, QB11 will start up very quickly.

Furthermore, the two MOS transistors in the preceding stage of the npn transistor QB12 are not source followers but a source common circuit. Therefore this
MOS transistor circuit operates at high speed.

As a result, a buffer circuit that is significantly faster than conventional techniques can be obtained.

Hereinafter, it will be explained in detail using examples.

FIG. 6 is a circuit diagram of an embodiment of the present invention. This circuit consists of a p-channel MOS transistor QM11,
QM12 and QM13, n-channel MOS transistor QM14, npn bipolar transistor QB1
Consists of 1 and QB12.

The operation of this circuit will be briefly explained. First, consider a state where both input and output are at high levels. At this time, QM11, QM12, and QM13 are off,
Only QM14 is on. Therefore, QB11,
QB12 is also off. Output under this condition
If OUT becomes low level for some reason (for example, leakage current from the load connected to the output), QM12 turns on, base current is supplied to QB11 from the input terminal IN, and the output OUT is kept at a high level. . As long as OUT is at a high level, QB11 is off, so little current flows in steady state. Next, consider a situation where the input IN switches from high level to low level. Output immediately after switching
OUT is still at a high level. In this state, QM
11 and QM13 are on, and QM12 and QM14 are off. The charge accumulated in the base of QB11 is extracted by OM11, and QB11 is turned off. On the other hand, QB12 is turned on because the base current is supplied through QM13. Therefore, QB1
Since a current that is h _FE times its base current flows through the collector of 2, the output OUT quickly goes to a low level. When the output OUT becomes low level, the output OUT
The base current from QB12 is no longer supplied to QB12, and QB12 is turned off. In this state, QM1
1. QM12 is also on, but the base charge of QB11 has already been extracted, so no current flows. In other words, even if both input and output are in a steady state with low levels, no current flows except for leakage current. Next, consider the case where the input changes from low level to high level. Immediately after the input switches, the output is still at a low level. Therefore, QM1
1 is off, QM12 is on, QM13 is off,
QM14 turns on, passes through QM12 and then QB11
While the base current is supplied to QB12, the base charge of QB12 is extracted by QM14. Therefore,
QB12 turns off quickly and the output OUT is QB1
1 to go to a higher level. When the output OUT reaches a completely high level, the QM 12 is turned off and returns to the state described at the beginning.

As explained above, according to this embodiment, as long as the input/output remains at a high or low level, only leakage current flows and the power consumption is almost zero. Current only flows during switching transients. Therefore, the power consumption as a whole can be considered to be almost the same as that of CMOS, and there is an effect that a low power consumption gate can be obtained. Also, the effective gm of the CMOS gate is h _FE
It can be thought of as being multiplied, and has the effect of obtaining a high gain gate. .

FIG. 7 is a circuit diagram of another embodiment of the present invention. The difference from the circuit in Figure 6 is that the output is in Figure 6.
The drain of QM11 connected to OUT is
In FIG. 7, it is connected to the base of QB12. In the circuit of FIG. 7, when the input switches from high level to low level, the charge extracted from the base of QB11 is supplied to QB12 as a base current. Therefore, the time the QB 12 is turned on becomes earlier. Regarding other operations, FIG. 7 and FIG. 6 are the same. In addition, the 6th
In the circuits shown in Figures and Figure 7, the base current of QB11 must be supplied by the previous stage circuit, so the third stage circuit must supply the base current of QB11.
A somewhat larger driving capacity is required in the front stage than in the case of FIGS.

The embodiments of FIGS. 6 and 7 do not include a CMOS source follower circuit. Both examples are npn
The base of the transistor QB11 and the input terminal IN are DC-coupled via the drain-source current path of the p-channel MOS transistor QM12. Therefore, it has the effect of providing a faster gate speed than a buffer circuit using a CMOS source follower.

A usage example of the circuit described in the above embodiment will be briefly described.

Figure 8 shows the 3-input CMOS NAND gate A and the 7th
This is an example of combining circuit B in the figure, with a total of 3
It constitutes an input NAND circuit. The delay time of this circuit was compared with that of the ECL circuit, which is currently the most standard high-speed bipolar logic circuit, assuming the same level of process. As a result, for a load capacitance of 1pF, the delay time of the circuit in Figure 8 is
It was found that it is almost the same as ECL. Also,
The delay times in both parts A and B were approximately equal, each about half of the ECL delay time. Also, the power consumption at this time is the switching cycle time of 50 ns.
Assuming that, it is extremely small, about 1/20th of ECL. In other words, if the circuit shown in Figure 8 is used, an LSI with approximately 20 times higher integration than ECL can be constructed in terms of power consumption, and the delay time of the unit gate can be basically the same as ECL.

Other approaches to using the buffers of the present invention are also possible. FIG. 9 shows the concept, where A is a logic circuit network consisting of a combination of a plurality of CMOS gates, and B, B', etc. are buffer circuits of the present invention. In this case, the CMOS gate circuit network is grouped together within a range that is considered to have a sufficiently light load on each gate, and each CMOS
The gate operates under light load conditions (that is, the loaded gate is placed nearby and the wiring capacitance, etc. is small). On the other hand, when the load is heavy, such as when an input is applied to a gate located far away within the chip, or when there is a large number of fan-outs, the signal is transmitted via the buffer circuit B or the like. Therefore,
The increase in delay time due to load is small. A simple case of such usage is shown in FIG.
In this case, for example, the signal input from I2 is
It passes through CMOS gates A1, A3, and A4, is buffered by B2, and goes out to output O2. In this case, A
1, A3, and A4 are light in load, so each operates with a delay time about 1/2 that of ECL. Further, even if the load on the output O2 is heavy, this part also operates with a delay time that is approximately 1/2 that of ECL, so the three stages of gates operate with a delay time that is twice as long as ECL as a whole. This reduction in delay time becomes greater as the number of cascaded gates in the CMOS gate network increases. However, since the load generally increases as the number of gates increases, there is an optimum point somewhere. This optimum point is determined by the process technology used, the level of circuit design technology, etc. Furthermore, in the case of the method of use shown in FIG. 9, the number of bipolar/CMOS buffers used is reduced, so that the increase in chip area due to the use of buffers can be kept to a minimum. In addition, in actual use, bipolar
As a CMOS composite buffer, a combination of both non-inverter type and inverter type will be used, but in that case, what kind of conventional inverter type buffer can be used in combination with the buffer of the present invention? May be used.

FIG. 11 is a diagram showing computer simulation results showing the effects of the present invention. The horizontal axis is the load capacity
CL, the vertical axis is the gate delay time tpd. The straight line indicated by L2 in Figure 11 is the input terminal of the circuit in Figure 5.
These are the characteristics calculated for a circuit in which the previous stage CMOS inverter circuit in FIG. 2 is added to IN, and a load capacitance CL is added to the output terminal OUT of the circuit in FIG.

The straight line indicated by L1 in FIG. 11 is the characteristic calculated for the first studied circuit including the CMOS source follower shown in FIG. Here, no inverter circuit is added to the front stage, and the characteristics are based only on the circuit shown in FIG. 3. The result has been obtained that this characteristic has a longer delay time than the above-mentioned L2.

From this figure, even if an inverter is added to the front stage of the circuit of FIG. 5, the delay time is even smaller than that of the circuit of FIG. 3, and a significant increase in speed can be achieved.

Generally, in CMOS circuits, inverter circuits are used as much as possible because CMOS source follower circuits are slow. Therefore, when driving a large load, the CMOS gate in front of the output buffer circuit is often an inverter circuit. On the other hand, the buffer circuit that receives the output of the CMOS inverter requires both an inverter type and a non-inverter type depending on the output logic requirements. For this reason, there are circuits with a CMOS inverter in the front stage of an inverter type buffer circuit, and circuits with a CMOS inverter in the front stage of a non-inverter type buffer circuit.
It is desirable that any circuit with a CMOS inverter be fast. According to the present invention, a high-speed non-inverter type buffer circuit can be obtained.

Note that in the present invention, V _TH of the MOS transistor
You can change the speed, power consumption, output level, etc. by changing the , but this is a matter of design.
It goes without saying that this is within the scope of the present invention.

Furthermore, it goes without saying that the same operation can be achieved by replacing the npn transistor with a pnp transistor and replacing the p-channel MOS transistor with the n-channel MOS transistor.

As described above, according to the present invention, a non-inverter type high speed, low power consumption composite buffer circuit can be obtained, and a desired logic circuit with high driving ability can be easily constructed, so that its industrial value is great.

[Brief explanation of drawings]

Figure 1 shows a conventional inverter-type buffer circuit.
Figure 2 is a diagram showing how to use the buffer circuit according to the present invention, Figure 3 is the first circuit considered by the inventors of the present application, Figure 4 is the second circuit examined by the inventors of the present application, and Figure 5 is 6 is a diagram showing one embodiment of the present invention, FIG. 7 is a diagram showing another embodiment of the present invention, and FIG. 8 is a diagram of a buffer circuit of the present invention. A diagram showing an example of how to use it,
FIG. 9 is a conceptual diagram of another embodiment of the method of using the buffer of the present invention, FIG. 10 is a diagram showing a simple usage example embodying the concept of FIG. 9, and FIG. 11 is a diagram showing the effect of the present invention. It is a figure which shows the result of the computer simulation shown. In the figure, IN...input terminal, OUT...output terminal, QB1, QB2...npn transistor, QM
3...p channel MOS transistor, QM4...
...N-channel MOS transistor.

Claims (1)

[Claims] 1. A bipolar device comprising a buffer circuit including a CMOS and a bipolar transistor, and a MOS circuit connected to the input of the buffer circuit.
The buffer circuit is a CMOS composite circuit, and includes an input terminal, an output terminal, a first npn transistor whose collector is connected to the first operating potential point and whose emitter is connected to the output terminal, and whose collector is connected to the first operating potential point. a second npn transistor connected to the output terminal and having its emitter connected to a second operating potential point; a gate connected to the input terminal, a drain connected to the base of the second npn transistor, and a source is connected to the above output terminal.
a channel MOS transistor; an n-channel MOS transistor having a gate connected to the input terminal, a drain connected to the base of the second npn transistor, and a source connected to the second operating potential point; a second pn transistor connected to the output terminal, whose drain is connected to the base of the first npn transistor, and whose source is connected to the input terminal;
a third p-channel MOS transistor whose gate is connected to the input terminal and whose source is connected to the base of the first npn transistor, and the MOS circuit has an input signal applied to its gate. is,
A bipolar CMOS composite circuit comprising an n-channel MOS transistor whose drain is connected to the input terminal of the buffer circuit. 2. The bipolar CMOS composite circuit according to claim 1, wherein the drain of the third p-channel MOS transistor is connected to the output terminal. 3. The bipolar CMOS composite circuit according to claim 1, wherein the drain of the third p-channel MOS transistor is connected to the base of the second npn transistor.