JP2552107B2 - Synchronous compound integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bipolar / CMOS composite type synchronous basic logic circuit which is small in size, has a high operation speed, and consumes little power.

(Summary of the Invention) The present invention is an integrated circuit device in which a plurality of p-channel enhancement type MOSFETs, n-channel enhancement type MOSFETs and npn bipolar transistors are mounted on the same semiconductor substrate, and an input signal line is connected to a gate electrode. A signal input circuit having at least two or more nMOSFETs, a gate electrode connected to a clock signal line, a source connected to a power supply line, and a train connected to one terminal of the signal input circuit. A first pMOSFET, and a fourth nMOSFET having a gate electrode connected to the clock signal, a source connected to the ground line, and a drain connected to the other terminal of the signal input circuit. A node having a connection point between the pMOSFET of 1 and the signal input circuit as a node, which has a logical function.
And a second pMOSFET, and fifth and sixth nMOSFETs whose gate electrodes are connected to the node and which are connected in cascade, and the source of the second pMOSFET is a power supply. Connected to a line, the drain is connected to the drain of the fifth nMOSFET, the source of the fifth nMOSFET is connected to the drain of the sixth nMOSFET, and the source of the sixth nMOSFET is connected to the drain of the seventh nMOSFET. , The source of the seventh nMOSFET is connected to the ground line, the gate electrode is connected to the clock signal input line, and has the first and second npn bipolar transistors connected in series. The base of the transistor is the drain of the second pMOSFET and the fifth
Connected to the drain connection point of the nMOSFET, the collector connected to the power supply line, the emitter connected to the collector of the second npn bipolar transistor, and the base of the second npn bipolar transistor connected to the source of the sixth nMOSFET. Connected to the drain of the 7th nMOSFET,
The emitter is connected to the ground wire, and the fifth nMOSFET is connected.
Point between the source of the second npn and the drain of the sixth nMOSFET, and the emitter and the second npn of the first npn bipolar transistor
A second node having a logical inversion function in which connection points with the collector of the bipolar transistor are connected to the output signal lines, respectively.
By including the partial circuit B of 1., the synchronous composite basic logic gate circuit realizes a part that realizes a complicated logic function with the smallest size nMOSFET and drives the output load with the npn bipolar transistor having a large driving capability. This is a high-density and high-speed LSI that has a circuit configuration that enables it.

(Problems to be Solved by Prior Art and Invention) A conventional device of this type is configured as shown in FIG. 3 or FIG. FIG. 3 shows a case where a single-phase clock is used, and FIG. 4 shows a case where a 4-phase clock is used.
In FIGS. 3 and 4, Q _11a and Q _21a are p channel enhancement type MOSFETs, Q _{1 to} Q ₃ , Q _11b , Q ₁₂ and Q _21b.
Is an n-channel enhancement type MOSFET, 1 to 3 are input signal terminals, 11 and 12 are clock signal terminals, 10 is a first internal signal terminal, 20 is an output signal terminal, 100 is a power supply terminal, and 101 is a first partial circuit. , 102 are second partial circuits. In these basic logic circuit devices, the logic function in 101 is nMOSFET.
It is realized only by itself, the input gate capacitance is smaller than that of pure CMOS, and high-speed operation is expected. Also, the clock signal
When 11 is in the low level state, the DC current path from the power supply 100 to ground is cut off because Q _11b is in the off state, and when the clock signal 11 is in the high level state, Q _11a is in the off state. The characteristics are that it performs a complementary operation of being cut off, has no power consumption in the steady state, and is a low power operation. However, when applied to the part where the wiring capacitance load becomes dominant, the delay time of the wiring capacitance governs the delay time rather than the input capacitance of the next stage. Therefore, the channel width of Q _21a and Q _21b forming the buffer partial circuit of 102 is In order to shorten the gate capacitance charging / discharging time of 102, which increases due to this, it is also necessary to increase the transistor channel width of 101, so the input gate capacitance is smaller than that of pure CMOS However, it has the drawback of halving the characteristics of the circuit that are expected to be realized and increasing the occupied area. In the circuit configuration of FIG. 4, the partial circuit 102 is not essential for operation, but the part where the wiring capacitance is dominant is a partial circuit required for speeding up, and is similar to the above. For the same reason, they had the same drawback. Furthermore, in both FIGS. 3 and 4, the larger the number of inputs, the larger the number of MOSFETs connected in series, the lower the load driving capability, and the delay time is significantly delayed.

(Means for Solving Problems) In order to eliminate these drawbacks, the present invention provides a synchronous logic circuit portion necessary for realizing a logic function with a CM of a minimum size.
It is composed of OSFETs, and all outputs are driven through bipolar and CMOS composite inverting buffer circuits to maintain low power consumption, increase delay time due to increased wiring capacitance, and load drive capability with increased number of inputs. It is an object of the present invention to provide a synchronous composite type integrated circuit device capable of preventing the deterioration of the transistor without increasing the size of the constituent transistors.

Next, examples of the present invention will be described. It is needless to say that the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention.

FIG. 1 shows a first embodiment of a synchronous composite type integrated circuit device of the present invention, in which Q _11a and Q _21c are p-channel enhancement type MOSFETs, Q _{1 to} Q ₃ , Q _11b and Q _{12 respectively.} ，
Q _21d and Q _21e are n-channel enhancement type MOSFET, Q
_20a , Q _20b are npn bipolar transistors, 1 to 3 are input signal terminals, 12 and 12 are clock signal terminals, 10 is a node, 20
Is an output signal terminal, 100 is a power supply terminal, 101 is a first partial circuit A for realizing a logical function in synchronization with a clock signal, and 102 is a bipolar and CMOS composite inverting buffer for driving an output load capacitance. It is a second partial circuit B.

More specifically, in an integrated circuit device in which a plurality of p-channel enhancement type MOSFETs, n-channel enhancement type MOSFETs and npn bipolar transistors are mounted on the same semiconductor substrate, input signal lines are connected to the gate electrodes and Cascaded first and second n-type MOs
The input signal circuit composed of SFETs Q ₁ and Q ₂ and a third n-type MOSFET Q ₃ connected in parallel with these cascade-connected elements and having an input signal line connected to the gate electrode and the gate electrode are clocked. A fourth nMOSFET Q _11b connected to the signal line 11, the source connected to the ground line, and the drain connected to the other terminal b of the signal input circuit, and the first pMOSFET and the signal input. The connection point with the circuit is node 10
And a first partial circuit A having a logical function is configured,
A second pMOSFET Q _21c , a fifth and a sixth nMOSF of which gate electrodes are connected to the node 10 and which are connected in cascade.
ETQ _21d and Q _21e , the source of the second pMOSFET Q _21c is connected to the power supply line, and the drain is the fifth nMOSFET Q _21d.
The source of nMOSFET Q _21d is connected to the drain of
Is connected to the drain of nMOSFETQ _21e, the source of NMOSFETQ _21e is connected to the drain of the seventh nMOSFETQ _11c, the nMO
The source of the SFETQ _11c is connected to the ground line, and the gate electrode is connected to the clock signal line 11. Also, the first and second npn bipolar transistors Q _20a and Q ₂₀ connected in series are connected.
_20b and the base of the first npn bipolar transistor Q _20a is the drain of the second pMOSFET Q _21c and the fifth nMOSFET Q 20c.
_It is connected to the connection point of the drain of _21d , the collector is connected to the power supply line, and the second npn bipolar transistor Q
The base of _20b is the source of the sixth nMOSFET Q _21e and the seventh nMOS.
It is connected to the connection point with the drain of FETQ _11c , and the emitter is connected to the ground wire. Furthermore, the fifth nMOSFE described above.
The connection point between the source of the TQ _{21d and} the drain of the sixth nMOSFET Q _21e and the connection point of the emitter of the first npn bipolar transistor Q _20a and the collector of the second npn bipolar transistor Q _20b are connected to the output signal line 20, respectively. As a result, a second partial circuit B having a logically inverting function is formed.

In the case of the signal input circuit, three nMOSFETs are used in the case shown, and one nMOSF is provided for two cascaded nMOSFETs.
The ETs are connected in parallel, but it is also possible to connect three nMOSFETs in cascade, or they can be connected in parallel with each other, and a desired logic circuit is constructed using four or more nMOSFETs. You can also do it.

Regarding the back gate connection, pMOSFET is connected to the power line and nMOSFET is connected to the ground line.

To operate it, the clock signal 11 is set to low level during the precharge period, Q _11b and Q _11c are turned off, Q _11a is turned on, node 10 is set to high level, Q _21c is turned off and Q _21d is turned on. , Q _21e is turned on to pull out the excess base carrier of Q _20a and turned off, and Q _21e is turned on to output terminal 20
The base current of Q _20b is supplied to turn on Q _20b and maintain the output terminal 20 at a low level. As a result, the gate electrodes of the FET transistors typified by Q _{1 to} Q ₃ in the gates connected to the next and subsequent stages are at a low level and are in an off state. Next, the clock signal is set to a high level, Q _11a is turned off, Q _11b and Q _11c are turned on, and the signal levels of the input signals 1 to 3 connected to the gate electrodes of Q _{1 to} Q ₃ are changed in the first stage of the constituent network. Once established, the level of internal node 10 will be Q ₁ , Q ₂ or Q ₃ and Q _11b depending on the logic function of its gate.
Through the low level or Q _{1 to} Q ₃
Is turned off and it is determined whether to maintain the high level charged during the precharge period, and that state determines the logic level of the output terminal 20 through the inverting buffer 102, and the signal level is sequentially increased from the first stage to the last stage of the network. Will be decided. node
The operation of 102 when 10 is in the low state is that Q _21d , Q _21e are off, Q _21c is on, and the excess minority carrier in the base of Q _20b is discharged through Q _11c , which is on. , from the base current power is supplied through Q _21c Q _20a
Turns on, and the output terminal 20 is charged from the power supply through Q _{20a and} goes to a high level state.

Therefore, the operation when the clock signal 11 changes from the low level to the high level is that the node 10 changes from the high level to the low level and the output terminal 20 changes from the low level to the high level, at which time Q _20b is quickly cut off. It becomes a state. That is, Q
_Because the gate of _11c has the opposite logic state from the gates of Q _21c , Q _21d and Q _21e , it is not possible to simply connect node 10 to the gate of Q _11c , and clock signal 11 to Q _11c
If it is not connected to the gate of, the normal buffer circuit configuration will be adopted, and from node 10 via inverter
The configuration is such that it is connected to the gate of Q _11c , but in such a configuration the delay time of the inverter may delay the time for the gate of Q _11c to change from the low level to the high level.
_{In order} to quickly cut off _20b , it is necessary to turn on Q _11c as quickly as possible to lower the base potential of Q _20b , so the configuration employing the above inverter is disadvantageous for high speed operation. Therefore, by connecting the clock signal to the gate of Q _11c , the clock signal 11 goes high before the node 10 goes low, so that Q _20b quickly goes into the cutoff state and the output terminal 20 goes high. The speed in achieving the level will be improved.

With such a structure, it is possible to charge and discharge the load capacitance of the output terminal in the precharge period and the operation period transition region by using the bipolar transistor having a large load driving capability, and realize the logical function.
The constituent transistor size of 101 is minimized, and high-speed operation is possible. Further, since the base current injecting MOSFET that determines the driving capability of the bipolar transistor in the output stage is irrelevant to the increase in the number of inputs, the load driving capability does not change even if the number of cascade-connected MOSFETs increases due to the logical function. Further, in the steady state, all DC paths from the power supply 100 to the ground are cut off, and the feature of low power consumption is maintained.

Figure 2 is a second embodiment of the present invention, between the nMOSFET and PMOSFETQ _11a of Q ₁ to Q ₃ for implementing logical functions, a second
It is applied to a CMOS 4-phase dynamic circuit in which an eighth nMOSFET Q ₁₂ which operates according to the clock signal 12 is connected in series.

That is, as the configuration of the first partial circuit 101, a signal input circuit having three nMOSFETs whose input signal line is connected to the gate electrode, a gate electrode connected to the first clock signal line 11, and a source connected The first pMOSFET Q _11a connected to the power supply line 100 and having the drain connected to the drain of the eighth nMOSFET Q ₁₂ , the gate electrode connected to the second clock signal line 12, and the source connected to the input signal circuit described above. The eighth nMOSFET Q ₁₂ (the back gate is connected to the ground line) connected to one terminal a, the gate electrode is connected to the first clock signal line 11, the source is connected to the ground line, and the drain is A fourth nMOSFET Q _11b connected to the other terminal b of the signal input circuit is provided, and the first pMOSFET Q _11b is provided.
A node 10 is a connection point between the drain of the MOSFET Q _{11a and} the drain of the eighth nMOSFET Q ₁₂ , and a first partial circuit A having a logical function is formed. The second partial circuit B is the same as in the first embodiment.

However, by providing 102 bipolar and CMOS composite buffer circuits, it is not necessary to set the transistor channel width according to the output load capacitance, and the 101 transistor size that realizes the logic function is minimized to achieve high-speed logic. The operation can be realized.

(Effects of the Invention) As described above, in the synchronous composite basic logic gate circuit of the present invention, the part that realizes the complicated logic function is realized by the minimum size nMOSFET, and the output load is n
The second npn bipolar transistor Q _20b has a circuit structure that can be driven by a pn bipolar transistor, and a clock signal is supplied to the second partial circuit B composed of the npn bipolar transistor or the like.
Can be cut off quickly, and the operation speed can be further increased.
There is an advantage that I can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a single-phase clock type circuit of one embodiment of the synchronous composite integrated circuit device of the present invention, and FIG. 2 is a block diagram of a four-phase dynamic type circuit of another embodiment of the present invention device. FIG. 3 shows a conventional single-phase clock type CMOS basic logic gate circuit diagram, and FIG. 4 shows a conventional 4-phase dynamic type CMOS basic logic gate circuit diagram. 1,2,3 …… Input signal terminal 11,12 …… Clock signal terminal 10 …… Node 20 …… Output signal terminal 100 …… Power supply terminal 101 …… The first partial circuit A 102 for realizing logic function …… Load Second partial circuit B Q _11a , Q _21a , Q _21c having drive buffer function ... P channel enhancement type
MOS transistors Q ₁ , Q ₂ , Q ₃ , Q _11b , Q ₁₂ , Q _21b , Q _21d , Q _21e , Q _11c , Q
_22a , Q _22b …… n Channel enhancement type MOS transistor Q _20a , Q _20b …… npn bipolar transistor Q _20c …… npn bipolar transistor R _1a , R _1b , R ₁ …… resistor

Claims (2)

(57) [Claims] 1. In an integrated circuit device having a plurality of p-channel enhancement type MOSFETs, n-channel enhancement type MOSFETs and npn bipolar transistors mounted on the same semiconductor substrate, at least an input signal line is connected to a gate electrode. Two
A signal input circuit having at least nMOSFETs, a first pMOSFET having a gate electrode connected to the clock signal line, a source connected to a power supply line, and a drain connected to one terminal of the signal input circuit. A gate electrode is connected to the clock signal, a source is connected to the ground line, and a drain is connected to the other terminal of the signal input circuit, and a fourth nMOSFET is provided. A first partial circuit A having a logical function with a connection point to the input circuit as a node, and a second pMOSFET, a fifth and a sixth of which the respective gate electrodes are connected to the node and are connected in cascade. an nMOSFET, the source of the second pMOSFET is connected to the power line, the drain is connected to the drain of the fifth nMOSFET,
The source of the fifth nMOSFET is connected to the drain of the sixth nMOSFET, the source of the sixth nMOSFET is connected to the drain of the seventh nMOSFET, the source of the seventh nMOSFET is connected to the ground line, and the gate electrode is It has first and second npn bipolar transistors connected to the clock signal input line and connected in series. The base of the first npn bipolar transistor is the drain of the second pMOSFET and the fifth npn bipolar transistor.
The drain is connected to the connection point of the MOSFET, the collector is connected to the power supply line, the emitter is connected to the collector of the second npn bipolar transistor, and the base of the second npn bipolar transistor is the source of the sixth nMOSFET. The emitter is connected to the connection point with the drain of the seventh nMOSFET, the emitter is connected to the ground line, the connection point between the source of the fifth nMOSFET and the drain of the sixth nMOSFET, and the first n
A connection point between the emitter of the pn bipolar transistor and the collector of the second npn bipolar transistor is connected to the output signal line, respectively, and a second partial circuit B having a logical inversion function is provided. Synchronous compound integrated circuit device. 2. In an integrated circuit device having a plurality of p-channel enhancement type MOSFETs, n-channel enhancement type MOSFETs and npn bipolar transistors mounted on the same semiconductor substrate, at least an input signal line is connected to a gate electrode. Two
A signal input circuit having at least nMOSFETs, a first pMOSFET having a gate electrode connected to the first clock signal line, a source connected to the power supply line, and a drain connected to the drain of the eighth nMOSFET. , An eighth nMOSFET having a gate electrode connected to the second clock signal line and a source connected to one terminal of the signal input circuit, and a gate electrode connected to the first clock signal line and a source Is connected to a ground line, and a drain is connected to the other terminal of the signal input circuit, and a fourth nMOSFET is provided. A connection point between the drain of the first pMOSFET and the drain of the eighth nMOSFET. A first partial circuit A having a logic function, and a second pMOSFET, a fifth and a sixth nMOSFET having respective gate electrodes connected to the node and connected in cascade, The source of the second pMOSFET is Is connected to a source line, a drain connected to the drain of the fifth nMOSFET,
The source of the fifth nMOSFET is connected to the drain of the sixth nMOSFET, the source of the sixth nMOSFET is connected to the drain of the seventh nMOSFET, the source of the seventh nMOSFET is connected to the ground line, and the gate electrode is It has first and second npn bipolar transistors connected to the clock signal input line and connected in series. The base of the first npn bipolar transistor is the drain of the second pMOSFET and the fifth npn bipolar transistor.
The drain is connected to the connection point of the MOSFET, the collector is connected to the power supply line, the emitter is connected to the collector of the second npn bipolar transistor, and the base of the second npn bipolar transistor is the source of the sixth nMOSFET. The emitter is connected to the connection point with the drain of the seventh nMOSFET, the emitter is connected to the ground line, the connection point between the source of the fifth nMOSFET and the drain of the sixth nMOSFET, and the first n
A connection point between the emitter of the pn bipolar transistor and the collector of the second npn bipolar transistor is connected to the output signal line, respectively, and a second partial circuit B having a logical inversion function is provided. The synchronous composite integrated circuit device according to claim 1.