JPH05335913A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To provide an output buffer circuit capable of suppressing a peak current to suppress fluctuation in a power supply voltage without disturbing a high speed operation by properly adjusting the rise of an output current. CONSTITUTION:A voltage control circuit 5 changes the gate voltage of a 2nd transistor(TR) group 4 when the level of output data of an internal circuit is switched for a prescribed time simultaneously with the gate voltage of a 1st TR group 2. Succeedingly, a voltage control circuit 5 holds the gate voltage of the 2nd TR group 4 for a prescribed time as it is. Then the voltage control circuit 5 changes the gate voltage of the 2nd TR group 4 corresponding to the gate voltage of the 1st TR group 2. The output data of an internal circuit are outputted to the external circuit via the 1st and 2nd TR groups 2, 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor integrated circuit device. 2. Description of the Related Art In recent years, semiconductor integrated circuit devices have been required to output multi-bit data as the speed has increased. Therefore, when the output data of all bits are the same, a large output current transiently flows from the output buffer circuit and the power supply voltage fluctuates, causing malfunction of the internal circuit. Therefore, it has been considered to suppress the peak of the output current of the output buffer circuit. However,
By suppressing the peak of the output current, it takes a long time to determine the level of the output data, which causes a problem that the access time becomes long. Therefore, in the output buffer circuit, it is required to suppress the peak current and suppress the fluctuation of the power supply voltage without hindering the high speed operation.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional totem pole output type output buffer circuit. N-channel MOS transistors 41 and 42 are connected in series between the high potential side power source VDD and the ground serving as the low potential side power source. Data transmitted from an internal circuit via a bus (not shown) (hereinafter,
Input data) is input to the gate of the MOS transistor 42, and M
It is input to the gate of the OS transistor 42. And
Output data is output from the node between the MOS transistors 41 and 42.

Therefore, when the input data is L level, M
The OS transistor 41 is turned on, the MOS transistor 42 is turned off, and the output data becomes H level. When the input data is at the H level, the MOS transistor 41 is turned off, the MOS transistor 42 is turned on, and the output data is at the L level. That is, the output data has an opposite phase to the input data.

FIG. 6 shows the MOS transistor 4 when the input data is switched from the H level to the L level.
1 shows the time change of the gate voltage G41 and the drain current (output current of the output buffer circuit) I41 of No.1.

When the gate voltage of the MOS transistor 41 rises to exceed the threshold voltage and the MOS transistor 41 is turned on, a transiently large output current I41 flows.
When the input data is switched from the L level to the H level, the MOS transistor 42 is simply replaced by the MOS transistor 41, and the same operation is performed.

Here, when the output data of all output bits of the semiconductor integrated circuit device is switched from the L level to the H level, that is, the input data of each output buffer circuit corresponding to the output bit is switched from the H level to the L level. Think about when it will change.

In this case, since the output current of the semiconductor integrated circuit device is the sum of the output currents of the output buffer circuits, its peak value becomes extremely large. However, since the current capacity of the high-potential-side power supply VDD is constant, power consumption momentarily becomes extremely large at the peak of the output current, and the voltage of the high-potential-side power supply VDD may temporarily drop.
The temporary drop in the power supply voltage of the high-potential-side power supply VDD causes power supply noise, which causes malfunction of the internal circuit.

On the other hand, when the output data of all output bits of the semiconductor integrated circuit device is switched from the H level to the L level, that is, the input data of each output buffer circuit corresponding to the output bit is switched from the L level to the H level. At this time, the high-potential-side power supply VDD is replaced with the ground and the MOS transistor 41 is replaced with the MOS transistor 42, and the same operation occurs.

That is, since the output current of the semiconductor integrated circuit device (current drawn from the connected external device) is the sum of the output currents of the output buffer circuits, its peak value becomes extremely large. Then, the current flowing into the ground increases, and the ground potential may temporarily rise. The temporary rise in the ground potential causes power supply noise, which causes malfunction of internal circuits.

As described above, when the output current of the output buffer circuit has a large peak, the power supply voltage on the high potential side or the low potential side (ground) fluctuates, which causes malfunction of the internal circuit. Therefore, it is considered to reduce the peak of the output current by the following method.

One is the MOS transistors 41 and 42.
This is a method in which the transistor size of the inverter circuit 43 for driving the inverter is reduced to slow the rise of the gate voltage and the rise of the output current to lower the peak value.

Another is that each MOS transistor 41,
This is a method of arranging a plurality of 42 in parallel and providing a time difference between the rising edges of the respective gate voltages to shift the respective peak values to make the rising of the output current gentle and lower the peak value.

FIG. 5 shows an example thereof, and MO in FIG.
An N-channel M transistor in which the S transistor 41 is connected in parallel.
It is replaced with the OS transistors 51 and 52. However,
The gates of the MOS transistors 51 and 52 are isolated from each other.

FIG. 5 shows only the pull-up side (H-level output side, upper stage of the totem pole). The pull-down side (L-level output side, lower stage of the totem pole, reverse data side) has the same structure as the pull-up side and is omitted because it is only mirror-inverted.

The drains of both MOS transistors 51 and 52 are connected to the high-potential side power supply VDD, and the sources are connected to the drains of the pull-down side MOS transistors (not shown).

The input data is input to the NOR circuit 53 and also to the gate of the MOS transistor 51 via the inverter circuit 54. In addition, the inverter circuit 5
The output of 4 is input to the NOR circuit 53 via the inverter circuit 55. The output of the NOR circuit 53 is input to the gate of the MOS transistor 52. The output data is output from the sources of both MOS transistors 51 and 52.

Therefore, when the input data is switched from the H level to the L level, the gate of the MOS transistor 51 is delayed by the signal delay time of the inverter circuit 54 to the H level.
A level signal is applied. On the other hand, in addition to the signal delay time of the inverter circuit 54, an H level signal is applied to the gate of the MOS transistor 52 with a delay of the signal delay time t1 of the inverter circuit 55 and the signal delay time t2 of the NOR circuit 53. That is, the MOS transistor 52
Rising of the gate voltage of the MOS transistor 51
In comparison with the rising of the gate voltage of
And the sum of the signal delay times of the NOR circuit 53 (t1 + t2).

FIG. 7 shows the gate voltages G51 and G52 and the drain current I5 of the MOS transistors 51 and 52 when the input data is switched from the H level to the L level.
1, I52 and output current of output buffer circuit (each MOS
The time change of the sum [I51 + I52]) IO of the drain currents I51 and I52 of the transistors 51 and 52 is shown.

When the gate voltages G51, G52 of the MOS transistors 51, 52 rise and exceed their respective threshold voltages and the MOS transistors 51, 52 are turned on, the drain currents I51, I52 reach their peaks. Become.
However, the peak values of the drain currents I51 and I52 are smaller than the peak value of the output current I41 shown in FIG. Further, the rise of the drain current I52 is delayed from the rise of the drain current I51 by the time difference (t1 + t2) between the rises of the MOS transistors 51 and 52. Therefore, the peak of the drain current I52 is different from the peak of the drain current I51 by the time difference (t1).
+ T2).

Therefore, the output current IO of the output buffer circuit
Is smaller than the peak value of the output current I41 shown in FIG. As a result, even when the output data of all output bits of the semiconductor integrated circuit device is switched from the H level to the L level, the peak value of the output current of the semiconductor integrated circuit device can be suppressed to a low value. That is, since the voltage of the high-potential side power supply VDD does not drop, power supply noise does not occur and malfunction of the internal circuit is not induced.

Further, even when the output data of all output bits of the semiconductor integrated circuit device is switched from the L level to the H level, each MOS transistor on the pull-down side (not shown) operates in the same manner as described above, and the semiconductor integrated circuit. The peak value of the output current of the device can be kept low. That is, since the ground potential does not rise, power supply noise does not occur and malfunction of the internal circuit is not induced.

[0022]

However, the above-mentioned two methods (reducing the transistor size of the inverter circuit for driving the output transistor, providing a plurality of output transistors in parallel, and providing a time difference between the rising edges of the respective gate voltages). In (), while the peak value of the output current of the output buffer circuit can be reduced, the rise of the output current also becomes gentle. As a result, it takes a long time to determine the level of output data, which causes a problem that access time becomes long and high-speed operation is hindered.

The present invention has been made to solve the above problems, and its purpose is to appropriately adjust the rising of the output current to suppress the peak current without hindering the high-speed operation and to suppress the power supply. An object of the present invention is to provide an output buffer circuit capable of suppressing fluctuations in voltage.

[0024]

FIG. 1 illustrates the principle of the present invention. The gates of the transistors 1 connected in parallel are common, and the output data of the internal circuit is input to each gate. Then, each transistor 1 constitutes a first transistor group 2. Further, the gates of the transistors 3 connected in parallel are common, and each transistor 3 constitutes a second transistor group 4. The two transistor groups 2 and 4 are connected in parallel with the power supply VDD.

The voltage control circuit 5 includes a second transistor group 4 when the level of the output data of the internal circuit is switched.
Gate voltage of the first transistor group 2 is changed simultaneously with the gate voltage of the first transistor group 2 for a predetermined time. Subsequently, the voltage control circuit 5 holds the gate voltage of the second transistor group 4 as it is for a certain period of time. After that, the voltage control circuit 5
Changes the gate voltage of the second transistor group 4 in accordance with the gate voltage of the first transistor group 2.

Then, the output data of the internal circuit is output to the external circuit through the first and second transistor groups 2 and 4.

[0027]

Therefore, when the level of the output data of the internal circuit is switched, the gate voltage of each of the transistor groups 2 and 4 simultaneously changes until a fixed time. After a lapse of a certain time, the gate voltage of the first transistor group 2 continues to change until it reaches the level of the output data of the internal circuit. On the other hand, the gate voltage of the second transistor group 2 is maintained as it is. After that, when a certain period of time elapses, the gate voltage of the second transistor group 2 changes until reaching the level of the output data of the internal circuit.

As a result, the peak of the output current of the second transistor group 4 is delayed from the peak of the output current of the first transistor group 2 by the time difference of the rise of the gate voltage of each transistor group. Therefore, the peak value of the output current of the output buffer circuit can be suppressed low.

Further, during the above-mentioned fixed time, the respective gate voltages of the respective transistor groups 2 and 4 simultaneously change, so that the respective output currents simultaneously rise. Then, each transistor group 2,
The output current of the output buffer circuit, which is the sum of the output currents of No. 4, rises rapidly. Therefore, the time required until the level of the output data output to the external circuit is determined can be shortened.

The rise of the output current of the output buffer circuit can be adjusted by changing the number of the transistors 1 and 3.

[0031]

Embodiment An embodiment embodying the present invention will now be described with reference to FIG.
It will be described with reference to FIG. FIG. 2 shows a totem pole output type output buffer circuit of this embodiment.

Note that FIG. 2 shows only the pull-up side, and the pull-down side has the same configuration as the pull-up side and is only mirror-reversed, so it is omitted.
The N-channel MOS transistors 21 have the same transistor size and are connected in parallel. Also, each N-channel MOS transistor 22 has the same transistor size and is connected in parallel by the same number as the MOS transistor 21. The drains of both MOS transistors 21 and 22 are connected to the high-potential power supply VDD, and the sources are connected to the drains of the pull-down MOS transistors (not shown).
Input data transmitted from an internal circuit via a bus (not shown) is input to the gate of each MOS transistor 21 via an inverter circuit 23, and each MOS transistor via an inverter circuit 24 and a CMOS transmission gate 25. It is input to the gate of 22.

The output of the inverter circuit 23 is input to one of the input terminals A of the NAND circuit 26, and at the same time, 3
It is input to the other input terminal B of the NAND circuit 26 via the individual inverter circuits 27. The output of the NAND circuit 26 is
N channel M that constitutes the transmission gate 25
It is input to the gate of the OS transistor and also input to the gate of the P-channel MOS transistor forming the transmission gate 25 via the inverter circuit 28. Therefore, when the output of the NAND circuit 26 is H level (the output of the inverter circuit 28 is L level), the transmission gate 25 is opened.

Then, both MOS transistors 21, 22
The output data is output from the source. The signal delay times t3 of the respective inverter circuits 23, 24 and 27 are set to be equal.

Next, the operation of this embodiment thus constructed will be described. When the input data is at H level, the output of each inverter circuit 23, 24 becomes L level,
The transistor 21 is turned off. At this time, NAND circuit 2
Since the input terminal B of 6 becomes the H level and the input terminal A becomes the L level, the output of the NAND circuit 26 becomes the H level (the output of the inverter circuit 28 is the L level), and the transmission gate 25 is opened. The L level output of the inverter circuit 24 is input to the gate of each MOS transistor 22 via the opened transmission gate 25, and each MOS transistor 22 is turned off.

Then, when the input data is switched from the H level to the L level, the gate of each MOS transistor 21 and the input terminal A of the NAND circuit 26 are delayed by the signal delay time t3 of the inverter circuit 23 and set to the H level. A level signal is applied. Further, the input terminal B of the NAND circuit 26 has an inverter circuit 23 and three inverter circuits 2
The L level signal is applied with a delay of the sum of the signal delay times of 7 (4 × t3).

Therefore, until the time (4 × t3) elapses after the input data is switched from the H level to the L level (after the output of each inverter circuit 23, 24 becomes the H level, the time (3 × Until t3) has elapsed), the input terminal B of the NAND circuit 26 is maintained at the H level.

Then, the input terminals A and B of the NAND circuit 26
Both become H level, the output of the NAND circuit 26 becomes H level.
The level is switched to the L level, but it takes a signal delay time t4 of the NAND circuit 26 until the level is switched. That is, the output of the NAND circuit 26 is kept at the H level and the transmission gate 25 is kept open until the time t4 elapses after the output of the inverter circuit 23 becomes the H level.

Therefore, the H level signal is applied to the gate of each MOS transistor 22 via the open transmission gate 25 with a delay of the signal delay time t3 of the inverter circuit 24.

Therefore, until the time t4 elapses after the output of each inverter circuit 23, 24 becomes H level, each gate voltage G of each MOS transistor 21, 22.
21, G22 will stand up at the same time.

Then, the time t4 elapses, and the NAND circuit 2
When the output of 6 switches from the H level to the L level, the transmission gate 25 will be closed. Then, no charge is supplied to the gate of each MOS transistor 22, and the gate voltage G22 of each MOS transistor 22 is maintained at the time when the transmission gate 25 was closed.

On the other hand, since the electric charge is continuously supplied to the gate of each MOS transistor 21, the gate voltage G21 of each MOS transistor 21 continues to increase until it reaches the level of the input data.

After that, when the time (3.times.t3) elapses after the outputs of the respective inverter circuits 23 and 24 become H level, the input terminal B of the NAND circuit 26 becomes L level. At this time, since the input terminal A of the NAND circuit 26 is at the H level, the output of the NAND circuit 26 becomes at the H level and the transmission gate 25 is opened again. Then, the charges are supplied again to the gates of the respective MOS transistors 22, so that the gate voltage G22 of the respective MOS transistors 22 continues to rise until reaching the level of the input data.

FIG. 3 shows the sum current I21 of the gate voltages G21 and G22 of the MOS transistors 21 and 22 and the drain currents of the MOS transistors 21 and 22 when the input data is switched from the H level to the L level. , I2
2 and the output current of the output buffer circuit (each sum current I2
1, the sum of I22 [I21 + I22]) shows the time shift of IOUT.

Each gate voltage G21, G22 rises to increase each MO
Exceeding the threshold voltage of S-transistors 21 and 22, each M
When the OS transistors 21 and 22 are turned on, the sum currents I21 and I22 reach their peaks. However, the peak value of each sum current I21, I22 is the output current I shown in FIG.
The value is smaller than the peak value of 41. Further, the peak of the sum current I22 is higher than that of the sum current I21 by the above M values.
Time difference of rising of the OS transistors 21 and 22 (3
Xt3-t4). Therefore, the peak value of the output current IOUT of the output buffer circuit is smaller than the peak value of the output current I41 shown in FIG.

Then, during the above-mentioned constant time (t4), since the respective gate voltages G21 and G22 rise together, the respective sum currents I2
1, 122 also rise at the same time, and the rising edge of the output current IOUT becomes steeper than the rising edge of the output current IO shown in FIG.

As described above, in this embodiment, even if the output data of all output bits of the semiconductor integrated circuit device is switched from the H level to the L level, the peak value of the output current can be kept low. In addition, the output current is constant (t
Since it rapidly rises by 4), the time required until the output data level is determined can be shortened, the access time can be shortened, and high-speed operation can be performed.

Further, even when the output data of all output bits of the semiconductor integrated circuit device is switched from the L level to the H level, each MOS transistor on the pull-down side (not shown) operates in the same manner as described above to output the output current. The peak value can be suppressed to a low level, and the output current can be rapidly raised to achieve high-speed operation.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) The signal delay times of the inverter circuits 23, 24, 27 are not the same but different values.

2) The number of each MOS transistor 21, 22 is not the same but is changed appropriately. Further, the transistor sizes of the MOS transistors 21 and 22 are not the same but are appropriately changed. As a result, the rise of each sum current I21, I22 can be adjusted appropriately, and thus the rise of the output current IOUT can be adjusted arbitrarily.

3) An appropriate number of inverter circuits 27 is used instead of three. As a result, the rise of the gate current G22 can be changed and the rise of the sum current I22 can be adjusted appropriately, so that the rise of the output current IOUT can be arbitrarily adjusted.

4) Regardless of the above embodiment, the gate voltage G22
Use some circuit that can adjust the rising edge of. 5) Not limited to the totem pole output type, it is used for output buffer circuits of other types such as three-state output type, open drain output type and source follower output type.

6) Each N-channel MOS transistor 2
1, 22 are P-channel MOS transistors and JFE
Replace with other transistors such as T, SIT and bipolar transistors.

[0054]

As described in detail above, according to the present invention, by appropriately adjusting the rising of the output current, the peak current can be suppressed and the fluctuation of the power supply voltage can be suppressed without disturbing the high speed operation. There is an excellent effect of being able to provide a possible output buffer circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram of an embodiment embodying the present invention.

FIG. 3 is a waveform diagram showing rise of voltage and current in each part of the embodiment.

FIG. 4 is a circuit diagram of a conventional example.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a waveform diagram showing rise of voltage and current in each part of a conventional example.

FIG. 7 is a waveform diagram showing rise of voltage and current in each part of a conventional example.

[Explanation of symbols]

 1 Transistor 2 1st Transistor Group 3 Transistor 4 2nd Transistor Group 5 Voltage Control Circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (1)

[Claims] 1. A first transistor group (2) comprising one or more transistors (1) connected in parallel with a common gate or base, to which output data of an internal circuit is input. ) And one or more transistors (3) connected in parallel with a common gate or base, and a second transistor connected in parallel to the first transistor group (2) and the power supply (VDD). When the level of the output data of the transistor group (4) and the internal circuit is switched, the gate or base voltage of the second transistor group (4) is changed to the first transistor group (2 ) Gate or base voltage at the same time, and then hold that voltage for a certain period of time.
And a voltage control circuit (5) for changing the gate voltage or the base voltage of the transistor group (2) of (1), and the output data of the internal circuit to the first and second transistor groups (2, 4). An output buffer circuit, which outputs to an external circuit via.