JPH0786896A - Field effect transistor - Google Patents

Abstract

PURPOSE:To provide a field effect transistor which prevents a through current and reduces the power consumption. CONSTITUTION:A PMOS 11 and an NMOS 13 are turned on and off by an input signal VIN which is supplied from an internal logic circuit 16 via an inverter 17 of the precedent stage. The signal VIN is delayed by a group 15 of delaying inverters of an even number of stages and then supplied to the gates of a PMOS 12 and an NMOD 14 as the delayed input signals VDIN of the same code. Therefore the PMOS 12 and the NMOS 14 are turned on and off later than the PMOS 11 and the NMOS 13 by an extent equal to the delay caused by the group 15. Thus the PMOS 11 and 12 and the NMOS 13 and 14 are turned on at a time so that the flow of a through current is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor that suppresses a through current.

[0002]

2. Description of the Related Art A field effect transistor is shown in FIG.
As shown in, the LSI (Large Scale Integrat)
used as the output circuit 1 of the (ion), the PMOS (P channel metal oxide semiconductor) 2 and the NMOS (N
CMOS (Co that incorporates channel MOS) 3 together (Co
mplementary MOS) is used.

This output circuit 1 has its PMOS 2 and NM
The drains of OS3 are commonly connected, and the output pad 6
It is connected to the. The source of the PMOS 2 is connected to the power supply voltage V _DD , and the source of the NMOS 3 is grounded.

The output circuit 1 is inputted to the gates of the PMOS 2 and the NMOS 3 thereof after the input signal V _IN from the internal logic circuit 4 is amplified via the preceding stage inverter group 5, and is output to the output pad 6. Output V _OUT .

In the output circuit 1, as shown in FIG. 5, for example, when the input signal V _IN switches from high (Hi) to low (Low), the PMOS 2 switches from off (off) to on (on). , NMOS3 is switched from ON to OFF, and the power supply voltage V _DD is applied to the output pad 6 by PMO.
It is output via S2. When the input signal V _IN switches from low to high, the PMOS 2 switches from on to off and the NMOS 3 switches from off to on,
The ground voltage is output to the output pad 6 via the NMOS 3.

[0006]

However, such a conventional field effect transistor has a CMOS structure in which one PMOS and one NMOS are connected to each other, and therefore, when the input signal is switched, a through-hole is generated. There is a problem that the current increases and the power consumption increases.

That is, in the output circuit 1 shown in FIG.
If there are variations in the switching characteristics of the PMOS2 and the NMOS3 that compose the CMOS, as shown in FIG. 5, when the input signal V _IN is switched, a deviation occurs between the rising timing and the falling timing of the PMOS2 and the NMOS3, and the PMOS2 and the NMOS3. Then, a period in which both of them are turned on occurs, and a large through current flows. For example, when the input signal V _IN switches from high to low, NMO
When switching characteristics of the S3 is poor, as shown as the waveform of NMOS3 5, delay the fall of NMOS3, both PMOS2 and NMOS3 is period t ₁ ON is generated, the power supply voltage V in the period t _{1 A} large through current flows from _DD to the ground potential. Further, when the input signal V _IN is switched from low to high and the switching characteristics of the PMOS2 are poor, as shown in the waveform of the PMOS2 in FIG. 5,
The fall of PMOS2 is delayed, and PMOS2 and NMOS
A period t _{2 in} which both 3 are on occurs, and during this period t ₂ , a large through current flows from the power supply voltage V _DD to the ground potential.
As a result, there is a problem that the power consumption due to the through current increases.

Therefore, the present invention has been made in view of the above situation, and an object thereof is to provide a field effect transistor capable of reducing power consumption.

[0009]

According to the present invention, a P-channel transistor and an N-channel transistor have their drains connected in common and are turned on / off by an input signal inputted to their gates to turn them on / off. In a field-effect transistor that outputs a corresponding output signal, a switching element is connected in series to the P-channel transistor, a switching element is connected in series to the N-channel transistor, and a switching element is connected to each of these switching elements via a delay element. The above object is achieved by delaying the input signal by a predetermined time and inputting it.

In this case, for example, as described in claim 2, the delay element is composed of an even number of stages of delay inverters, and the switch element connected to the P-channel transistor is a drain of the P-channel transistor. P-channel transistor whose source electrode is connected to the electrode, and the switch element connected to the N-channel transistor is an N-channel transistor whose source electrode is connected to the drain electrode of the N-channel transistor. The drain electrodes of the channel transistors as elements may be connected to each other.

Further, for example, as described in claim 3, the delay element is composed of an odd number of stages of delay inverters, and the switch element connected to the P-channel transistor is a drain electrode of the P-channel transistor. The drain electrode of which is connected to the N-channel transistor, and the switch element connected to the N-channel transistor is a P-channel transistor whose drain electrode is connected to the drain electrode of the N-channel transistor. The source electrodes of the channel transistors may be connected to each other.

[0012]

According to the present invention, P-channel transistors and N-channel transistors are used.
When the falling characteristics of the channel transistors are bad and they turn on / off by an input signal, even if there is a period in which both of these channel transistors are both turned on, the switching elements connected in series with these channel transistors are delayed. Since it is turned on / off by the input signal delayed by the element and input, the P-channel transistor and the N-channel transistor are not short-circuited, a large through current can be prevented from flowing, and power consumption is saved. can do.

[0013]

EXAMPLES The present invention will be specifically described below based on examples.

1 and 2 are views showing an embodiment of the field effect transistor of the present invention. This embodiment is an LSI.
Applied to the output circuit of.

In FIG. 1, the output circuit 10 has two Ps.
MOS11, PMOS12 and two NMOS13, NM
It is composed of the OS 14 and the delay inverter group 15, and the first-stage inverter and PM of the delay inverter group 15 are included.
The internal logic circuit 1 is connected to the gates of the OS 11 and the NMOS 13.
The input signal V _IN from 6 is input via the front stage inverter group 17.

PMOS 11 and PMOS 12 are PMOS
By connecting the drain of 11 and the source of PMOS 12, serial connection is made in two stages.
A positive power supply voltage V _DD is connected to the source of 1.

The NMOS 13 and the NMOS 14 are NMOS
By connecting the drain of 13 and the source of NMOS 14, they are serially connected in two stages.
The source of 3 is grounded.

The drain of the PMOS 12 and the NMOS
The drains of 14 are commonly connected and also connected to the output pad 18.

Further, the gate of the PMOS 12 and the NMOS
14 gates, while being commonly connected, is connected to a delay inverter group 15, the delayed input signal V _{DI N} delayed to the gate of the PMOS12 and NMOS14 through the delay inverter group 15 is input .

The delay inverter group 15 is composed of an even number of inverters, the input signal V _IN causes a predetermined time delay, the input signal V _IN and the same sign of the delayed input signal V _{DI N} PMOS 12 and NMOS14 Output to the gate.

Next, the operation will be described.

In the present embodiment, the field effect transistor is used as the output circuit 10 of the LSI as described above, and the output circuit 10 receives the input signal V _IN from the internal logic circuit 16 via the pre-stage inverter 17. Is entered.

When the input signal V _IN as shown in FIG. 2 is input, the output circuit 10 outputs PMO at the input timing.
The input signal V _IN is input to the gates of S11 and the NMOS 13, and the input signal V _IN is input to the delay inverter group 15.
_IN is input. Since the delay inverter group 15 is composed of an even number of inverters, the delay inverter group 15 delays the input signal V _IN by a predetermined delay time T and, at the same time, delay inputs the same sign as the input signal V _IN input to the PMOS 11 and the NMOS 13. The signal V _DIN is output to the gates of the PMOS 12 and the NMOS 14 after the input signal V _IN is input to the gates of the PMOS 11 and the NMOS 13.

Here, when the input signal V _IN is switched from low to high, the switched input signal V _IN is transferred to the PMOS 11 and the NMOS 13 at this switching timing.
Is input to the gate of, NMOS13 turns on, PMOS
11 turns off. After that, the delayed input signal V _DIN having the same sign delayed by the delay inverter group 15 is input to the PMOS 12 and the NMOS 14, and the NMOS 14 causes the NMOS 1 to operate.
3 is turned on after a delay time T from the on timing of 3, and the PMOS 12 is turned off after a delay time T from the off timing of the PMOS 11.

At this time, even if the switching characteristic of the PMOS 11 is poor and the off timing of the PMOS 11 is delayed for a predetermined time later than the on timing of the NMOS 13, the NMOS 14 is turned on with a delay of the delay time T. By setting the delay time to be longer than the off-timing delay time, N is set after the PMOS 11 turns off.
MOS14 can be turned on and all PMOS1
1, it is possible to prevent the PMOS 12 and the NMOS 13 and the NMOS 14 from being turned on at the same time. At this time, the PMOS 12 is turned off with a delay time T, but when the NMOS 14 is turned on, as described above,
Since the PMOS 11 has already been turned off, the power supply voltage V _DD will not be short-circuited to the ground potential, and a through current can be prevented from flowing. And the PMOS 11 and P
When the MOS 12 is turned off and the NMOS 13 and the NMOS 14 are turned on, the ground potential is output to the output pad 18 as the output signal V _OUT .

That is, in the output circuit 10, as shown in FIG. 2, when the input signal V _IN switches from low to high, the output signal V _OUT switches from high to low with a delay of a predetermined delay time T, The ground potential is output as the output signal V _OUT .

When the input signal V _IN switches from high to low, the switched input signal V _IN is input to the gates of the PMOS 11 and the NMOS 13, and the PMOS 11 turns on and the NMOS 13 turns off at this switching timing. To do. After that, the delay input signal V _DIN delayed by the delay inverter group 15 has the same sign,
It is input to the OS 14, and the PMOS 12 turns on after a delay time T from the on timing of the PMOS 11 to turn on NM.
The OS 14 turns off after a delay time T from the off timing of the NMOS 13.

At this time, even if the switching characteristic of the NMOS 13 is poor and the off timing is delayed for a predetermined time later than the on timing of the PMOS 11, the PMOS 12 is turned on with a delay time T, so that the delay time T depends on the switching characteristic. By setting the delay time longer than the off-timing delay time of, the PMOS 12 can be turned on after the NMOS 13 is turned off.
11, it is possible to prevent the PMOS 12, the NMOS 13, and the NMOS 14 from turning on. Also, at this time,
The NMOS 14 is turned off after a delay time T, but P
When the MOS 12 is turned on, as described above, the NMO
Since S13 has already been turned off, the power supply voltage V _DD is not short-circuited to the ground potential, and it is possible to prevent a through current from flowing. And NMOS 13 and NMOS
14 is turned off and the PMOS 11 and the PMOS 12 are turned on, so that the power supply voltage V _DD is output to the output pad 18 as the output signal V _OUT .

That is, as shown in FIG. 2, when the input signal V _IN switches from high to low, the output circuit 10 switches the output signal V _OUT from low to high with a delay of a predetermined delay time T. The power supply voltage V _DD is output as the output signal V _OUT .

As described above, according to this embodiment, the input signal V _IN can be delayed by the predetermined delay time T, and the ON time of the PMOS 12 and the NMOS 14 can be delayed by the delay time T. Even if the NMOS 13 has a delay in cutoff due to the switch characteristic, all the PMOS 11, PMOS 12, NMOS 13, and NMOS
It is possible to prevent 14 from turning on. As a result, it is possible to prevent the occurrence of shoot-through current and reduce power consumption.

In the output circuit 10 of the above embodiment, the delay inverter group 15 composed of an even number of inverters is used.
Although the PMOS 11 is serially connected to the PMOS 12 and the NMOS 13 is serially connected to the NMOS 14 by using, the present invention is not limited to this, and a delay inverter group composed of an odd number of inverters may be used.

In this case, as shown in FIG. 3, the output circuit 2
For 0, the delay inverter group 21 including an odd number of inverters is used to serially connect the NMOS 22 to the PMOS 11 and the PMOS 23 to the NMOS 13.

In this way, the input signal V _IN is delayed by the odd-numbered delay inverter group 21 and its sign is inverted, so that the delayed input signal V _DIN is NMO.
It is input to S22 and PMOS23. However, PM
Reverse channel NMOS22 and OS13
Since the reverse-channel PMOS 23 is connected to the output circuit 20, the output circuit 20 performs the same operation as that of the above-described embodiment and can obtain the same effect as that of the above-described embodiment.

Further, in each of the above embodiments, the input signal V _IN is delayed by the delay inverter group 15 or the delay inverter group 21, but the invention is not limited to the inverter, and is cut by the switching characteristics of the PMOS 11 and the NMOS 13. Any delay element may be used as long as it can cover the off delay time.

Furthermore, in the above embodiment, the PMOS 12 and the NMOS 14 or the NM are used as the switch elements.
Although the OS 22 and the PMOS 23 are used, the OS 22 and the PMOS 23 are not limited to the MOS transistor, and can be appropriately used as long as they have switch characteristics.

[0036]

According to the present invention, it is possible to prevent the P-channel transistor and the N-channel transistor from being short-circuited and prevent a large through current from flowing. As a result, power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an output circuit to which an embodiment of a field effect transistor according to the present invention is applied.

FIG. 2 is a timing waveform chart of an input signal and an output signal of the output circuit of FIG.

FIG. 3 is a circuit configuration diagram of an output circuit to which another embodiment of the field effect transistor according to the present invention is applied.

FIG. 4 is a circuit configuration diagram of an example of a conventional output circuit.

5 is a signal waveform diagram of an input signal of the output circuit of FIG. 4 and each MOS.

[Explanation of symbols]

 10, 20 Output circuit 11, 12, 23 PMOS 13, 14, 22 NMOS 15, 21 Delay inverter 16 Internal logic circuit 17 Previous stage inverter group 18 Output pad

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 27/092 H03K 17/687 19/0175 19/0948 9473-5J H03K 17/687 F 8321-5J 19/00 101 F 8321-5J 19/094 B

Claims (3)

[Claims] 1. A P-channel transistor and an N-channel transistor, whose drains are commonly connected to each other, are turned on / off by an input signal input to their gates, and output an output signal corresponding to the on / off. In the field effect transistor, a switch element is connected in series to the P-channel transistor, a switch element is connected in series to the N-channel transistor, and the input signal is delayed by a delay element to each of these switch elements for a predetermined time. A field effect transistor characterized in that it is input as an input. 2. A P-channel transistor in which the delay element comprises an even number of stages of delay inverters, and a switch element connected to the P-channel transistor has a drain electrode of the P-channel transistor connected to a source electrode thereof. The switch element connected to the N-channel transistor is an N-channel transistor in which the source electrode is connected to the drain electrode of the N-channel transistor, and the drain electrodes of the channel transistors as these switch elements are connected to each other. The field effect transistor according to claim 1, characterized in that: 3. The N-channel transistor in which the delay element is composed of an odd number of stages of delay inverters, and the switch element connected to the P-channel transistor has a drain electrode connected to the drain electrode of the P-channel transistor. The switch element connected to the N-channel transistor is a P-channel transistor in which the drain electrode is connected to the drain electrode of the N-channel transistor, and the source electrodes of the channel transistors as these switch elements are connected to each other. The field effect transistor according to claim 1, characterized in that: