JPS5977694A - Information processor - Google Patents

Abstract

PURPOSE:To attain the coupled use and protection of plural segments by generating a signal when the starting segment No. of the operated and coupled segments is larger than the starting No. of segments to be coupled. CONSTITUTION:The contents of a base register 2 and an index register 3 which correspond to the set contents of an instruction register 1 are added by an adder 4 and the added result is set up in an address register 6. In accordance with the segment No. address of a segmentation effective address, an address conversion buffer 7 is indexed. The segment starting point address of from the buffer 7 and the address the register 6 are added and a coupled address or the like is set up in a register 12. If the starting point segment No. from the buffer 7 is smaller than the segment No. of information to be operated from the register 5, access inhibiting state is formed through a comparator 8, an OR gate 10 and an exclusive processing part 14. Said constitution makes it possible to use plural segments by coupling them and protect them properly.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an information processing apparatus that connects and utilizes a plurality of segments of a storage device.

BACKGROUND TECHNOLOGY Conventionally, in this type of information processing device, the content of the letter pace register specified by an instruction, the intra-segment address in the base register and the displacement field of the instruction in the process of generating a segmented effective address by displacing the instruction. The segment number in the base register is used as it is as the segment number of the segmented effective address. Therefore, segments other than the segment specified by the base register cannot be accessed. The disadvantage is that it is not possible to process a large amount of data by concatenating several segments.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an information processing device that connects a plurality of segments to enable use of C and further protects the connected segments. 1 Structure of the Invention The device of the present invention converts segmented address information consisting of an n-bit segment number field and an m-bit intra-segment address field into n+m-bit operands, with the upper digits being the segment number and the lower digits being the intra-segment address. means for calculating C as information; means for holding a segment number serving as the starting point of a group of connected segments including the segment corresponding to the segment number indicated by the upper n bits of the output of the calculating means; Top n of the operand information
and means for generating a signal when the segment number is greater than the segment number indicated by the bit.

Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an instruction code;
Instruction register 1 for storing instructions having a pace register number field, an index register number field and a displacement field. Base register 2. Index register 3. Addition circuit 4. Base segment register5. Address register 6, address translation buffer 7, comparison circuits 8 and 9. OR gate 10
゜Addition circuit 11. Address register 12. Non-zero detection circuit 13. and an exception handling section '14.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, in response to the setting of an instruction to instruction register 1, the operation traversed by the instruction code is initiated. When the instruction requires a memory operand, the contents of base register 2 specified by the base register number field of instruction register 1, the contents of index register 3 specified by the index register number field, and the displacement field. The contents are added by the adder circuit 4 and set in the address register 6. In this addition operation, segment No. 11 (8EG) of base register 2 shown in Fig. 2 and intra-segment address (A) are treated as one continuous data, and the upper digits of the data are expanded with zero. . Also, instruction register 1
The zero is also expanded to the upper digits of (displacement) (IJ). These data and the index (INDEX) of the index register 3 are added and set in the address register 6.

The output of the base register 2 shown in FIG. The address translation buffer 7 is indexed according to the contents of the segment number field of the segmented effective address set in the address register 6. The address translation buffer 7 is composed of an associative memory, and stores the contents of the segment descriptor of the segment corresponding to the contents of the segment number field.

Specifically, an address indicating the starting point of the segment, a size indicating the size of the segment, information indicating the attribute of the segment, and a starting point segment number of a group of connected segments including the segment are stored. The address indicating the starting point of the segment output from the address translation buffer is added to the intra-segment address of the address register 6 by an adder circuit 11 and set in the address register 12. The segment size of the output of the address conversion buffer 7 is compared with the intra-segment address of the address register 6 by a comparison circuit 9. A signal is sent to logical locate 10 when the intra-segment address is greater than the segment size.

The starting point segment a of the concatenated segment group output from the address conversion buffer is compared with the base segment number register 5 in the comparison circuit 8, and the pace segment number and starting point segmentation digit are given to the non-zero detection circuit 13, When the zero detection circuit 13 detects a non-zero, a signal is sent to the OR gate 10. The output of the OR gate 10 is given to an exception handling section 14. The exception handling unit 14 handles the gate 1
In response to an input signal from 0, 'C access is stopped and the program is notified of this if necessary.0 Referring to Figure 3, segment descriptors 30 to 35 are defined corresponding to segments 20 to 25, and the starting point of the segment is It consists of an address 3d, size 3c, attribute 3b, and starting segment number 3a field. 8DQ in Figure 3
indicates a segment descriptor 30 corresponding to segment 20. Similarly, Sn2 indicates the segment descriptor 35 of segment 5. In this example, segment O is a single segment, segments 1, 2 . and 3. A connected segment that connects three segments, segment 4. and 5 each indicate a connected segment in which two segments are connected. Now segment 1 in base register
is specified and as a result of address generation, segment 3 is pointed to by the segmented effective address. As a result, the segment descriptor 8D3 of segment 3 is read and the starting point address and the intra-segment address of the segmented effective address are added to obtain the real address. At this time, the intra-segment address and size of the segmented effective address are compared to check whether the intra-segment address is equal to or smaller than the size. 'Also, the segment number and segment descriptor SD3 indicated by the base register
is compared with the starting segment number to check whether the segment number is equal to or greater than the starting segment pot number. In the example of FIG. 3, access to the segment is permitted because the conditions are met. Here, it is assumed that the pace register indicates segment 0 and the segmented effective address indicates segment 3. Since the starting segment number of the segment descriptor 8D3 is 1 and the segment number indicated by the pace register is 00, access to segment 3 is prohibited.

The segment descriptor is normally stored in the address translation buffer 7 of FIG. If the segment descriptor of the designated segment is not stored in the address translation buffer 7, the corresponding segment descriptor is read from the storage section and stored in the address translation buffer 7.

Effects of the Invention The present invention has the advantage that segments of a count can be linked and accessed as if they were two segments of a large size.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the addition method of the adder circuit shown in FIG. 1, and FIG. 3 is a diagram showing connected segments. 1 to 3, 1...instruction register, 2...pace register, 3°゛°°゛° index register, 4...addition circuit, 5...
... Base segment register, 6 ... Address register, 7 ... Address conversion buffer, 8 ... Comparison circuit, 9 ... Comparison circuit,
10...OR gate, 11...Addition circuit, 12...Address register, 13.°°
・°°Non-zero detection circuit, 14...Exception handling section, 2
0-25...Segmentation effect 3a...Start segment number, 3b...
・Segment attribute, 3c...Segment size, 3d・°・pa. v;1 DaZ? B

Claims (1)

[Claims] means for calculating segmented address information consisting of an n-bit segment number field and an m-bit intra-segment address field as n0m-bit operand information, with the upper field as the segment number and the lower field as the intra-segment address; means for holding a segment number serving as a starting point of a connected segment group including a segment corresponding to a segment number indicated by the upper n bits of the output of the calculation means; and a segment number serving as the starting point is the upper n bits of the operand information. An information processing device comprising: means for generating a signal when the segment number is thicker than the indicated segment number.